2020-01-26 19:51:34 +01:00
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/*
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* QEMU AVR CPU
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*
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* Copyright (c) 2019-2020 Michael Rolnik
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/qemu-print.h"
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#include "exec/exec-all.h"
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#include "cpu.h"
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#include "disas/dis-asm.h"
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static void avr_cpu_set_pc(CPUState *cs, vaddr value)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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cpu->env.pc_w = value / 2; /* internally PC points to words */
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}
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static bool avr_cpu_has_work(CPUState *cs)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
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&& cpu_interrupts_enabled(env);
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}
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2020-10-29 20:30:01 +01:00
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static void avr_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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2020-01-26 19:51:34 +01:00
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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env->pc_w = tb->pc / 2; /* internally PC points to words */
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}
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static void avr_cpu_reset(DeviceState *ds)
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{
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CPUState *cs = CPU(ds);
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AVRCPU *cpu = AVR_CPU(cs);
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AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
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CPUAVRState *env = &cpu->env;
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mcc->parent_reset(ds);
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env->pc_w = 0;
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env->sregI = 1;
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env->sregC = 0;
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env->sregZ = 0;
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env->sregN = 0;
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env->sregV = 0;
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env->sregS = 0;
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env->sregH = 0;
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env->sregT = 0;
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env->rampD = 0;
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env->rampX = 0;
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env->rampY = 0;
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env->rampZ = 0;
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env->eind = 0;
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env->sp = 0;
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env->skip = 0;
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memset(env->r, 0, sizeof(env->r));
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}
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static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->mach = bfd_arch_avr;
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2020-01-24 01:51:16 +01:00
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info->print_insn = avr_print_insn;
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2020-01-26 19:51:34 +01:00
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}
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static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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mcc->parent_realize(dev, errp);
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}
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static void avr_cpu_set_int(void *opaque, int irq, int level)
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{
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AVRCPU *cpu = opaque;
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CPUAVRState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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uint64_t mask = (1ull << irq);
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if (level) {
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env->intsrc |= mask;
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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env->intsrc &= ~mask;
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if (env->intsrc == 0) {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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}
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static void avr_cpu_initfn(Object *obj)
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{
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AVRCPU *cpu = AVR_CPU(obj);
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cpu_set_cpustate_pointers(cpu);
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/* Set the number of interrupts supported by the CPU. */
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qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
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sizeof(cpu->env.intsrc) * 8);
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}
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static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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oc = object_class_by_name(cpu_model);
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if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
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object_class_is_abstract(oc)) {
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oc = NULL;
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}
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return oc;
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}
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static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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AVRCPU *cpu = AVR_CPU(cs);
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CPUAVRState *env = &cpu->env;
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int i;
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qemu_fprintf(f, "\n");
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2020-03-30 11:30:27 +02:00
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qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2); /* PC points to words */
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2020-01-26 19:51:34 +01:00
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qemu_fprintf(f, "SP: %04x\n", env->sp);
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qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16);
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qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16);
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qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16);
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qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16);
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qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16);
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qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]);
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qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]);
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qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]);
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qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n",
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env->sregI ? 'I' : '-',
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env->sregT ? 'T' : '-',
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env->sregH ? 'H' : '-',
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env->sregS ? 'S' : '-',
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env->sregV ? 'V' : '-',
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env->sregN ? '-' : 'N', /* Zf has negative logic */
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env->sregZ ? 'Z' : '-',
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env->sregC ? 'I' : '-');
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qemu_fprintf(f, "SKIP: %02x\n", env->skip);
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qemu_fprintf(f, "\n");
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for (i = 0; i < ARRAY_SIZE(env->r); i++) {
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qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]);
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if ((i % 8) == 7) {
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qemu_fprintf(f, "\n");
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}
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}
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qemu_fprintf(f, "\n");
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}
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2021-05-17 12:51:31 +02:00
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps avr_sysemu_ops = {
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2021-05-17 12:51:37 +02:00
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.get_phys_page_debug = avr_cpu_get_phys_page_debug,
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2021-05-17 12:51:31 +02:00
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};
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2021-02-04 17:39:23 +01:00
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#include "hw/core/tcg-cpu-ops.h"
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2021-02-28 00:21:17 +01:00
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static const struct TCGCPUOps avr_tcg_ops = {
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2021-02-04 17:39:23 +01:00
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.initialize = avr_cpu_tcg_init,
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.synchronize_from_tb = avr_cpu_synchronize_from_tb,
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.cpu_exec_interrupt = avr_cpu_exec_interrupt,
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.tlb_fill = avr_cpu_tlb_fill,
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.do_interrupt = avr_cpu_do_interrupt,
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};
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2020-01-26 19:51:34 +01:00
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static void avr_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
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2021-02-01 09:03:48 +01:00
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device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
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2020-01-26 19:51:34 +01:00
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device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset);
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cc->class_by_name = avr_cpu_class_by_name;
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cc->has_work = avr_cpu_has_work;
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cc->dump_state = avr_cpu_dump_state;
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cc->set_pc = avr_cpu_set_pc;
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2021-05-17 12:51:30 +02:00
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dc->vmsd = &vms_avr_cpu;
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2021-05-17 12:51:31 +02:00
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cc->sysemu_ops = &avr_sysemu_ops;
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2020-01-26 19:51:34 +01:00
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cc->disas_set_info = avr_cpu_disas_set_info;
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2020-01-26 18:52:23 +01:00
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cc->gdb_read_register = avr_cpu_gdb_read_register;
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cc->gdb_write_register = avr_cpu_gdb_write_register;
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2021-07-20 17:48:46 +02:00
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cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint;
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2020-01-26 18:52:23 +01:00
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cc->gdb_num_core_regs = 35;
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cc->gdb_core_xml_file = "avr-cpu.xml";
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2021-02-04 17:39:23 +01:00
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cc->tcg_ops = &avr_tcg_ops;
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2020-01-26 19:51:34 +01:00
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}
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2020-01-26 18:34:33 +01:00
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/*
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* Setting features of AVR core type avr5
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* --------------------------------------
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*
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* This type of AVR core is present in the following AVR MCUs:
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*
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* ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c,
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* ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162,
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* atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a,
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* atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa,
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* atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb,
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* atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323,
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* atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p,
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* atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
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* atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa,
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* atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1,
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* atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644,
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* atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p,
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* atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p,
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* atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p,
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* atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2,
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* atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216,
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* at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000
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*/
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static void avr_avr5_initfn(Object *obj)
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{
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AVRCPU *cpu = AVR_CPU(obj);
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CPUAVRState *env = &cpu->env;
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set_avr_feature(env, AVR_FEATURE_LPM);
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set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
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set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
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set_avr_feature(env, AVR_FEATURE_SRAM);
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set_avr_feature(env, AVR_FEATURE_BREAK);
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set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
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set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
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set_avr_feature(env, AVR_FEATURE_JMP_CALL);
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set_avr_feature(env, AVR_FEATURE_LPMX);
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set_avr_feature(env, AVR_FEATURE_MOVW);
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set_avr_feature(env, AVR_FEATURE_MUL);
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}
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/*
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* Setting features of AVR core type avr51
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* --------------------------------------
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*
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* This type of AVR core is present in the following AVR MCUs:
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*
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* atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p,
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* atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
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* at90usb1287
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*/
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static void avr_avr51_initfn(Object *obj)
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{
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AVRCPU *cpu = AVR_CPU(obj);
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CPUAVRState *env = &cpu->env;
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set_avr_feature(env, AVR_FEATURE_LPM);
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set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
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set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
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set_avr_feature(env, AVR_FEATURE_SRAM);
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set_avr_feature(env, AVR_FEATURE_BREAK);
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set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
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set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
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set_avr_feature(env, AVR_FEATURE_RAMPZ);
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set_avr_feature(env, AVR_FEATURE_ELPMX);
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set_avr_feature(env, AVR_FEATURE_ELPM);
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set_avr_feature(env, AVR_FEATURE_JMP_CALL);
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set_avr_feature(env, AVR_FEATURE_LPMX);
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set_avr_feature(env, AVR_FEATURE_MOVW);
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set_avr_feature(env, AVR_FEATURE_MUL);
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}
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/*
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* Setting features of AVR core type avr6
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* --------------------------------------
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*
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* This type of AVR core is present in the following AVR MCUs:
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*
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* atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2
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*/
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static void avr_avr6_initfn(Object *obj)
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{
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AVRCPU *cpu = AVR_CPU(obj);
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CPUAVRState *env = &cpu->env;
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set_avr_feature(env, AVR_FEATURE_LPM);
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set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
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set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
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set_avr_feature(env, AVR_FEATURE_SRAM);
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set_avr_feature(env, AVR_FEATURE_BREAK);
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set_avr_feature(env, AVR_FEATURE_3_BYTE_PC);
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set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
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set_avr_feature(env, AVR_FEATURE_RAMPZ);
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set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL);
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set_avr_feature(env, AVR_FEATURE_ELPMX);
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set_avr_feature(env, AVR_FEATURE_ELPM);
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set_avr_feature(env, AVR_FEATURE_JMP_CALL);
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set_avr_feature(env, AVR_FEATURE_LPMX);
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set_avr_feature(env, AVR_FEATURE_MOVW);
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set_avr_feature(env, AVR_FEATURE_MUL);
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}
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typedef struct AVRCPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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} AVRCPUInfo;
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static void avr_cpu_list_entry(gpointer data, gpointer user_data)
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{
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const char *typename = object_class_get_name(OBJECT_CLASS(data));
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qemu_printf("%s\n", typename);
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}
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void avr_cpu_list(void)
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{
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GSList *list;
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list = object_class_get_list_sorted(TYPE_AVR_CPU, false);
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g_slist_foreach(list, avr_cpu_list_entry, NULL);
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g_slist_free(list);
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}
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#define DEFINE_AVR_CPU_TYPE(model, initfn) \
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{ \
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.parent = TYPE_AVR_CPU, \
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.instance_init = initfn, \
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.name = AVR_CPU_TYPE_NAME(model), \
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}
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static const TypeInfo avr_cpu_type_info[] = {
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{
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.name = TYPE_AVR_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(AVRCPU),
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.instance_init = avr_cpu_initfn,
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.class_size = sizeof(AVRCPUClass),
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.class_init = avr_cpu_class_init,
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.abstract = true,
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},
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DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
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DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
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DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
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};
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DEFINE_TYPES(avr_cpu_type_info)
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