2016-11-08 07:00:35 +01:00
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/*
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2019-10-04 01:03:54 +02:00
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* QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface)
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2016-11-08 07:00:35 +01:00
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*
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* Copyright (c) 2003-2005, 2007 Jocelyn Mayer
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* Copyright (c) 2013 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2019-05-23 16:35:07 +02:00
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2016-11-08 07:00:35 +01:00
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#include "qemu/osdep.h"
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#include "hw/isa/isa.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2019-10-04 01:03:54 +02:00
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#include "hw/rtc/m48t59.h"
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2016-11-08 07:00:35 +01:00
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#include "m48t59-internal.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2016-11-08 07:00:35 +01:00
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#define TYPE_M48TXX_ISA "isa-m48txx"
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#define M48TXX_ISA_GET_CLASS(obj) \
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OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
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#define M48TXX_ISA_CLASS(klass) \
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OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
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#define M48TXX_ISA(obj) \
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OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
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typedef struct M48txxISAState {
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ISADevice parent_obj;
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M48t59State state;
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uint32_t io_base;
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MemoryRegion io;
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} M48txxISAState;
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typedef struct M48txxISADeviceClass {
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ISADeviceClass parent_class;
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M48txxInfo info;
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} M48txxISADeviceClass;
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static M48txxInfo m48txx_isa_info[] = {
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{
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.bus_name = "isa-m48t59",
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.model = 59,
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.size = 0x2000,
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}
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};
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Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
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int base_year, int model)
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{
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DeviceState *dev;
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int i;
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for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
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if (m48txx_isa_info[i].size != size ||
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m48txx_isa_info[i].model != model) {
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continue;
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}
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dev = DEVICE(isa_create(bus, m48txx_isa_info[i].bus_name));
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qdev_prop_set_uint32(dev, "iobase", io_base);
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qdev_prop_set_int32(dev, "base-year", base_year);
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qdev_init_nofail(dev);
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return NVRAM(dev);
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}
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assert(false);
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return NULL;
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}
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static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
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{
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M48txxISAState *d = M48TXX_ISA(obj);
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return m48t59_read(&d->state, addr);
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}
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static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
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{
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M48txxISAState *d = M48TXX_ISA(obj);
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m48t59_write(&d->state, addr, val);
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}
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static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
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{
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M48txxISAState *d = M48TXX_ISA(obj);
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m48t59_toggle_lock(&d->state, lock);
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}
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static Property m48t59_isa_properties[] = {
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DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
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DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void m48t59_reset_isa(DeviceState *d)
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{
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M48txxISAState *isa = M48TXX_ISA(d);
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M48t59State *NVRAM = &isa->state;
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m48t59_reset_common(NVRAM);
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}
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static void m48t59_isa_realize(DeviceState *dev, Error **errp)
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{
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M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
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ISADevice *isadev = ISA_DEVICE(dev);
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M48txxISAState *d = M48TXX_ISA(dev);
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M48t59State *s = &d->state;
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s->model = u->info.model;
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s->size = u->info.size;
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isa_init_irq(isadev, &s->IRQ, 8);
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m48t59_realize_common(s, errp);
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memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
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if (d->io_base != 0) {
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isa_register_ioport(isadev, &d->io, d->io_base);
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}
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}
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static void m48txx_isa_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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NvramClass *nc = NVRAM_CLASS(klass);
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dc->realize = m48t59_isa_realize;
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dc->reset = m48t59_reset_isa;
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2020-01-10 16:30:32 +01:00
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device_class_set_props(dc, m48t59_isa_properties);
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2016-11-08 07:00:35 +01:00
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nc->read = m48txx_isa_read;
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nc->write = m48txx_isa_write;
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nc->toggle_lock = m48txx_isa_toggle_lock;
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}
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static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
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{
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M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
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M48txxInfo *info = data;
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u->info = *info;
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}
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static const TypeInfo m48txx_isa_type_info = {
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.name = TYPE_M48TXX_ISA,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(M48txxISAState),
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.abstract = true,
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.class_init = m48txx_isa_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_NVRAM },
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{ }
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}
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};
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static void m48t59_isa_register_types(void)
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{
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TypeInfo isa_type_info = {
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.parent = TYPE_M48TXX_ISA,
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.class_size = sizeof(M48txxISADeviceClass),
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.class_init = m48txx_isa_concrete_class_init,
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};
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int i;
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type_register_static(&m48txx_isa_type_info);
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for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
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isa_type_info.name = m48txx_isa_info[i].bus_name;
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isa_type_info.class_data = &m48txx_isa_info[i];
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type_register(&isa_type_info);
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}
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}
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type_init(m48t59_isa_register_types)
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