2016-06-29 13:47:03 +02:00
|
|
|
#ifndef QEMU_MIPS_DEFS_H
|
|
|
|
#define QEMU_MIPS_DEFS_H
|
2005-07-02 16:58:51 +02:00
|
|
|
|
2007-12-25 21:46:56 +01:00
|
|
|
/* Real pages are variable size... */
|
2006-12-06 18:42:40 +01:00
|
|
|
#define MIPS_TLB_MAX 128
|
2005-07-02 16:58:51 +02:00
|
|
|
|
2018-10-16 12:09:54 +02:00
|
|
|
/*
|
|
|
|
* bit definitions for insn_flags (ISAs/ASEs flags)
|
|
|
|
* ------------------------------------------------
|
|
|
|
*/
|
|
|
|
/*
|
2020-06-02 04:39:15 +02:00
|
|
|
* bits 0-23: MIPS base instruction sets
|
2018-10-16 12:09:54 +02:00
|
|
|
*/
|
|
|
|
#define ISA_MIPS1 0x0000000000000001ULL
|
|
|
|
#define ISA_MIPS2 0x0000000000000002ULL
|
2020-12-16 12:41:25 +01:00
|
|
|
#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
|
2018-10-16 12:09:54 +02:00
|
|
|
#define ISA_MIPS4 0x0000000000000008ULL
|
|
|
|
#define ISA_MIPS5 0x0000000000000010ULL
|
2020-12-16 12:26:56 +01:00
|
|
|
#define ISA_MIPS_R1 0x0000000000000020ULL
|
2020-12-16 12:29:00 +01:00
|
|
|
#define ISA_MIPS_R2 0x0000000000000040ULL
|
2020-12-16 12:29:34 +01:00
|
|
|
#define ISA_MIPS_R3 0x0000000000000080ULL
|
2020-12-16 12:30:11 +01:00
|
|
|
#define ISA_MIPS_R5 0x0000000000000100ULL
|
2020-12-16 12:34:42 +01:00
|
|
|
#define ISA_MIPS_R6 0x0000000000000200ULL
|
2018-10-16 12:09:54 +02:00
|
|
|
#define ISA_NANOMIPS32 0x0000000000008000ULL
|
|
|
|
/*
|
2020-06-02 04:39:15 +02:00
|
|
|
* bits 24-39: MIPS ASEs
|
2018-10-16 12:09:54 +02:00
|
|
|
*/
|
2020-06-02 04:39:15 +02:00
|
|
|
#define ASE_MIPS16 0x0000000001000000ULL
|
|
|
|
#define ASE_MIPS3D 0x0000000002000000ULL
|
|
|
|
#define ASE_MDMX 0x0000000004000000ULL
|
|
|
|
#define ASE_DSP 0x0000000008000000ULL
|
|
|
|
#define ASE_DSP_R2 0x0000000010000000ULL
|
|
|
|
#define ASE_DSP_R3 0x0000000020000000ULL
|
|
|
|
#define ASE_MT 0x0000000040000000ULL
|
|
|
|
#define ASE_SMARTMIPS 0x0000000080000000ULL
|
|
|
|
#define ASE_MICROMIPS 0x0000000100000000ULL
|
2018-10-16 12:09:54 +02:00
|
|
|
/*
|
2020-06-02 04:39:15 +02:00
|
|
|
* bits 40-51: vendor-specific base instruction sets
|
2018-10-16 12:09:54 +02:00
|
|
|
*/
|
2020-06-02 04:39:15 +02:00
|
|
|
#define INSN_VR54XX 0x0000010000000000ULL
|
|
|
|
#define INSN_R5900 0x0000020000000000ULL
|
|
|
|
#define INSN_LOONGSON2E 0x0000040000000000ULL
|
|
|
|
#define INSN_LOONGSON2F 0x0000080000000000ULL
|
|
|
|
#define INSN_LOONGSON3A 0x0000100000000000ULL
|
2018-10-16 12:09:54 +02:00
|
|
|
/*
|
2020-06-02 04:39:15 +02:00
|
|
|
* bits 52-63: vendor-specific ASEs
|
2018-10-16 12:09:54 +02:00
|
|
|
*/
|
2020-06-14 10:00:47 +02:00
|
|
|
/* MultiMedia Instructions defined by R5900 */
|
2020-06-02 04:39:15 +02:00
|
|
|
#define ASE_MMI 0x0010000000000000ULL
|
2020-06-14 10:00:47 +02:00
|
|
|
/* MIPS eXtension/enhanced Unit defined by Ingenic */
|
2020-06-02 04:39:15 +02:00
|
|
|
#define ASE_MXU 0x0020000000000000ULL
|
2020-06-14 10:00:47 +02:00
|
|
|
/* Loongson MultiMedia Instructions */
|
2020-06-02 04:39:15 +02:00
|
|
|
#define ASE_LMMI 0x0040000000000000ULL
|
2020-06-14 10:00:47 +02:00
|
|
|
/* Loongson EXTensions */
|
2020-06-02 04:39:15 +02:00
|
|
|
#define ASE_LEXT 0x0080000000000000ULL
|
2007-09-24 14:48:00 +02:00
|
|
|
|
2007-12-25 21:46:56 +01:00
|
|
|
/* MIPS CPU defines. */
|
2019-09-24 15:26:35 +02:00
|
|
|
#define CPU_MIPS1 (ISA_MIPS1)
|
|
|
|
#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
|
|
|
|
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
|
|
|
|
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
|
2020-12-16 12:23:38 +01:00
|
|
|
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
|
2007-12-25 21:46:56 +01:00
|
|
|
|
2020-12-16 12:41:25 +01:00
|
|
|
#define CPU_MIPS64 (ISA_MIPS3)
|
|
|
|
|
2007-12-25 21:46:56 +01:00
|
|
|
/* MIPS Technologies "Release 1" */
|
2020-12-16 12:26:56 +01:00
|
|
|
#define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1)
|
2020-12-16 17:23:15 +01:00
|
|
|
#define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1)
|
2007-09-24 14:48:00 +02:00
|
|
|
|
2007-12-25 21:46:56 +01:00
|
|
|
/* MIPS Technologies "Release 2" */
|
2020-12-16 12:29:00 +01:00
|
|
|
#define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2)
|
2020-12-16 12:06:51 +01:00
|
|
|
#define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2)
|
2007-09-24 14:48:00 +02:00
|
|
|
|
2014-01-15 17:01:46 +01:00
|
|
|
/* MIPS Technologies "Release 3" */
|
2020-12-16 12:29:34 +01:00
|
|
|
#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3)
|
2020-12-16 12:08:40 +01:00
|
|
|
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
|
2014-01-15 17:01:46 +01:00
|
|
|
|
|
|
|
/* MIPS Technologies "Release 5" */
|
2020-12-16 12:30:11 +01:00
|
|
|
#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5)
|
2020-12-16 12:09:08 +01:00
|
|
|
#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5)
|
2014-06-27 09:49:00 +02:00
|
|
|
|
|
|
|
/* MIPS Technologies "Release 6" */
|
2020-12-16 12:34:42 +01:00
|
|
|
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
|
2020-12-16 12:14:00 +01:00
|
|
|
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
|
2014-01-15 17:01:46 +01:00
|
|
|
|
2019-09-24 15:26:35 +02:00
|
|
|
/*
|
|
|
|
* Strictly follow the architecture standard:
|
|
|
|
* - Disallow "special" instruction handling for PMON/SPIM.
|
|
|
|
* Note that we still maintain Count/Compare to match the host clock.
|
|
|
|
*
|
|
|
|
* #define MIPS_STRICT_STANDARD 1
|
|
|
|
*/
|
2007-04-11 04:24:14 +02:00
|
|
|
|
2016-06-29 13:47:03 +02:00
|
|
|
#endif /* QEMU_MIPS_DEFS_H */
|