2016-06-27 16:37:33 +02:00
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/*
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* ASPEED System Control Unit
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*
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* Andrew Jeffery <andrew@aj.id.au>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/misc/aspeed_scu.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "qemu/bitops.h"
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2016-06-27 23:53:04 +02:00
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#include "qemu/log.h"
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2016-06-27 16:37:33 +02:00
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#include "trace.h"
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#define TO_REG(offset) ((offset) >> 2)
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#define PROT_KEY TO_REG(0x00)
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#define SYS_RST_CTRL TO_REG(0x04)
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#define CLK_SEL TO_REG(0x08)
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#define CLK_STOP_CTRL TO_REG(0x0C)
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#define FREQ_CNTR_CTRL TO_REG(0x10)
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#define FREQ_CNTR_EVAL TO_REG(0x14)
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#define IRQ_CTRL TO_REG(0x18)
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#define D2PLL_PARAM TO_REG(0x1C)
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#define MPLL_PARAM TO_REG(0x20)
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#define HPLL_PARAM TO_REG(0x24)
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#define FREQ_CNTR_RANGE TO_REG(0x28)
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#define MISC_CTRL1 TO_REG(0x2C)
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#define PCI_CTRL1 TO_REG(0x30)
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#define PCI_CTRL2 TO_REG(0x34)
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#define PCI_CTRL3 TO_REG(0x38)
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#define SYS_RST_STATUS TO_REG(0x3C)
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#define SOC_SCRATCH1 TO_REG(0x40)
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#define SOC_SCRATCH2 TO_REG(0x44)
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#define MAC_CLK_DELAY TO_REG(0x48)
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#define MISC_CTRL2 TO_REG(0x4C)
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#define VGA_SCRATCH1 TO_REG(0x50)
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#define VGA_SCRATCH2 TO_REG(0x54)
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#define VGA_SCRATCH3 TO_REG(0x58)
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#define VGA_SCRATCH4 TO_REG(0x5C)
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#define VGA_SCRATCH5 TO_REG(0x60)
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#define VGA_SCRATCH6 TO_REG(0x64)
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#define VGA_SCRATCH7 TO_REG(0x68)
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#define VGA_SCRATCH8 TO_REG(0x6C)
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#define HW_STRAP1 TO_REG(0x70)
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#define RNG_CTRL TO_REG(0x74)
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#define RNG_DATA TO_REG(0x78)
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#define SILICON_REV TO_REG(0x7C)
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#define PINMUX_CTRL1 TO_REG(0x80)
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#define PINMUX_CTRL2 TO_REG(0x84)
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#define PINMUX_CTRL3 TO_REG(0x88)
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#define PINMUX_CTRL4 TO_REG(0x8C)
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#define PINMUX_CTRL5 TO_REG(0x90)
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#define PINMUX_CTRL6 TO_REG(0x94)
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#define WDT_RST_CTRL TO_REG(0x9C)
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#define PINMUX_CTRL7 TO_REG(0xA0)
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#define PINMUX_CTRL8 TO_REG(0xA4)
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#define PINMUX_CTRL9 TO_REG(0xA8)
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#define WAKEUP_EN TO_REG(0xC0)
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#define WAKEUP_CTRL TO_REG(0xC4)
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#define HW_STRAP2 TO_REG(0xD0)
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#define FREE_CNTR4 TO_REG(0xE0)
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#define FREE_CNTR4_EXT TO_REG(0xE4)
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#define CPU2_CTRL TO_REG(0x100)
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#define CPU2_BASE_SEG1 TO_REG(0x104)
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#define CPU2_BASE_SEG2 TO_REG(0x108)
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#define CPU2_BASE_SEG3 TO_REG(0x10C)
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#define CPU2_BASE_SEG4 TO_REG(0x110)
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#define CPU2_BASE_SEG5 TO_REG(0x114)
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#define CPU2_CACHE_CTRL TO_REG(0x118)
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#define UART_HPLL_CLK TO_REG(0x160)
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#define PCIE_CTRL TO_REG(0x180)
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#define BMC_MMIO_CTRL TO_REG(0x184)
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#define RELOC_DECODE_BASE1 TO_REG(0x188)
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#define RELOC_DECODE_BASE2 TO_REG(0x18C)
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#define MAILBOX_DECODE_BASE TO_REG(0x190)
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#define SRAM_DECODE_BASE1 TO_REG(0x194)
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#define SRAM_DECODE_BASE2 TO_REG(0x198)
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#define BMC_REV TO_REG(0x19C)
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#define BMC_DEV_ID TO_REG(0x1A4)
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#define PROT_KEY_UNLOCK 0x1688A8A8
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2016-12-27 15:59:28 +01:00
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#define SCU_IO_REGION_SIZE 0x1000
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2016-06-27 16:37:33 +02:00
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static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
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[SYS_RST_CTRL] = 0xFFCFFEDCU,
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[CLK_SEL] = 0xF3F40000U,
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[CLK_STOP_CTRL] = 0x19FC3E8BU,
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[D2PLL_PARAM] = 0x00026108U,
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[MPLL_PARAM] = 0x00030291U,
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[HPLL_PARAM] = 0x00000291U,
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[MISC_CTRL1] = 0x00000010U,
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[PCI_CTRL1] = 0x20001A03U,
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[PCI_CTRL2] = 0x20001A03U,
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[PCI_CTRL3] = 0x04000030U,
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[SYS_RST_STATUS] = 0x00000001U,
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[SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
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[MISC_CTRL2] = 0x00000023U,
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[RNG_CTRL] = 0x0000000EU,
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[PINMUX_CTRL2] = 0x0000F000U,
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[PINMUX_CTRL3] = 0x01000000U,
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[PINMUX_CTRL4] = 0x000000FFU,
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[PINMUX_CTRL5] = 0x0000A000U,
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[WDT_RST_CTRL] = 0x003FFFF3U,
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[PINMUX_CTRL8] = 0xFFFF0000U,
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[PINMUX_CTRL9] = 0x000FFFFFU,
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[FREE_CNTR4] = 0x000000FFU,
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[FREE_CNTR4_EXT] = 0x000000FFU,
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[CPU2_BASE_SEG1] = 0x80000000U,
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[CPU2_BASE_SEG4] = 0x1E600000U,
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[CPU2_BASE_SEG5] = 0xC0000000U,
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[UART_HPLL_CLK] = 0x00001903U,
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[PCIE_CTRL] = 0x0000007BU,
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[BMC_DEV_ID] = 0x00002402U
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};
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2016-09-22 19:13:05 +02:00
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/* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
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/* AST2500 revision A1 */
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static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
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[SYS_RST_CTRL] = 0xFFCFFEDCU,
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[CLK_SEL] = 0xF3F40000U,
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[CLK_STOP_CTRL] = 0x19FC3E8BU,
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[D2PLL_PARAM] = 0x00026108U,
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[MPLL_PARAM] = 0x00030291U,
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[HPLL_PARAM] = 0x93000400U,
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[MISC_CTRL1] = 0x00000010U,
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[PCI_CTRL1] = 0x20001A03U,
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[PCI_CTRL2] = 0x20001A03U,
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[PCI_CTRL3] = 0x04000030U,
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[SYS_RST_STATUS] = 0x00000001U,
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[SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
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[MISC_CTRL2] = 0x00000023U,
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[RNG_CTRL] = 0x0000000EU,
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[PINMUX_CTRL2] = 0x0000F000U,
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[PINMUX_CTRL3] = 0x03000000U,
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[PINMUX_CTRL4] = 0x00000000U,
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[PINMUX_CTRL5] = 0x0000A000U,
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[WDT_RST_CTRL] = 0x023FFFF3U,
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[PINMUX_CTRL8] = 0xFFFF0000U,
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[PINMUX_CTRL9] = 0x000FFFFFU,
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[FREE_CNTR4] = 0x000000FFU,
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[FREE_CNTR4_EXT] = 0x000000FFU,
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[CPU2_BASE_SEG1] = 0x80000000U,
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[CPU2_BASE_SEG4] = 0x1E600000U,
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[CPU2_BASE_SEG5] = 0xC0000000U,
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[UART_HPLL_CLK] = 0x00001903U,
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[PCIE_CTRL] = 0x0000007BU,
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[BMC_DEV_ID] = 0x00002402U
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};
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2016-06-27 16:37:33 +02:00
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static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
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{
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AspeedSCUState *s = ASPEED_SCU(opaque);
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int reg = TO_REG(offset);
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if (reg >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return 0;
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}
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switch (reg) {
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case WAKEUP_EN:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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return s->regs[reg];
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}
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static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned size)
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{
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AspeedSCUState *s = ASPEED_SCU(opaque);
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int reg = TO_REG(offset);
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if (reg >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return;
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}
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if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
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s->regs[PROT_KEY] != PROT_KEY_UNLOCK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
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return;
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}
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trace_aspeed_scu_write(offset, size, data);
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switch (reg) {
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case FREQ_CNTR_EVAL:
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case VGA_SCRATCH1 ... VGA_SCRATCH8:
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case RNG_DATA:
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case SILICON_REV:
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case FREE_CNTR4:
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case FREE_CNTR4_EXT:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return;
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}
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s->regs[reg] = data;
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}
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static const MemoryRegionOps aspeed_scu_ops = {
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.read = aspeed_scu_read,
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.write = aspeed_scu_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.valid.unaligned = false,
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};
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static void aspeed_scu_reset(DeviceState *dev)
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{
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AspeedSCUState *s = ASPEED_SCU(dev);
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const uint32_t *reset;
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switch (s->silicon_rev) {
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case AST2400_A0_SILICON_REV:
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2016-12-27 15:59:28 +01:00
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case AST2400_A1_SILICON_REV:
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2016-06-27 16:37:33 +02:00
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reset = ast2400_a0_resets;
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break;
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2016-09-22 19:13:05 +02:00
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case AST2500_A0_SILICON_REV:
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case AST2500_A1_SILICON_REV:
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reset = ast2500_a1_resets;
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break;
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2016-06-27 16:37:33 +02:00
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default:
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g_assert_not_reached();
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}
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memcpy(s->regs, reset, sizeof(s->regs));
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s->regs[SILICON_REV] = s->silicon_rev;
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s->regs[HW_STRAP1] = s->hw_strap1;
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s->regs[HW_STRAP2] = s->hw_strap2;
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}
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2016-09-22 19:13:05 +02:00
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static uint32_t aspeed_silicon_revs[] = {
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AST2400_A0_SILICON_REV,
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2016-12-27 15:59:28 +01:00
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AST2400_A1_SILICON_REV,
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2016-09-22 19:13:05 +02:00
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AST2500_A0_SILICON_REV,
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AST2500_A1_SILICON_REV,
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};
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2016-06-27 16:37:33 +02:00
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2016-07-14 17:51:39 +02:00
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bool is_supported_silicon_rev(uint32_t silicon_rev)
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2016-06-27 16:37:33 +02:00
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
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if (silicon_rev == aspeed_silicon_revs[i]) {
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return true;
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}
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}
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return false;
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}
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static void aspeed_scu_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedSCUState *s = ASPEED_SCU(dev);
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if (!is_supported_silicon_rev(s->silicon_rev)) {
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error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
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s->silicon_rev);
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return;
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}
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
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TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription vmstate_aspeed_scu = {
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.name = "aspeed.scu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property aspeed_scu_properties[] = {
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DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
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DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
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2016-07-14 17:51:38 +02:00
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DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
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2016-06-27 16:37:33 +02:00
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DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_scu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = aspeed_scu_realize;
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dc->reset = aspeed_scu_reset;
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dc->desc = "ASPEED System Control Unit";
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dc->vmsd = &vmstate_aspeed_scu;
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dc->props = aspeed_scu_properties;
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}
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static const TypeInfo aspeed_scu_info = {
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.name = TYPE_ASPEED_SCU,
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|
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSCUState),
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|
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.class_init = aspeed_scu_class_init,
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|
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};
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static void aspeed_scu_register_types(void)
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|
|
{
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|
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type_register_static(&aspeed_scu_info);
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|
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}
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|
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type_init(aspeed_scu_register_types);
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