98 lines
2.9 KiB
C
98 lines
2.9 KiB
C
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/*
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* Global peripheral timer block for ARM A9MP
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*
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* (C) 2013 Xilinx Inc.
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*
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* Written by François LEGAL
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_TIMER_A9_GTIMER_H_H
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#define HW_TIMER_A9_GTIMER_H_H
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#include "hw/sysbus.h"
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#define A9_GTIMER_MAX_CPUS 4
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#define TYPE_A9_GTIMER "arm.cortex-a9-global-timer"
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#define A9_GTIMER(obj) OBJECT_CHECK(A9GTimerState, (obj), TYPE_A9_GTIMER)
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#define R_COUNTER_LO 0x00
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#define R_COUNTER_HI 0x04
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#define R_CONTROL 0x08
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#define R_CONTROL_TIMER_ENABLE (1 << 0)
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#define R_CONTROL_COMP_ENABLE (1 << 1)
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#define R_CONTROL_IRQ_ENABLE (1 << 2)
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#define R_CONTROL_AUTO_INCREMENT (1 << 2)
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#define R_CONTROL_PRESCALER_SHIFT 8
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#define R_CONTROL_PRESCALER_LEN 8
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#define R_CONTROL_PRESCALER_MASK (((1 << R_CONTROL_PRESCALER_LEN) - 1) << \
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R_CONTROL_PRESCALER_SHIFT)
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#define R_CONTROL_BANKED (R_CONTROL_COMP_ENABLE | \
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R_CONTROL_IRQ_ENABLE | \
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R_CONTROL_AUTO_INCREMENT)
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#define R_CONTROL_NEEDS_SYNC (R_CONTROL_TIMER_ENABLE | \
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R_CONTROL_PRESCALER_MASK)
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#define R_INTERRUPT_STATUS 0x0C
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#define R_COMPARATOR_LO 0x10
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#define R_COMPARATOR_HI 0x14
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#define R_AUTO_INCREMENT 0x18
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typedef struct A9GTimerPerCPU A9GTimerPerCPU;
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typedef struct A9GTimerState A9GTimerState;
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struct A9GTimerPerCPU {
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A9GTimerState *parent;
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uint32_t control; /* only per cpu banked bits valid */
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uint64_t compare;
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uint32_t status;
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uint32_t inc;
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MemoryRegion iomem;
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qemu_irq irq; /* PPI interrupts */
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};
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struct A9GTimerState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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/* static props */
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uint32_t num_cpu;
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QEMUTimer *timer;
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uint64_t counter; /* current timer value */
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uint64_t ref_counter;
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uint64_t cpu_ref_time; /* the cpu time as of last update of ref_counter */
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uint32_t control; /* only non per cpu banked bits valid */
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A9GTimerPerCPU per_cpu[A9_GTIMER_MAX_CPUS];
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};
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typedef struct A9GTimerUpdate {
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uint64_t now;
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uint64_t new;
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} A9GTimerUpdate;
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#endif /* #ifdef HW_TIMER_A9_GTIMER_H_H */
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