2013-05-13 13:29:47 +02:00
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/*
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* Simple interface for atomic operations.
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*
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* Copyright (C) 2013 Red Hat, Inc.
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*
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* Author: Paolo Bonzini <pbonzini@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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2017-07-29 00:46:04 +02:00
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* See docs/devel/atomics.txt for discussion about the guarantees each
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2016-01-28 11:15:17 +01:00
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* atomic primitive is meant to provide.
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2013-05-13 13:29:47 +02:00
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*/
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2010-02-22 17:57:54 +01:00
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2016-06-29 13:47:03 +02:00
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#ifndef QEMU_ATOMIC_H
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#define QEMU_ATOMIC_H
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2012-10-06 12:46:15 +02:00
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2013-05-13 13:29:47 +02:00
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/* Compiler barrier */
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#define barrier() ({ asm volatile("" ::: "memory"); (void)0; })
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2016-08-09 21:02:24 +02:00
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/* The variable that receives the old value of an atomically-accessed
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* variable must be non-qualified, because atomic builtins return values
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* through a pointer-type argument as in __atomic_load(&var, &old, MODEL).
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*
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* This macro has to handle types smaller than int manually, because of
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* implicit promotion. int and larger types, as well as pointers, can be
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* converted to a non-qualified type just by applying a binary operator.
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*/
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#define typeof_strip_qual(expr) \
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typeof( \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), bool) || \
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__builtin_types_compatible_p(typeof(expr), const bool) || \
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__builtin_types_compatible_p(typeof(expr), volatile bool) || \
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__builtin_types_compatible_p(typeof(expr), const volatile bool), \
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(bool)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), signed char) || \
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__builtin_types_compatible_p(typeof(expr), const signed char) || \
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__builtin_types_compatible_p(typeof(expr), volatile signed char) || \
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__builtin_types_compatible_p(typeof(expr), const volatile signed char), \
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(signed char)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), unsigned char) || \
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__builtin_types_compatible_p(typeof(expr), const unsigned char) || \
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__builtin_types_compatible_p(typeof(expr), volatile unsigned char) || \
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__builtin_types_compatible_p(typeof(expr), const volatile unsigned char), \
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(unsigned char)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), signed short) || \
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__builtin_types_compatible_p(typeof(expr), const signed short) || \
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__builtin_types_compatible_p(typeof(expr), volatile signed short) || \
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__builtin_types_compatible_p(typeof(expr), const volatile signed short), \
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(signed short)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), unsigned short) || \
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__builtin_types_compatible_p(typeof(expr), const unsigned short) || \
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__builtin_types_compatible_p(typeof(expr), volatile unsigned short) || \
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__builtin_types_compatible_p(typeof(expr), const volatile unsigned short), \
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(unsigned short)1, \
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(expr)+0))))))
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2016-01-28 11:15:17 +01:00
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#ifdef __ATOMIC_RELAXED
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/* For C11 atomic ops */
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/* Manual memory barriers
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*
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*__atomic_thread_fence does not include a compiler barrier; instead,
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* the barrier is part of __atomic_load/__atomic_store's "volatile-like"
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* semantics. If smp_wmb() is a no-op, absence of the barrier means that
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* the compiler is free to reorder stores on each side of the barrier.
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* Add one here, and similarly in smp_rmb() and smp_read_barrier_depends().
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*/
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2016-09-19 10:50:38 +02:00
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#define smp_mb() ({ barrier(); __atomic_thread_fence(__ATOMIC_SEQ_CST); })
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#define smp_mb_release() ({ barrier(); __atomic_thread_fence(__ATOMIC_RELEASE); })
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#define smp_mb_acquire() ({ barrier(); __atomic_thread_fence(__ATOMIC_ACQUIRE); })
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2016-01-28 11:15:17 +01:00
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2016-05-24 22:06:13 +02:00
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/* Most compilers currently treat consume and acquire the same, but really
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* no processors except Alpha need a barrier here. Leave it in if
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* using Thread Sanitizer to avoid warnings, otherwise optimize it away.
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*/
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#if defined(__SANITIZE_THREAD__)
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2016-09-19 10:50:38 +02:00
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#define smp_read_barrier_depends() ({ barrier(); __atomic_thread_fence(__ATOMIC_CONSUME); })
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2016-09-30 23:30:52 +02:00
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#elif defined(__alpha__)
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2016-05-24 22:06:13 +02:00
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#define smp_read_barrier_depends() asm volatile("mb":::"memory")
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#else
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#define smp_read_barrier_depends() barrier()
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#endif
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2017-04-26 19:41:55 +02:00
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/* Sanity check that the size of an atomic operation isn't "overly large".
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* Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
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* want to use them because we ought not need them, and this lets us do a
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* bit of sanity checking that other 32-bit hosts might build.
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*
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* That said, we have a problem on 64-bit ILP32 hosts in that in order to
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* sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS.
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* We'd prefer not want to pull in everything else TCG related, so handle
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* those few cases by hand.
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*
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2018-09-03 19:18:28 +02:00
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* Note that x32 is fully detected with __x86_64__ + _ILP32, and that for
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2018-12-27 16:32:11 +01:00
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* Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) &
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* n64 (LP64) ABIs are both detected using __mips64.
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2017-04-26 19:41:55 +02:00
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*/
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2018-12-27 16:32:11 +01:00
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#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64)
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2017-04-26 19:41:55 +02:00
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# define ATOMIC_REG_SIZE 8
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#else
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# define ATOMIC_REG_SIZE sizeof(void *)
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#endif
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2016-01-28 11:15:17 +01:00
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/* Weak atomic operations prevent the compiler moving other
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* loads/stores past the atomic operation load/store. However there is
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* no explicit memory barrier for the processor.
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2016-09-30 23:30:53 +02:00
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*
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* The C11 memory model says that variables that are accessed from
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* different threads should at least be done with __ATOMIC_RELAXED
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* primitives or the result is undefined. Generally this has little to
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* no effect on the generated code but not using the atomic primitives
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* will get flagged by sanitizers as a violation.
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2016-01-28 11:15:17 +01:00
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*/
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2016-10-24 19:29:32 +02:00
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#define atomic_read__nocheck(ptr) \
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__atomic_load_n(ptr, __ATOMIC_RELAXED)
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2016-04-04 16:35:49 +02:00
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#define atomic_read(ptr) \
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({ \
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2017-04-26 19:41:55 +02:00
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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2016-10-24 19:29:32 +02:00
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atomic_read__nocheck(ptr); \
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2016-01-28 11:15:17 +01:00
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})
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2016-10-24 19:29:32 +02:00
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#define atomic_set__nocheck(ptr, i) \
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__atomic_store_n(ptr, i, __ATOMIC_RELAXED)
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2016-04-04 16:35:49 +02:00
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#define atomic_set(ptr, i) do { \
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2017-04-26 19:41:55 +02:00
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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2016-10-24 19:29:32 +02:00
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atomic_set__nocheck(ptr, i); \
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2016-01-28 11:15:17 +01:00
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} while(0)
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2016-05-24 22:06:14 +02:00
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/* See above: most compilers currently treat consume and acquire the
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* same, but this slows down atomic_rcu_read unnecessarily.
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*/
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#ifdef __SANITIZE_THREAD__
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#define atomic_rcu_read__nocheck(ptr, valptr) \
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__atomic_load(ptr, valptr, __ATOMIC_CONSUME);
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#else
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#define atomic_rcu_read__nocheck(ptr, valptr) \
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__atomic_load(ptr, valptr, __ATOMIC_RELAXED); \
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smp_read_barrier_depends();
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#endif
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2016-01-28 11:15:17 +01:00
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2016-04-04 16:35:49 +02:00
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#define atomic_rcu_read(ptr) \
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({ \
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2017-04-26 19:41:55 +02:00
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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2016-08-09 21:02:24 +02:00
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typeof_strip_qual(*ptr) _val; \
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2016-05-24 22:06:14 +02:00
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atomic_rcu_read__nocheck(ptr, &_val); \
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2016-04-04 16:35:49 +02:00
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_val; \
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2016-01-28 11:15:17 +01:00
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})
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2016-04-04 16:35:49 +02:00
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#define atomic_rcu_set(ptr, i) do { \
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2017-04-26 19:41:55 +02:00
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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2016-08-29 19:17:01 +02:00
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__atomic_store_n(ptr, i, __ATOMIC_RELEASE); \
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2016-01-28 11:15:17 +01:00
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} while(0)
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2016-09-19 11:36:44 +02:00
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#define atomic_load_acquire(ptr) \
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2016-01-28 11:15:17 +01:00
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({ \
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2017-04-26 19:41:55 +02:00
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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2016-08-09 21:02:24 +02:00
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typeof_strip_qual(*ptr) _val; \
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2016-09-19 11:36:44 +02:00
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__atomic_load(ptr, &_val, __ATOMIC_ACQUIRE); \
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2016-01-28 11:15:17 +01:00
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_val; \
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})
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2016-09-19 11:36:44 +02:00
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#define atomic_store_release(ptr, i) do { \
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2017-04-26 19:41:55 +02:00
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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2016-09-19 11:36:44 +02:00
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__atomic_store_n(ptr, i, __ATOMIC_RELEASE); \
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2016-01-28 11:15:17 +01:00
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} while(0)
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/* All the remaining operations are fully sequentially consistent */
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2016-10-24 19:29:32 +02:00
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#define atomic_xchg__nocheck(ptr, i) ({ \
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__atomic_exchange_n(ptr, (i), __ATOMIC_SEQ_CST); \
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})
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2016-01-28 11:15:17 +01:00
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#define atomic_xchg(ptr, i) ({ \
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2017-04-26 19:41:55 +02:00
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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2016-10-24 19:29:32 +02:00
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atomic_xchg__nocheck(ptr, i); \
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2016-01-28 11:15:17 +01:00
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})
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/* Returns the eventual value, failed or not */
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2016-10-24 19:29:32 +02:00
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#define atomic_cmpxchg__nocheck(ptr, old, new) ({ \
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2016-08-29 19:17:01 +02:00
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typeof_strip_qual(*ptr) _old = (old); \
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2018-05-10 19:10:57 +02:00
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(void)__atomic_compare_exchange_n(ptr, &_old, new, false, \
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2016-01-28 11:15:17 +01:00
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__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); \
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_old; \
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2016-10-24 19:29:32 +02:00
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})
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#define atomic_cmpxchg(ptr, old, new) ({ \
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2017-04-26 19:41:55 +02:00
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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2016-10-24 19:29:32 +02:00
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atomic_cmpxchg__nocheck(ptr, old, new); \
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})
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2016-01-28 11:15:17 +01:00
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/* Provide shorter names for GCC atomic builtins, return old value */
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#define atomic_fetch_inc(ptr) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_fetch_dec(ptr) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_fetch_add(ptr, n) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_sub(ptr, n) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_and(ptr, n) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_or(ptr, n) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST)
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2016-06-27 21:01:53 +02:00
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#define atomic_fetch_xor(ptr, n) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST)
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2016-01-28 11:15:17 +01:00
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2016-06-27 21:01:54 +02:00
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#define atomic_inc_fetch(ptr) __atomic_add_fetch(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_dec_fetch(ptr) __atomic_sub_fetch(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_add_fetch(ptr, n) __atomic_add_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_sub_fetch(ptr, n) __atomic_sub_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_and_fetch(ptr, n) __atomic_and_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_or_fetch(ptr, n) __atomic_or_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_xor_fetch(ptr, n) __atomic_xor_fetch(ptr, n, __ATOMIC_SEQ_CST)
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2016-01-28 11:15:17 +01:00
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/* And even shorter names that return void. */
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#define atomic_inc(ptr) ((void) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST))
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#define atomic_dec(ptr) ((void) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST))
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#define atomic_add(ptr, n) ((void) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_sub(ptr, n) ((void) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_and(ptr, n) ((void) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_or(ptr, n) ((void) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST))
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2016-06-27 21:01:53 +02:00
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#define atomic_xor(ptr, n) ((void) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST))
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2016-01-28 11:15:17 +01:00
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#else /* __ATOMIC_RELAXED */
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2013-02-22 17:36:25 +01:00
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virtio: add missing mb() on notification
During normal operation, virtio first writes a used index
and then checks whether it should interrupt the guest
by reading guest avail index/flag values.
Guest does the reverse: writes the index/flag,
then checks the used ring.
The ordering is important: if host avail flag read bypasses the used
index write, we could in effect get this timing:
host avail flag read
guest enable interrupts: avail flag write
guest check used ring: ring is empty
host used index write
which results in a lost interrupt: guest will never be notified
about the used ring update.
This actually can happen when using kvm with an io thread,
such that the guest vcpu and qemu run on different host cpus,
and this has actually been observed in the field
(but only seems to trigger on very specific processor types)
with userspace virtio: vhost has the necessary smp_mb()
in place to prevent the regordering, so the same workload stalls
forever waiting for an interrupt with vhost=off but works
fine with vhost=on.
Insert an smp_mb barrier operation in userspace virtio to
ensure the correct ordering.
Applying this patch fixed the race condition we have observed.
Tested on x86_64. I checked the code generated by the new macro
for i386 and ppc but didn't run virtio.
Note: mb could in theory be implemented by __sync_synchronize, but this
would make us hit old GCC bugs. Besides old GCC
not implementing __sync_synchronize at all, there were bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793
in this functionality as recently as in 4.3.
As we need asm for rmb,wmb anyway, it's just as well to
use it for mb.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2012-04-22 15:45:53 +02:00
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/*
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2013-05-13 13:29:47 +02:00
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* We use GCC builtin if it's available, as that can use mfence on
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* 32-bit as well, e.g. if built with -march=pentium-m. However, on
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* i386 the spec is buggy, and the implementation followed it until
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* 4.3 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793).
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#if !QEMU_GNUC_PREREQ(4, 4)
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#if defined __x86_64__
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#define smp_mb() ({ asm volatile("mfence" ::: "memory"); (void)0; })
|
virtio: add missing mb() on notification
During normal operation, virtio first writes a used index
and then checks whether it should interrupt the guest
by reading guest avail index/flag values.
Guest does the reverse: writes the index/flag,
then checks the used ring.
The ordering is important: if host avail flag read bypasses the used
index write, we could in effect get this timing:
host avail flag read
guest enable interrupts: avail flag write
guest check used ring: ring is empty
host used index write
which results in a lost interrupt: guest will never be notified
about the used ring update.
This actually can happen when using kvm with an io thread,
such that the guest vcpu and qemu run on different host cpus,
and this has actually been observed in the field
(but only seems to trigger on very specific processor types)
with userspace virtio: vhost has the necessary smp_mb()
in place to prevent the regordering, so the same workload stalls
forever waiting for an interrupt with vhost=off but works
fine with vhost=on.
Insert an smp_mb barrier operation in userspace virtio to
ensure the correct ordering.
Applying this patch fixed the race condition we have observed.
Tested on x86_64. I checked the code generated by the new macro
for i386 and ppc but didn't run virtio.
Note: mb could in theory be implemented by __sync_synchronize, but this
would make us hit old GCC bugs. Besides old GCC
not implementing __sync_synchronize at all, there were bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793
in this functionality as recently as in 4.3.
As we need asm for rmb,wmb anyway, it's just as well to
use it for mb.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2012-04-22 15:45:53 +02:00
|
|
|
#else
|
2013-05-13 13:29:47 +02:00
|
|
|
#define smp_mb() ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; })
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef __alpha__
|
|
|
|
#define smp_read_barrier_depends() asm volatile("mb":::"memory")
|
virtio: add missing mb() on notification
During normal operation, virtio first writes a used index
and then checks whether it should interrupt the guest
by reading guest avail index/flag values.
Guest does the reverse: writes the index/flag,
then checks the used ring.
The ordering is important: if host avail flag read bypasses the used
index write, we could in effect get this timing:
host avail flag read
guest enable interrupts: avail flag write
guest check used ring: ring is empty
host used index write
which results in a lost interrupt: guest will never be notified
about the used ring update.
This actually can happen when using kvm with an io thread,
such that the guest vcpu and qemu run on different host cpus,
and this has actually been observed in the field
(but only seems to trigger on very specific processor types)
with userspace virtio: vhost has the necessary smp_mb()
in place to prevent the regordering, so the same workload stalls
forever waiting for an interrupt with vhost=off but works
fine with vhost=on.
Insert an smp_mb barrier operation in userspace virtio to
ensure the correct ordering.
Applying this patch fixed the race condition we have observed.
Tested on x86_64. I checked the code generated by the new macro
for i386 and ppc but didn't run virtio.
Note: mb could in theory be implemented by __sync_synchronize, but this
would make us hit old GCC bugs. Besides old GCC
not implementing __sync_synchronize at all, there were bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793
in this functionality as recently as in 4.3.
As we need asm for rmb,wmb anyway, it's just as well to
use it for mb.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2012-04-22 15:45:53 +02:00
|
|
|
#endif
|
|
|
|
|
2013-05-13 13:29:47 +02:00
|
|
|
#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__)
|
virtio: add missing mb() on notification
During normal operation, virtio first writes a used index
and then checks whether it should interrupt the guest
by reading guest avail index/flag values.
Guest does the reverse: writes the index/flag,
then checks the used ring.
The ordering is important: if host avail flag read bypasses the used
index write, we could in effect get this timing:
host avail flag read
guest enable interrupts: avail flag write
guest check used ring: ring is empty
host used index write
which results in a lost interrupt: guest will never be notified
about the used ring update.
This actually can happen when using kvm with an io thread,
such that the guest vcpu and qemu run on different host cpus,
and this has actually been observed in the field
(but only seems to trigger on very specific processor types)
with userspace virtio: vhost has the necessary smp_mb()
in place to prevent the regordering, so the same workload stalls
forever waiting for an interrupt with vhost=off but works
fine with vhost=on.
Insert an smp_mb barrier operation in userspace virtio to
ensure the correct ordering.
Applying this patch fixed the race condition we have observed.
Tested on x86_64. I checked the code generated by the new macro
for i386 and ppc but didn't run virtio.
Note: mb could in theory be implemented by __sync_synchronize, but this
would make us hit old GCC bugs. Besides old GCC
not implementing __sync_synchronize at all, there were bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793
in this functionality as recently as in 4.3.
As we need asm for rmb,wmb anyway, it's just as well to
use it for mb.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2012-04-22 15:45:53 +02:00
|
|
|
|
2013-05-13 13:29:47 +02:00
|
|
|
/*
|
|
|
|
* Because of the strongly ordered storage model, wmb() and rmb() are nops
|
|
|
|
* here (a compiler barrier only). QEMU doesn't do accesses to write-combining
|
|
|
|
* qemu memory or non-temporal load/stores from C code.
|
|
|
|
*/
|
2016-09-19 10:50:38 +02:00
|
|
|
#define smp_mb_release() barrier()
|
|
|
|
#define smp_mb_acquire() barrier()
|
2013-05-13 13:29:47 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* __sync_lock_test_and_set() is documented to be an acquire barrier only,
|
|
|
|
* but it is a full barrier at the hardware level. Add a compiler barrier
|
|
|
|
* to make it a full barrier also at the compiler level.
|
|
|
|
*/
|
|
|
|
#define atomic_xchg(ptr, i) (barrier(), __sync_lock_test_and_set(ptr, i))
|
|
|
|
|
2011-11-01 10:39:49 +01:00
|
|
|
#elif defined(_ARCH_PPC)
|
Barriers in qemu-barrier.h should not be x86 specific
qemu-barrier.h contains a few macros implementing memory barrier
primitives used in several places throughout qemu. However, apart
from the compiler-only barrier, the defined wmb() is correct only for
x86, or platforms which are similarly strongly ordered.
This patch addresses the FIXME about this by making the wmb() macro
arch dependent. On x86, it remains a compiler barrier only, but with
a comment explaining in more detail the conditions under which this is
correct. On weakly-ordered powerpc, an "eieio" instruction is used,
again with explanation of the conditions under which it is sufficient.
On other platforms, we use the __sync_synchronize() primitive,
available in sufficiently recent gcc (4.2 and after?). This should
implement a full barrier which will be sufficient on all platforms,
although it may be overkill in some cases. Other platforms can add
optimized versions in future if it's worth it for them.
Without proper memory barriers, it is easy to reproduce ordering
problems with virtio on powerpc; specifically, the QEMU puts new
element into the "used" ring and then updates the ring free-running
counter. Without a barrier between these under the right
circumstances, the guest linux driver can receive an interrupt, read
the counter change but find the ring element to be handled still has
an old value, leading to an "id %u is not a head!\n" error message.
Similar problems are likely to be possible with kvm on other weakly
ordered platforms.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-20 04:05:21 +02:00
|
|
|
|
|
|
|
/*
|
virtio: add missing mb() on notification
During normal operation, virtio first writes a used index
and then checks whether it should interrupt the guest
by reading guest avail index/flag values.
Guest does the reverse: writes the index/flag,
then checks the used ring.
The ordering is important: if host avail flag read bypasses the used
index write, we could in effect get this timing:
host avail flag read
guest enable interrupts: avail flag write
guest check used ring: ring is empty
host used index write
which results in a lost interrupt: guest will never be notified
about the used ring update.
This actually can happen when using kvm with an io thread,
such that the guest vcpu and qemu run on different host cpus,
and this has actually been observed in the field
(but only seems to trigger on very specific processor types)
with userspace virtio: vhost has the necessary smp_mb()
in place to prevent the regordering, so the same workload stalls
forever waiting for an interrupt with vhost=off but works
fine with vhost=on.
Insert an smp_mb barrier operation in userspace virtio to
ensure the correct ordering.
Applying this patch fixed the race condition we have observed.
Tested on x86_64. I checked the code generated by the new macro
for i386 and ppc but didn't run virtio.
Note: mb could in theory be implemented by __sync_synchronize, but this
would make us hit old GCC bugs. Besides old GCC
not implementing __sync_synchronize at all, there were bugs
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793
in this functionality as recently as in 4.3.
As we need asm for rmb,wmb anyway, it's just as well to
use it for mb.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2012-04-22 15:45:53 +02:00
|
|
|
* We use an eieio() for wmb() on powerpc. This assumes we don't
|
Barriers in qemu-barrier.h should not be x86 specific
qemu-barrier.h contains a few macros implementing memory barrier
primitives used in several places throughout qemu. However, apart
from the compiler-only barrier, the defined wmb() is correct only for
x86, or platforms which are similarly strongly ordered.
This patch addresses the FIXME about this by making the wmb() macro
arch dependent. On x86, it remains a compiler barrier only, but with
a comment explaining in more detail the conditions under which this is
correct. On weakly-ordered powerpc, an "eieio" instruction is used,
again with explanation of the conditions under which it is sufficient.
On other platforms, we use the __sync_synchronize() primitive,
available in sufficiently recent gcc (4.2 and after?). This should
implement a full barrier which will be sufficient on all platforms,
although it may be overkill in some cases. Other platforms can add
optimized versions in future if it's worth it for them.
Without proper memory barriers, it is easy to reproduce ordering
problems with virtio on powerpc; specifically, the QEMU puts new
element into the "used" ring and then updates the ring free-running
counter. Without a barrier between these under the right
circumstances, the guest linux driver can receive an interrupt, read
the counter change but find the ring element to be handled still has
an old value, leading to an "id %u is not a head!\n" error message.
Similar problems are likely to be possible with kvm on other weakly
ordered platforms.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-20 04:05:21 +02:00
|
|
|
* need to order cacheable and non-cacheable stores with respect to
|
2013-05-13 13:29:47 +02:00
|
|
|
* each other.
|
|
|
|
*
|
|
|
|
* smp_mb has the same problem as on x86 for not-very-new GCC
|
|
|
|
* (http://patchwork.ozlabs.org/patch/126184/, Nov 2011).
|
Barriers in qemu-barrier.h should not be x86 specific
qemu-barrier.h contains a few macros implementing memory barrier
primitives used in several places throughout qemu. However, apart
from the compiler-only barrier, the defined wmb() is correct only for
x86, or platforms which are similarly strongly ordered.
This patch addresses the FIXME about this by making the wmb() macro
arch dependent. On x86, it remains a compiler barrier only, but with
a comment explaining in more detail the conditions under which this is
correct. On weakly-ordered powerpc, an "eieio" instruction is used,
again with explanation of the conditions under which it is sufficient.
On other platforms, we use the __sync_synchronize() primitive,
available in sufficiently recent gcc (4.2 and after?). This should
implement a full barrier which will be sufficient on all platforms,
although it may be overkill in some cases. Other platforms can add
optimized versions in future if it's worth it for them.
Without proper memory barriers, it is easy to reproduce ordering
problems with virtio on powerpc; specifically, the QEMU puts new
element into the "used" ring and then updates the ring free-running
counter. Without a barrier between these under the right
circumstances, the guest linux driver can receive an interrupt, read
the counter change but find the ring element to be handled still has
an old value, leading to an "id %u is not a head!\n" error message.
Similar problems are likely to be possible with kvm on other weakly
ordered platforms.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-20 04:05:21 +02:00
|
|
|
*/
|
2016-09-19 10:50:38 +02:00
|
|
|
#define smp_wmb() ({ asm volatile("eieio" ::: "memory"); (void)0; })
|
2012-04-23 14:46:22 +02:00
|
|
|
#if defined(__powerpc64__)
|
2016-09-19 10:50:38 +02:00
|
|
|
#define smp_mb_release() ({ asm volatile("lwsync" ::: "memory"); (void)0; })
|
|
|
|
#define smp_mb_acquire() ({ asm volatile("lwsync" ::: "memory"); (void)0; })
|
2012-04-23 14:46:22 +02:00
|
|
|
#else
|
2016-09-19 10:50:38 +02:00
|
|
|
#define smp_mb_release() ({ asm volatile("sync" ::: "memory"); (void)0; })
|
|
|
|
#define smp_mb_acquire() ({ asm volatile("sync" ::: "memory"); (void)0; })
|
2012-04-23 14:46:22 +02:00
|
|
|
#endif
|
2016-09-19 10:50:38 +02:00
|
|
|
#define smp_mb() ({ asm volatile("sync" ::: "memory"); (void)0; })
|
2012-04-23 14:46:22 +02:00
|
|
|
|
2013-05-13 13:29:47 +02:00
|
|
|
#endif /* _ARCH_PPC */
|
Barriers in qemu-barrier.h should not be x86 specific
qemu-barrier.h contains a few macros implementing memory barrier
primitives used in several places throughout qemu. However, apart
from the compiler-only barrier, the defined wmb() is correct only for
x86, or platforms which are similarly strongly ordered.
This patch addresses the FIXME about this by making the wmb() macro
arch dependent. On x86, it remains a compiler barrier only, but with
a comment explaining in more detail the conditions under which this is
correct. On weakly-ordered powerpc, an "eieio" instruction is used,
again with explanation of the conditions under which it is sufficient.
On other platforms, we use the __sync_synchronize() primitive,
available in sufficiently recent gcc (4.2 and after?). This should
implement a full barrier which will be sufficient on all platforms,
although it may be overkill in some cases. Other platforms can add
optimized versions in future if it's worth it for them.
Without proper memory barriers, it is easy to reproduce ordering
problems with virtio on powerpc; specifically, the QEMU puts new
element into the "used" ring and then updates the ring free-running
counter. Without a barrier between these under the right
circumstances, the guest linux driver can receive an interrupt, read
the counter change but find the ring element to be handled still has
an old value, leading to an "id %u is not a head!\n" error message.
Similar problems are likely to be possible with kvm on other weakly
ordered platforms.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-20 04:05:21 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For (host) platforms we don't have explicit barrier definitions
|
|
|
|
* for, we use the gcc __sync_synchronize() primitive to generate a
|
|
|
|
* full barrier. This should be safe on all platforms, though it may
|
2016-09-19 10:50:38 +02:00
|
|
|
* be overkill for smp_mb_acquire() and smp_mb_release().
|
Barriers in qemu-barrier.h should not be x86 specific
qemu-barrier.h contains a few macros implementing memory barrier
primitives used in several places throughout qemu. However, apart
from the compiler-only barrier, the defined wmb() is correct only for
x86, or platforms which are similarly strongly ordered.
This patch addresses the FIXME about this by making the wmb() macro
arch dependent. On x86, it remains a compiler barrier only, but with
a comment explaining in more detail the conditions under which this is
correct. On weakly-ordered powerpc, an "eieio" instruction is used,
again with explanation of the conditions under which it is sufficient.
On other platforms, we use the __sync_synchronize() primitive,
available in sufficiently recent gcc (4.2 and after?). This should
implement a full barrier which will be sufficient on all platforms,
although it may be overkill in some cases. Other platforms can add
optimized versions in future if it's worth it for them.
Without proper memory barriers, it is easy to reproduce ordering
problems with virtio on powerpc; specifically, the QEMU puts new
element into the "used" ring and then updates the ring free-running
counter. Without a barrier between these under the right
circumstances, the guest linux driver can receive an interrupt, read
the counter change but find the ring element to be handled still has
an old value, leading to an "id %u is not a head!\n" error message.
Similar problems are likely to be possible with kvm on other weakly
ordered platforms.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-20 04:05:21 +02:00
|
|
|
*/
|
2013-05-13 13:29:47 +02:00
|
|
|
#ifndef smp_mb
|
2016-09-19 10:50:38 +02:00
|
|
|
#define smp_mb() __sync_synchronize()
|
2013-05-13 13:29:47 +02:00
|
|
|
#endif
|
|
|
|
|
2016-09-19 10:50:38 +02:00
|
|
|
#ifndef smp_mb_acquire
|
|
|
|
#define smp_mb_acquire() __sync_synchronize()
|
2013-05-13 13:29:47 +02:00
|
|
|
#endif
|
|
|
|
|
2016-09-19 10:50:38 +02:00
|
|
|
#ifndef smp_mb_release
|
|
|
|
#define smp_mb_release() __sync_synchronize()
|
2013-05-13 13:29:47 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef smp_read_barrier_depends
|
|
|
|
#define smp_read_barrier_depends() barrier()
|
|
|
|
#endif
|
Barriers in qemu-barrier.h should not be x86 specific
qemu-barrier.h contains a few macros implementing memory barrier
primitives used in several places throughout qemu. However, apart
from the compiler-only barrier, the defined wmb() is correct only for
x86, or platforms which are similarly strongly ordered.
This patch addresses the FIXME about this by making the wmb() macro
arch dependent. On x86, it remains a compiler barrier only, but with
a comment explaining in more detail the conditions under which this is
correct. On weakly-ordered powerpc, an "eieio" instruction is used,
again with explanation of the conditions under which it is sufficient.
On other platforms, we use the __sync_synchronize() primitive,
available in sufficiently recent gcc (4.2 and after?). This should
implement a full barrier which will be sufficient on all platforms,
although it may be overkill in some cases. Other platforms can add
optimized versions in future if it's worth it for them.
Without proper memory barriers, it is easy to reproduce ordering
problems with virtio on powerpc; specifically, the QEMU puts new
element into the "used" ring and then updates the ring free-running
counter. Without a barrier between these under the right
circumstances, the guest linux driver can receive an interrupt, read
the counter change but find the ring element to be handled still has
an old value, leading to an "id %u is not a head!\n" error message.
Similar problems are likely to be possible with kvm on other weakly
ordered platforms.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-20 04:05:21 +02:00
|
|
|
|
2016-01-28 11:15:17 +01:00
|
|
|
/* These will only be atomic if the processor does the fetch or store
|
|
|
|
* in a single issue memory operation
|
|
|
|
*/
|
2016-10-24 19:29:32 +02:00
|
|
|
#define atomic_read__nocheck(p) (*(__typeof__(*(p)) volatile*) (p))
|
|
|
|
#define atomic_set__nocheck(p, i) ((*(__typeof__(*(p)) volatile*) (p)) = (i))
|
|
|
|
|
|
|
|
#define atomic_read(ptr) atomic_read__nocheck(ptr)
|
|
|
|
#define atomic_set(ptr, i) atomic_set__nocheck(ptr,i)
|
2013-05-13 13:29:47 +02:00
|
|
|
|
2013-05-13 13:29:47 +02:00
|
|
|
/**
|
|
|
|
* atomic_rcu_read - reads a RCU-protected pointer to a local variable
|
|
|
|
* into a RCU read-side critical section. The pointer can later be safely
|
|
|
|
* dereferenced within the critical section.
|
|
|
|
*
|
|
|
|
* This ensures that the pointer copy is invariant thorough the whole critical
|
|
|
|
* section.
|
|
|
|
*
|
|
|
|
* Inserts memory barriers on architectures that require them (currently only
|
|
|
|
* Alpha) and documents which pointers are protected by RCU.
|
|
|
|
*
|
2016-01-28 11:15:17 +01:00
|
|
|
* atomic_rcu_read also includes a compiler barrier to ensure that
|
|
|
|
* value-speculative optimizations (e.g. VSS: Value Speculation
|
|
|
|
* Scheduling) does not perform the data read before the pointer read
|
|
|
|
* by speculating the value of the pointer.
|
2013-05-13 13:29:47 +02:00
|
|
|
*
|
|
|
|
* Should match atomic_rcu_set(), atomic_xchg(), atomic_cmpxchg().
|
|
|
|
*/
|
|
|
|
#define atomic_rcu_read(ptr) ({ \
|
|
|
|
typeof(*ptr) _val = atomic_read(ptr); \
|
|
|
|
smp_read_barrier_depends(); \
|
|
|
|
_val; \
|
|
|
|
})
|
|
|
|
|
|
|
|
/**
|
|
|
|
* atomic_rcu_set - assigns (publicizes) a pointer to a new data structure
|
|
|
|
* meant to be read by RCU read-side critical sections.
|
|
|
|
*
|
|
|
|
* Documents which pointers will be dereferenced by RCU read-side critical
|
|
|
|
* sections and adds the required memory barriers on architectures requiring
|
|
|
|
* them. It also makes sure the compiler does not reorder code initializing the
|
|
|
|
* data structure before its publication.
|
|
|
|
*
|
|
|
|
* Should match atomic_rcu_read().
|
|
|
|
*/
|
|
|
|
#define atomic_rcu_set(ptr, i) do { \
|
|
|
|
smp_wmb(); \
|
|
|
|
atomic_set(ptr, i); \
|
|
|
|
} while (0)
|
|
|
|
|
2016-09-19 11:36:44 +02:00
|
|
|
#define atomic_load_acquire(ptr) ({ \
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2013-05-13 13:29:47 +02:00
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typeof(*ptr) _val = atomic_read(ptr); \
|
2016-09-19 10:50:38 +02:00
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|
smp_mb_acquire(); \
|
2013-05-13 13:29:47 +02:00
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_val; \
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|
})
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2016-09-19 11:36:44 +02:00
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|
#define atomic_store_release(ptr, i) do { \
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2016-09-19 10:50:38 +02:00
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smp_mb_release(); \
|
2013-05-13 13:29:47 +02:00
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|
atomic_set(ptr, i); \
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|
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|
} while (0)
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#ifndef atomic_xchg
|
2013-10-22 11:58:41 +02:00
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|
#if defined(__clang__)
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#define atomic_xchg(ptr, i) __sync_swap(ptr, i)
|
2013-05-13 13:29:47 +02:00
|
|
|
#else
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|
/* __sync_lock_test_and_set() is documented to be an acquire barrier only. */
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#define atomic_xchg(ptr, i) (smp_mb(), __sync_lock_test_and_set(ptr, i))
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|
#endif
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|
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#endif
|
2016-10-24 19:29:32 +02:00
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|
#define atomic_xchg__nocheck atomic_xchg
|
2013-05-13 13:29:47 +02:00
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|
/* Provide shorter names for GCC atomic builtins. */
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#define atomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1)
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|
#define atomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1)
|
2016-10-24 18:49:25 +02:00
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|
#define atomic_fetch_add(ptr, n) __sync_fetch_and_add(ptr, n)
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#define atomic_fetch_sub(ptr, n) __sync_fetch_and_sub(ptr, n)
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#define atomic_fetch_and(ptr, n) __sync_fetch_and_and(ptr, n)
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#define atomic_fetch_or(ptr, n) __sync_fetch_and_or(ptr, n)
|
2016-06-27 21:01:53 +02:00
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|
#define atomic_fetch_xor(ptr, n) __sync_fetch_and_xor(ptr, n)
|
2016-06-27 21:01:54 +02:00
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|
|
#define atomic_inc_fetch(ptr) __sync_add_and_fetch(ptr, 1)
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#define atomic_dec_fetch(ptr) __sync_add_and_fetch(ptr, -1)
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#define atomic_add_fetch(ptr, n) __sync_add_and_fetch(ptr, n)
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|
#define atomic_sub_fetch(ptr, n) __sync_sub_and_fetch(ptr, n)
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|
#define atomic_and_fetch(ptr, n) __sync_and_and_fetch(ptr, n)
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|
#define atomic_or_fetch(ptr, n) __sync_or_and_fetch(ptr, n)
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|
#define atomic_xor_fetch(ptr, n) __sync_xor_and_fetch(ptr, n)
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|
|
2016-10-24 18:49:25 +02:00
|
|
|
#define atomic_cmpxchg(ptr, old, new) __sync_val_compare_and_swap(ptr, old, new)
|
2016-10-24 19:29:32 +02:00
|
|
|
#define atomic_cmpxchg__nocheck(ptr, old, new) atomic_cmpxchg(ptr, old, new)
|
2013-05-13 13:29:47 +02:00
|
|
|
|
|
|
|
/* And even shorter names that return void. */
|
|
|
|
#define atomic_inc(ptr) ((void) __sync_fetch_and_add(ptr, 1))
|
|
|
|
#define atomic_dec(ptr) ((void) __sync_fetch_and_add(ptr, -1))
|
|
|
|
#define atomic_add(ptr, n) ((void) __sync_fetch_and_add(ptr, n))
|
|
|
|
#define atomic_sub(ptr, n) ((void) __sync_fetch_and_sub(ptr, n))
|
|
|
|
#define atomic_and(ptr, n) ((void) __sync_fetch_and_and(ptr, n))
|
|
|
|
#define atomic_or(ptr, n) ((void) __sync_fetch_and_or(ptr, n))
|
2016-06-27 21:01:53 +02:00
|
|
|
#define atomic_xor(ptr, n) ((void) __sync_fetch_and_xor(ptr, n))
|
2013-05-13 13:29:47 +02:00
|
|
|
|
2016-01-28 11:15:17 +01:00
|
|
|
#endif /* __ATOMIC_RELAXED */
|
2016-09-19 10:50:38 +02:00
|
|
|
|
|
|
|
#ifndef smp_wmb
|
|
|
|
#define smp_wmb() smp_mb_release()
|
|
|
|
#endif
|
|
|
|
#ifndef smp_rmb
|
|
|
|
#define smp_rmb() smp_mb_acquire()
|
|
|
|
#endif
|
|
|
|
|
2016-09-19 11:36:44 +02:00
|
|
|
/* This is more efficient than a store plus a fence. */
|
|
|
|
#if !defined(__SANITIZE_THREAD__)
|
|
|
|
#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__)
|
|
|
|
#define atomic_mb_set(ptr, i) ((void)atomic_xchg(ptr, i))
|
|
|
|
#endif
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* atomic_mb_read/set semantics map Java volatile variables. They are
|
|
|
|
* less expensive on some platforms (notably POWER) than fully
|
|
|
|
* sequentially consistent operations.
|
|
|
|
*
|
|
|
|
* As long as they are used as paired operations they are safe to
|
2017-07-29 00:46:04 +02:00
|
|
|
* use. See docs/devel/atomics.txt for more discussion.
|
2016-09-19 11:36:44 +02:00
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef atomic_mb_read
|
|
|
|
#define atomic_mb_read(ptr) \
|
|
|
|
atomic_load_acquire(ptr)
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifndef atomic_mb_set
|
|
|
|
#define atomic_mb_set(ptr, i) do { \
|
|
|
|
atomic_store_release(ptr, i); \
|
|
|
|
smp_mb(); \
|
|
|
|
} while(0)
|
|
|
|
#endif
|
|
|
|
|
2017-09-21 14:32:47 +02:00
|
|
|
#define atomic_fetch_inc_nonzero(ptr) ({ \
|
|
|
|
typeof_strip_qual(*ptr) _oldn = atomic_read(ptr); \
|
|
|
|
while (_oldn && atomic_cmpxchg(ptr, _oldn, _oldn + 1) != _oldn) { \
|
|
|
|
_oldn = atomic_read(ptr); \
|
|
|
|
} \
|
|
|
|
_oldn; \
|
|
|
|
})
|
|
|
|
|
2018-09-11 01:27:42 +02:00
|
|
|
/* Abstractions to access atomically (i.e. "once") i64/u64 variables */
|
|
|
|
#ifdef CONFIG_ATOMIC64
|
|
|
|
static inline int64_t atomic_read_i64(const int64_t *ptr)
|
|
|
|
{
|
|
|
|
/* use __nocheck because sizeof(void *) might be < sizeof(u64) */
|
|
|
|
return atomic_read__nocheck(ptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline uint64_t atomic_read_u64(const uint64_t *ptr)
|
|
|
|
{
|
|
|
|
return atomic_read__nocheck(ptr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void atomic_set_i64(int64_t *ptr, int64_t val)
|
|
|
|
{
|
|
|
|
atomic_set__nocheck(ptr, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void atomic_set_u64(uint64_t *ptr, uint64_t val)
|
|
|
|
{
|
|
|
|
atomic_set__nocheck(ptr, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void atomic64_init(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#else /* !CONFIG_ATOMIC64 */
|
|
|
|
int64_t atomic_read_i64(const int64_t *ptr);
|
|
|
|
uint64_t atomic_read_u64(const uint64_t *ptr);
|
|
|
|
void atomic_set_i64(int64_t *ptr, int64_t val);
|
|
|
|
void atomic_set_u64(uint64_t *ptr, uint64_t val);
|
|
|
|
void atomic64_init(void);
|
|
|
|
#endif /* !CONFIG_ATOMIC64 */
|
|
|
|
|
2016-06-29 13:47:03 +02:00
|
|
|
#endif /* QEMU_ATOMIC_H */
|