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qemu-e2k/target/arm/a32.decode

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target/arm: Add stubs for aa32 decodetree Add the infrastructure that will become the new decoder. No instructions adjusted so far. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:52 +02:00
# A32 conditional instructions
#
# Copyright (c) 2019 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#
# All of the insn that have a COND field in insn[31:28] are here.
# All insns that have 0xf in insn[31:28] are in a32-uncond.decode.
#
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:53 +02:00
&s_rrr_shi s rd rn rm shim shty
target/arm: Convert Data Processing (reg-shifted-reg) Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:54 +02:00
&s_rrr_shr s rn rd rm rs shty
target/arm: Convert Data Processing (immediate) Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:55 +02:00
&s_rri_rot s rn rd imm rot
target/arm: Convert multiply and multiply accumulate Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:56 +02:00
&s_rrrr s rd rn rm ra
&rrrr rd rn rm ra
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:53 +02:00
# Data-processing (register)
@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \
&s_rrr_shi
@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \
&s_rrr_shi rn=0
@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \
&s_rrr_shi s=1 rd=0
AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi
EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi
SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi
RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi
ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi
ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi
SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi
RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi
TST_xrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi
TEQ_xrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi
CMP_xrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi
CMN_xrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi
ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi
MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi
BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi
MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi
target/arm: Convert Data Processing (reg-shifted-reg) Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:54 +02:00
# Data-processing (register-shifted register)
@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
&s_rrr_shr
@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \
&s_rrr_shr rn=0
@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \
&s_rrr_shr rd=0 s=1
AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr
EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr
SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr
RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr
ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr
ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr
SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr
RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr
TST_xrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
TEQ_xrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
CMP_xrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
CMN_xrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr
ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr
MOV_rxrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr
BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr
MVN_rxrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr
target/arm: Convert Data Processing (immediate) Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:55 +02:00
# Data-processing (immediate)
%a32extrot 8:4 !function=times_2
@s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \
&s_rri_rot rot=%a32extrot
@s_rxi_rot ---- ... .... s:1 .... rd:4 .... imm:8 \
&s_rri_rot rot=%a32extrot rn=0
@S_xri_rot ---- ... .... . rn:4 .... .... imm:8 \
&s_rri_rot rot=%a32extrot rd=0 s=1
AND_rri .... 001 0000 . .... .... ............ @s_rri_rot
EOR_rri .... 001 0001 . .... .... ............ @s_rri_rot
SUB_rri .... 001 0010 . .... .... ............ @s_rri_rot
RSB_rri .... 001 0011 . .... .... ............ @s_rri_rot
ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot
ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot
SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot
RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot
TST_xri .... 001 1000 1 .... 0000 ............ @S_xri_rot
TEQ_xri .... 001 1001 1 .... 0000 ............ @S_xri_rot
CMP_xri .... 001 1010 1 .... 0000 ............ @S_xri_rot
CMN_xri .... 001 1011 1 .... 0000 ............ @S_xri_rot
ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot
MOV_rxi .... 001 1101 . 0000 .... ............ @s_rxi_rot
BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot
MVN_rxi .... 001 1111 . 0000 .... ............ @s_rxi_rot
target/arm: Convert multiply and multiply accumulate Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:56 +02:00
# Multiply and multiply accumulate
@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr
@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0
@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr
MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn
MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn
UMAAL .... 0000 010 0 .... .... .... 1001 .... @rdamn
MLS .... 0000 011 0 .... .... .... 1001 .... @rdamn
UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn
UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn
SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn
SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn