2021-07-27 23:10:22 +02:00
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/*
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* Memory helpers that will be used by TCG generated code.
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef TCG_LDST_H
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2022-05-06 15:49:10 +02:00
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#define TCG_LDST_H
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2021-07-27 23:10:22 +02:00
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/* Value zero-extended to tcg register size. */
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2023-04-26 23:09:47 +02:00
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tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr,
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2023-02-15 09:16:17 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2021-07-27 23:10:22 +02:00
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/* Value sign-extended to tcg register size. */
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2023-04-26 23:09:47 +02:00
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tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2021-07-27 23:10:22 +02:00
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2023-04-10 07:11:39 +02:00
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/*
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* Value extended to at least uint32_t, so that some ABIs do not require
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* zero-extension from uint8_t or uint16_t.
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*/
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2023-04-26 23:09:47 +02:00
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void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val,
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2022-11-01 02:51:04 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2023-04-26 23:09:47 +02:00
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void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val,
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2023-02-15 09:16:17 +01:00
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MemOpIdx oi, uintptr_t retaddr);
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2021-07-27 23:10:22 +02:00
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#endif /* TCG_LDST_H */
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