2022-04-29 16:40:40 +02:00
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/*
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* QTest testcase for CXL
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "libqtest-single.h"
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2022-04-29 16:40:47 +02:00
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#define QEMU_PXB_CMD "-machine q35,cxl=on " \
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2022-04-29 16:41:04 +02:00
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"-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
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2022-06-08 16:54:33 +02:00
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"-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G "
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2022-04-29 16:40:47 +02:00
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2022-04-29 16:41:04 +02:00
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#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
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2022-04-29 16:40:47 +02:00
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"-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
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2022-04-29 16:41:04 +02:00
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"-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
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2022-06-08 16:54:33 +02:00
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"-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
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2022-04-29 16:40:47 +02:00
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#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
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/* Dual ports on first pxb */
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#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
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"-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
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/* Dual ports on each of the pxb instances */
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#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
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"-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
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"-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
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"-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
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#define QEMU_T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
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"-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
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"-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 "
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#define QEMU_2T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
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"-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
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"-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
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"-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
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"-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
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"-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 "
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#define QEMU_4T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
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"-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
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"-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
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"-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
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"-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
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"-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \
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"-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M " \
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"-object memory-backend-file,id=lsa2,mem-path=%s,size=256M " \
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"-device cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \
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"-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \
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"-object memory-backend-file,id=lsa3,mem-path=%s,size=256M " \
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"-device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 "
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static void cxl_basic_hb(void)
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{
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qtest_start("-machine q35,cxl=on");
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qtest_end();
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}
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2022-04-29 16:40:40 +02:00
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static void cxl_basic_pxb(void)
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{
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qtest_start("-machine q35,cxl=on -device pxb-cxl,bus=pcie.0");
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qtest_end();
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}
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2022-04-29 16:40:47 +02:00
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static void cxl_pxb_with_window(void)
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{
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qtest_start(QEMU_PXB_CMD);
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qtest_end();
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}
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static void cxl_2pxb_with_window(void)
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{
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qtest_start(QEMU_2PXB_CMD);
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qtest_end();
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}
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static void cxl_root_port(void)
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{
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qtest_start(QEMU_PXB_CMD QEMU_RP);
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qtest_end();
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}
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static void cxl_2root_port(void)
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{
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qtest_start(QEMU_PXB_CMD QEMU_2RP);
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qtest_end();
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}
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2022-08-24 11:39:56 +02:00
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#ifdef CONFIG_POSIX
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2022-04-29 16:40:47 +02:00
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static void cxl_t3d(void)
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{
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g_autoptr(GString) cmdline = g_string_new(NULL);
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g_autofree const char *tmpfs = NULL;
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2022-09-25 13:29:46 +02:00
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tmpfs = g_dir_make_tmp("cxl-test-XXXXXX", NULL);
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g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs, tmpfs);
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qtest_start(cmdline->str);
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qtest_end();
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2022-10-12 11:14:35 +02:00
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rmdir(tmpfs);
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}
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static void cxl_1pxb_2rp_2t3d(void)
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{
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g_autoptr(GString) cmdline = g_string_new(NULL);
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2022-09-25 13:29:46 +02:00
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g_autofree const char *tmpfs = NULL;
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2022-04-29 16:40:47 +02:00
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2022-09-25 13:29:46 +02:00
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tmpfs = g_dir_make_tmp("cxl-test-XXXXXX", NULL);
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2022-04-29 16:40:47 +02:00
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g_string_printf(cmdline, QEMU_PXB_CMD QEMU_2RP QEMU_2T3D,
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tmpfs, tmpfs, tmpfs, tmpfs);
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qtest_start(cmdline->str);
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qtest_end();
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2022-10-12 11:14:35 +02:00
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rmdir(tmpfs);
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2022-04-29 16:40:47 +02:00
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}
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static void cxl_2pxb_4rp_4t3d(void)
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{
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g_autoptr(GString) cmdline = g_string_new(NULL);
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2022-09-25 13:29:46 +02:00
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g_autofree const char *tmpfs = NULL;
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2022-04-29 16:40:47 +02:00
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2022-09-25 13:29:46 +02:00
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tmpfs = g_dir_make_tmp("cxl-test-XXXXXX", NULL);
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2022-04-29 16:40:47 +02:00
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g_string_printf(cmdline, QEMU_2PXB_CMD QEMU_4RP QEMU_4T3D,
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tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs,
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tmpfs, tmpfs);
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qtest_start(cmdline->str);
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qtest_end();
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2022-10-12 11:14:35 +02:00
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rmdir(tmpfs);
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2022-04-29 16:40:47 +02:00
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}
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2022-08-24 11:39:56 +02:00
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#endif /* CONFIG_POSIX */
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2022-04-29 16:40:47 +02:00
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2022-04-29 16:40:40 +02:00
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int main(int argc, char **argv)
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{
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g_test_init(&argc, &argv, NULL);
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2022-04-29 16:40:47 +02:00
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qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
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2022-04-29 16:40:40 +02:00
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qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
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2022-04-29 16:40:47 +02:00
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qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
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qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
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qtest_add_func("/pci/cxl/rp", cxl_root_port);
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qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
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2022-08-24 11:39:56 +02:00
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#ifdef CONFIG_POSIX
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qtest_add_func("/pci/cxl/type3_device", cxl_t3d);
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qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
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qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d);
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#endif
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return g_test_run();
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}
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