349 lines
9.6 KiB
C
349 lines
9.6 KiB
C
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/*
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* DDR2 SDRAM controller:
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2019 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h" /* get_system_memory() */
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/ppc/ppc4xx.h"
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#include "trace.h"
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/*****************************************************************************/
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/* Shared functions */
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static void sdram_bank_map(Ppc4xxSdramBank *bank)
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{
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memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
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memory_region_add_subregion(&bank->container, 0, &bank->ram);
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memory_region_add_subregion(get_system_memory(), bank->base,
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&bank->container);
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}
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static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
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{
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memory_region_del_subregion(get_system_memory(), &bank->container);
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memory_region_del_subregion(&bank->container, &bank->ram);
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object_unparent(OBJECT(&bank->container));
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}
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enum {
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SDRAM0_CFGADDR = 0x010,
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SDRAM0_CFGDATA = 0x011,
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};
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/*****************************************************************************/
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/* DDR2 SDRAM controller */
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enum {
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SDRAM_R0BAS = 0x40,
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SDRAM_R1BAS,
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SDRAM_R2BAS,
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SDRAM_R3BAS,
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SDRAM_CONF1HB = 0x45,
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SDRAM_PLBADDULL = 0x4a,
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SDRAM_CONF1LL = 0x4b,
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SDRAM_CONFPATHB = 0x4f,
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SDRAM_PLBADDUHB = 0x50,
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};
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static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
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{
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uint32_t bcr;
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switch (ram_size) {
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case 8 * MiB:
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bcr = 0xffc0;
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break;
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case 16 * MiB:
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bcr = 0xff80;
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break;
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case 32 * MiB:
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bcr = 0xff00;
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break;
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case 64 * MiB:
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bcr = 0xfe00;
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break;
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case 128 * MiB:
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bcr = 0xfc00;
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break;
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case 256 * MiB:
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bcr = 0xf800;
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break;
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case 512 * MiB:
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bcr = 0xf000;
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break;
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case 1 * GiB:
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bcr = 0xe000;
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break;
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case 2 * GiB:
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bcr = 0xc000;
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break;
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case 4 * GiB:
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bcr = 0x8000;
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break;
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default:
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error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
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return 0;
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}
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bcr |= ram_base >> 2 & 0xffe00000;
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bcr |= 1;
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return bcr;
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}
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static inline hwaddr sdram_ddr2_base(uint32_t bcr)
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{
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return (bcr & 0xffe00000) << 2;
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}
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static uint64_t sdram_ddr2_size(uint32_t bcr)
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{
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uint64_t size;
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int sh;
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sh = 1024 - ((bcr >> 6) & 0x3ff);
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size = 8 * MiB * sh;
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return size;
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}
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static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i,
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uint32_t bcr, int enabled)
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{
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if (sdram->bank[i].bcr & 1) {
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/* First unmap RAM if enabled */
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trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr),
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sdram_ddr2_size(sdram->bank[i].bcr));
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sdram_bank_unmap(&sdram->bank[i]);
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}
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sdram->bank[i].bcr = bcr & 0xffe0ffc1;
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if (enabled && (bcr & 1)) {
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trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr));
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sdram_bank_map(&sdram->bank[i]);
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}
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}
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static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram)
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{
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int i;
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for (i = 0; i < sdram->nbanks; i++) {
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if (sdram->bank[i].size) {
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sdram_ddr2_set_bcr(sdram, i,
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sdram_ddr2_bcr(sdram->bank[i].base,
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sdram->bank[i].size), 1);
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} else {
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sdram_ddr2_set_bcr(sdram, i, 0, 0);
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}
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}
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}
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static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram)
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{
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int i;
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for (i = 0; i < sdram->nbanks; i++) {
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if (sdram->bank[i].size) {
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sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
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}
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}
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}
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static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
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{
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Ppc4xxSdramDdr2State *sdram = opaque;
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uint32_t ret = 0;
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switch (dcrn) {
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case SDRAM_R0BAS:
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case SDRAM_R1BAS:
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case SDRAM_R2BAS:
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case SDRAM_R3BAS:
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if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
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ret = sdram_ddr2_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
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sdram->bank[dcrn - SDRAM_R0BAS].size);
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}
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break;
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case SDRAM_CONF1HB:
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case SDRAM_CONF1LL:
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case SDRAM_CONFPATHB:
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case SDRAM_PLBADDULL:
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case SDRAM_PLBADDUHB:
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break;
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case SDRAM0_CFGADDR:
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ret = sdram->addr;
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break;
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case SDRAM0_CFGDATA:
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switch (sdram->addr) {
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case 0x14: /* SDRAM_MCSTAT (405EX) */
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case 0x1F:
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ret = 0x80000000;
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break;
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case 0x21: /* SDRAM_MCOPT2 */
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ret = sdram->mcopt2;
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break;
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case 0x40: /* SDRAM_MB0CF */
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ret = 0x00008001;
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break;
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case 0x7A: /* SDRAM_DLCR */
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ret = 0x02000000;
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break;
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case 0xE1: /* SDR0_DDR0 */
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ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return ret;
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}
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#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
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static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
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{
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Ppc4xxSdramDdr2State *sdram = opaque;
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switch (dcrn) {
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case SDRAM_R0BAS:
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case SDRAM_R1BAS:
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case SDRAM_R2BAS:
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case SDRAM_R3BAS:
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case SDRAM_CONF1HB:
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case SDRAM_CONF1LL:
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case SDRAM_CONFPATHB:
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case SDRAM_PLBADDULL:
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case SDRAM_PLBADDUHB:
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break;
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case SDRAM0_CFGADDR:
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sdram->addr = val;
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break;
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case SDRAM0_CFGDATA:
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switch (sdram->addr) {
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case 0x00: /* B0CR */
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break;
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case 0x21: /* SDRAM_MCOPT2 */
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if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
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(val & SDRAM_DDR2_MCOPT2_DCEN)) {
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trace_ppc4xx_sdram_enable("enable");
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/* validate all RAM mappings */
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sdram_ddr2_map_bcr(sdram);
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sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
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} else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
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!(val & SDRAM_DDR2_MCOPT2_DCEN)) {
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trace_ppc4xx_sdram_enable("disable");
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/* invalidate all RAM mappings */
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sdram_ddr2_unmap_bcr(sdram);
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sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
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}
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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}
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static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
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{
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Ppc4xxSdramDdr2State *sdram = PPC4xx_SDRAM_DDR2(dev);
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sdram->addr = 0;
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sdram->mcopt2 = 0;
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}
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static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
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{
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Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
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Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
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/*
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* SoC also has 4 GiB but that causes problem with 32 bit
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* builds (4*GiB overflows the 32 bit ram_addr_t).
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*/
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const ram_addr_t valid_bank_sizes[] = {
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2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB,
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64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
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};
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if (s->nbanks < 1 || s->nbanks > 4) {
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error_setg(errp, "Invalid number of RAM banks");
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return;
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}
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if (!s->dram_mr) {
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error_setg(errp, "Missing dram memory region");
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return;
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}
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ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes);
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ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
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s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
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}
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static Property ppc4xx_sdram_ddr2_props[] = {
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DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = ppc4xx_sdram_ddr2_realize;
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dc->reset = ppc4xx_sdram_ddr2_reset;
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/* Reason: only works as function of a ppc4xx SoC */
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dc->user_creatable = false;
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device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
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}
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void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s)
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{
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sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21);
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sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000);
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}
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static const TypeInfo ppc4xx_sdram_types[] = {
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{
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.name = TYPE_PPC4xx_SDRAM_DDR2,
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.parent = TYPE_PPC4xx_DCR_DEVICE,
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.instance_size = sizeof(Ppc4xxSdramDdr2State),
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.class_init = ppc4xx_sdram_ddr2_class_init,
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}
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};
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||
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DEFINE_TYPES(ppc4xx_sdram_types)
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