2010-07-13 06:01:39 +02:00
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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to dea
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* split out from pci.c
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*/
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2016-01-26 19:17:15 +01:00
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#include "qemu/osdep.h"
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hw/pci/pci_bridge: Correct pci_bridge_io memory region size
memory_region_set_size() handle the 16 Exabytes limit by
special-casing the UINT64_MAX value. This is not a problem
for the 32-bit maximum, 4 GiB.
By using the UINT32_MAX value, the pci_bridge_io MemoryRegion
ends up missing 1 byte:
(qemu) info mtree
memory-region: pci_bridge_io
0000000000000000-00000000fffffffe (prio 0, i/o): pci_bridge_io
0000000000000060-0000000000000060 (prio 0, i/o): i8042-data
0000000000000064-0000000000000064 (prio 0, i/o): i8042-cmd
00000000000001ce-00000000000001d1 (prio 0, i/o): vbe
0000000000000378-000000000000037f (prio 0, i/o): parallel
00000000000003b4-00000000000003b5 (prio 0, i/o): vga
...
Fix by using the correct value. We now have:
memory-region: pci_bridge_io
0000000000000000-00000000ffffffff (prio 0, i/o): pci_bridge_io
0000000000000060-0000000000000060 (prio 0, i/o): i8042-data
0000000000000064-0000000000000064 (prio 0, i/o): i8042-cmd
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200601142930.29408-4-f4bug@amsat.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-01 16:29:25 +02:00
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#include "qemu/units.h"
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2012-12-12 22:05:42 +01:00
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#include "hw/pci/pci_bridge.h"
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2012-12-12 14:00:45 +01:00
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#include "hw/pci/pci_bus.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/range.h"
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2017-06-27 08:16:50 +02:00
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#include "qapi/error.h"
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2010-07-13 06:01:39 +02:00
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2010-09-06 09:46:17 +02:00
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/* PCI bridge subsystem vendor ID helper functions */
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#define PCI_SSVID_SIZEOF 8
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#define PCI_SSVID_SVID 4
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#define PCI_SSVID_SSID 6
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int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
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2017-06-27 08:16:52 +02:00
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uint16_t svid, uint16_t ssid,
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Error **errp)
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2010-09-06 09:46:17 +02:00
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{
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int pos;
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2017-06-27 08:16:50 +02:00
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pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
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2017-06-27 08:16:52 +02:00
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PCI_SSVID_SIZEOF, errp);
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2010-09-06 09:46:17 +02:00
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if (pos < 0) {
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return pos;
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}
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pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
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pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
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return pos;
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}
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2010-07-13 06:01:42 +02:00
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/* Accessor function to get parent bridge device from pci bus. */
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2010-07-13 06:01:39 +02:00
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PCIDevice *pci_bridge_get_device(PCIBus *bus)
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{
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return bus->parent_dev;
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}
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2010-07-13 06:01:42 +02:00
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/* Accessor function to get secondary bus from pci-to-pci bridge device */
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PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
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{
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return &br->sec_bus;
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}
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static uint32_t pci_config_get_io_base(const PCIDevice *d,
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2010-07-13 06:01:39 +02:00
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uint32_t base, uint32_t base_upper16)
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{
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uint32_t val;
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val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
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if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
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val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
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}
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return val;
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}
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2010-07-13 06:01:42 +02:00
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static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
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2010-07-13 06:01:39 +02:00
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{
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return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
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<< 16;
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}
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2010-07-13 06:01:42 +02:00
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static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
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2010-07-13 06:01:39 +02:00
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uint32_t base, uint32_t upper)
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{
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pcibus_t tmp;
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pcibus_t val;
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tmp = (pcibus_t)pci_get_word(d->config + base);
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val = (tmp & PCI_PREF_RANGE_MASK) << 16;
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if (tmp & PCI_PREF_RANGE_TYPE_64) {
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val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
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}
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return val;
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}
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2010-07-13 06:01:42 +02:00
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/* accessor function to get bridge filtering base address */
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pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
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2010-07-13 06:01:39 +02:00
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{
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pcibus_t base;
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if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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base = pci_config_get_io_base(bridge,
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PCI_IO_BASE, PCI_IO_BASE_UPPER16);
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} else {
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if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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base = pci_config_get_pref_base(
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bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
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} else {
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base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
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}
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}
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return base;
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}
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2016-03-23 15:59:57 +01:00
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/* accessor function to get bridge filtering limit */
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2010-07-13 06:01:42 +02:00
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pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
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2010-07-13 06:01:39 +02:00
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{
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pcibus_t limit;
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if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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limit = pci_config_get_io_base(bridge,
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PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
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limit |= 0xfff; /* PCI bridge spec 3.2.5.6. */
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} else {
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if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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limit = pci_config_get_pref_base(
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bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
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} else {
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limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
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}
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limit |= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
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}
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return limit;
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}
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2011-09-04 15:50:55 +02:00
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static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
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uint8_t type, const char *name,
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MemoryRegion *space,
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MemoryRegion *parent_space,
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bool enabled)
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{
|
2013-07-11 17:13:43 +02:00
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PCIDevice *bridge_dev = PCI_DEVICE(bridge);
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pcibus_t base = pci_bridge_get_base(bridge_dev, type);
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pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
|
2011-09-04 15:50:55 +02:00
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/* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
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* Apparently no way to do this with existing memory APIs. */
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pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
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2013-06-07 03:25:08 +02:00
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memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
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2011-09-04 15:50:55 +02:00
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memory_region_add_subregion_overlap(parent_space, base, alias, 1);
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}
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2013-03-03 18:21:32 +01:00
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static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
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MemoryRegion *alias_vga)
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{
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2013-07-11 17:13:43 +02:00
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PCIDevice *pd = PCI_DEVICE(br);
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uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);
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2013-03-03 18:21:32 +01:00
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2013-06-07 03:25:08 +02:00
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memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
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2013-03-03 18:21:32 +01:00
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"pci_bridge_vga_io_lo", &br->address_space_io,
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QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
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2013-06-07 03:25:08 +02:00
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memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
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2013-03-03 18:21:32 +01:00
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"pci_bridge_vga_io_hi", &br->address_space_io,
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QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
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2013-06-07 03:25:08 +02:00
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memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
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2013-03-03 18:21:32 +01:00
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"pci_bridge_vga_mem", &br->address_space_mem,
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QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
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if (brctl & PCI_BRIDGE_CTL_VGA) {
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2013-07-11 17:13:43 +02:00
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pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
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2013-03-03 18:21:32 +01:00
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&alias_vga[QEMU_PCI_VGA_IO_LO],
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&alias_vga[QEMU_PCI_VGA_IO_HI]);
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}
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}
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2012-10-25 12:37:57 +02:00
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static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)
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2011-09-04 15:50:55 +02:00
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{
|
2013-07-11 17:13:43 +02:00
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PCIDevice *pd = PCI_DEVICE(br);
|
2017-11-29 09:46:27 +01:00
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PCIBus *parent = pci_get_bus(pd);
|
2012-10-25 12:37:57 +02:00
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PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1);
|
2013-07-11 17:13:43 +02:00
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uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);
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2011-09-04 15:50:55 +02:00
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2012-10-25 12:37:57 +02:00
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pci_bridge_init_alias(br, &w->alias_pref_mem,
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2011-09-04 15:50:55 +02:00
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PCI_BASE_ADDRESS_MEM_PREFETCH,
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"pci_bridge_pref_mem",
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2011-09-06 19:58:22 +02:00
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&br->address_space_mem,
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2011-09-04 15:50:55 +02:00
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parent->address_space_mem,
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cmd & PCI_COMMAND_MEMORY);
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2012-10-25 12:37:57 +02:00
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pci_bridge_init_alias(br, &w->alias_mem,
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2011-09-04 15:50:55 +02:00
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PCI_BASE_ADDRESS_SPACE_MEMORY,
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"pci_bridge_mem",
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2011-09-06 19:58:22 +02:00
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&br->address_space_mem,
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2011-09-04 15:50:55 +02:00
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parent->address_space_mem,
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cmd & PCI_COMMAND_MEMORY);
|
2012-10-25 12:37:57 +02:00
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pci_bridge_init_alias(br, &w->alias_io,
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2011-09-04 15:50:55 +02:00
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PCI_BASE_ADDRESS_SPACE_IO,
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"pci_bridge_io",
|
2011-09-06 19:58:22 +02:00
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&br->address_space_io,
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2011-09-04 15:50:55 +02:00
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parent->address_space_io,
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cmd & PCI_COMMAND_IO);
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2013-03-03 18:21:32 +01:00
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pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
|
2012-10-25 12:37:57 +02:00
|
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return w;
|
2011-09-04 15:50:55 +02:00
|
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}
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2012-10-25 12:37:57 +02:00
|
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static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
|
2011-09-04 15:50:55 +02:00
|
|
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{
|
2013-07-11 17:13:43 +02:00
|
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PCIDevice *pd = PCI_DEVICE(br);
|
2017-11-29 09:46:27 +01:00
|
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PCIBus *parent = pci_get_bus(pd);
|
2012-10-25 12:37:57 +02:00
|
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memory_region_del_subregion(parent->address_space_io, &w->alias_io);
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memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
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memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
|
2013-07-11 17:13:43 +02:00
|
|
|
pci_unregister_vga(pd);
|
2012-10-25 12:37:57 +02:00
|
|
|
}
|
|
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|
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|
|
|
static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
|
|
|
|
{
|
2014-08-20 17:50:05 +02:00
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object_unparent(OBJECT(&w->alias_io));
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|
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object_unparent(OBJECT(&w->alias_mem));
|
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object_unparent(OBJECT(&w->alias_pref_mem));
|
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object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO]));
|
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object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI]));
|
|
|
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object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM]));
|
2012-10-25 12:37:57 +02:00
|
|
|
g_free(w);
|
2011-09-04 15:50:55 +02:00
|
|
|
}
|
|
|
|
|
2013-07-09 17:40:02 +02:00
|
|
|
void pci_bridge_update_mappings(PCIBridge *br)
|
2011-09-04 15:50:55 +02:00
|
|
|
{
|
2012-10-25 12:37:57 +02:00
|
|
|
PCIBridgeWindows *w = br->windows;
|
|
|
|
|
2011-09-04 15:50:55 +02:00
|
|
|
/* Make updates atomic to: handle the case of one VCPU updating the bridge
|
|
|
|
* while another accesses an unaffected region. */
|
|
|
|
memory_region_transaction_begin();
|
2012-10-25 12:37:57 +02:00
|
|
|
pci_bridge_region_del(br, br->windows);
|
2018-12-10 14:00:48 +01:00
|
|
|
pci_bridge_region_cleanup(br, w);
|
2012-10-25 12:37:57 +02:00
|
|
|
br->windows = pci_bridge_region_init(br);
|
2011-09-04 15:50:55 +02:00
|
|
|
memory_region_transaction_commit();
|
|
|
|
}
|
|
|
|
|
2010-07-13 06:01:42 +02:00
|
|
|
/* default write_config function for PCI-to-PCI bridge */
|
|
|
|
void pci_bridge_write_config(PCIDevice *d,
|
2010-07-13 06:01:39 +02:00
|
|
|
uint32_t address, uint32_t val, int len)
|
|
|
|
{
|
2013-07-11 17:13:43 +02:00
|
|
|
PCIBridge *s = PCI_BRIDGE(d);
|
2010-11-19 10:56:03 +01:00
|
|
|
uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
|
|
|
|
uint16_t newctl;
|
|
|
|
|
2010-07-13 06:01:39 +02:00
|
|
|
pci_default_write_config(d, address, val, len);
|
|
|
|
|
2011-09-04 15:50:55 +02:00
|
|
|
if (ranges_overlap(address, len, PCI_COMMAND, 2) ||
|
|
|
|
|
|
|
|
/* io base/limit */
|
2010-07-13 06:01:39 +02:00
|
|
|
ranges_overlap(address, len, PCI_IO_BASE, 2) ||
|
|
|
|
|
|
|
|
/* memory base/limit, prefetchable base/limit and
|
|
|
|
io base/limit upper 16 */
|
2013-03-03 18:21:32 +01:00
|
|
|
ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||
|
|
|
|
|
|
|
|
/* vga enable */
|
|
|
|
ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
|
2011-09-04 15:50:55 +02:00
|
|
|
pci_bridge_update_mappings(s);
|
2010-07-13 06:01:39 +02:00
|
|
|
}
|
2010-11-19 10:56:03 +01:00
|
|
|
|
|
|
|
newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
|
|
|
|
if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
|
|
|
|
/* Trigger hot reset on 0->1 transition. */
|
2022-12-16 16:55:26 +01:00
|
|
|
bus_cold_reset(BUS(&s->sec_bus));
|
2010-11-19 10:56:03 +01:00
|
|
|
}
|
2010-07-13 06:01:39 +02:00
|
|
|
}
|
|
|
|
|
2010-10-20 10:18:51 +02:00
|
|
|
void pci_bridge_disable_base_limit(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
uint8_t *conf = dev->config;
|
|
|
|
|
|
|
|
pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
|
|
|
|
PCI_IO_RANGE_MASK & 0xff);
|
|
|
|
pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
|
|
|
|
PCI_IO_RANGE_MASK & 0xff);
|
|
|
|
pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
|
|
|
|
PCI_MEMORY_RANGE_MASK & 0xffff);
|
|
|
|
pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
|
|
|
|
PCI_MEMORY_RANGE_MASK & 0xffff);
|
|
|
|
pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
|
|
|
|
PCI_PREF_RANGE_MASK & 0xffff);
|
|
|
|
pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
|
|
|
|
PCI_PREF_RANGE_MASK & 0xffff);
|
2012-03-04 14:35:29 +01:00
|
|
|
pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
|
|
|
|
pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
|
2010-10-20 10:18:51 +02:00
|
|
|
}
|
|
|
|
|
2010-07-13 06:01:42 +02:00
|
|
|
/* reset bridge specific configuration registers */
|
2012-05-16 01:09:56 +02:00
|
|
|
void pci_bridge_reset(DeviceState *qdev)
|
2010-07-13 06:01:42 +02:00
|
|
|
{
|
2012-05-16 01:09:56 +02:00
|
|
|
PCIDevice *dev = PCI_DEVICE(qdev);
|
2010-07-13 06:01:42 +02:00
|
|
|
uint8_t *conf = dev->config;
|
|
|
|
|
|
|
|
conf[PCI_PRIMARY_BUS] = 0;
|
|
|
|
conf[PCI_SECONDARY_BUS] = 0;
|
|
|
|
conf[PCI_SUBORDINATE_BUS] = 0;
|
|
|
|
conf[PCI_SEC_LATENCY_TIMER] = 0;
|
|
|
|
|
2010-10-20 10:18:51 +02:00
|
|
|
/*
|
|
|
|
* the default values for base/limit registers aren't specified
|
2019-09-09 05:14:46 +02:00
|
|
|
* in the PCI-to-PCI-bridge spec. So we don't touch them here.
|
2010-10-20 10:18:51 +02:00
|
|
|
* Each implementation can override it.
|
|
|
|
* typical implementation does
|
|
|
|
* zero base/limit registers or
|
|
|
|
* disable forwarding: pci_bridge_disable_base_limit()
|
|
|
|
* If disable forwarding is wanted, call pci_bridge_disable_base_limit()
|
|
|
|
* after this function.
|
|
|
|
*/
|
|
|
|
pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
|
|
|
|
PCI_IO_RANGE_MASK & 0xff);
|
|
|
|
pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
|
|
|
|
PCI_IO_RANGE_MASK & 0xff);
|
|
|
|
pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
|
|
|
|
PCI_MEMORY_RANGE_MASK & 0xffff);
|
|
|
|
pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
|
|
|
|
PCI_MEMORY_RANGE_MASK & 0xffff);
|
|
|
|
pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
|
|
|
|
PCI_PREF_RANGE_MASK & 0xffff);
|
|
|
|
pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
|
|
|
|
PCI_PREF_RANGE_MASK & 0xffff);
|
2012-03-04 14:35:29 +01:00
|
|
|
pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
|
|
|
|
pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
|
2010-07-13 06:01:42 +02:00
|
|
|
|
|
|
|
pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* default qdev initialization function for PCI-to-PCI bridge */
|
2016-01-15 03:23:32 +01:00
|
|
|
void pci_bridge_initfn(PCIDevice *dev, const char *typename)
|
2010-07-13 06:01:42 +02:00
|
|
|
{
|
2017-11-29 09:46:27 +01:00
|
|
|
PCIBus *parent = pci_get_bus(dev);
|
2013-07-11 17:13:43 +02:00
|
|
|
PCIBridge *br = PCI_BRIDGE(dev);
|
2010-07-13 06:01:42 +02:00
|
|
|
PCIBus *sec_bus = &br->sec_bus;
|
2010-07-13 06:01:39 +02:00
|
|
|
|
2012-02-12 20:02:01 +01:00
|
|
|
pci_word_test_and_set_mask(dev->config + PCI_STATUS,
|
|
|
|
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
|
2013-03-03 18:21:32 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* TODO: We implement VGA Enable in the Bridge Control Register
|
|
|
|
* therefore per the PCI to PCI bridge spec we must also implement
|
|
|
|
* VGA Palette Snooping. When done, set this bit writable:
|
|
|
|
*
|
|
|
|
* pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
|
|
|
|
* PCI_COMMAND_VGA_PALETTE);
|
|
|
|
*/
|
|
|
|
|
2010-07-13 06:01:39 +02:00
|
|
|
pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
|
|
|
|
dev->config[PCI_HEADER_TYPE] =
|
|
|
|
(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
|
|
|
|
PCI_HEADER_TYPE_BRIDGE;
|
|
|
|
pci_set_word(dev->config + PCI_SEC_STATUS,
|
|
|
|
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
|
2010-07-13 06:01:42 +02:00
|
|
|
|
2012-02-20 00:34:01 +01:00
|
|
|
/*
|
|
|
|
* If we don't specify the name, the bus will be addressed as <id>.0, where
|
|
|
|
* id is the device id.
|
|
|
|
* Since PCI Bridge devices have a single bus each, we don't need the index:
|
|
|
|
* let users address the bus using the device name.
|
|
|
|
*/
|
|
|
|
if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
|
2018-12-13 23:37:37 +01:00
|
|
|
br->bus_name = dev->qdev.id;
|
2012-02-20 00:34:01 +01:00
|
|
|
}
|
|
|
|
|
2021-09-23 14:11:51 +02:00
|
|
|
qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
|
|
|
|
br->bus_name);
|
2010-07-13 06:01:42 +02:00
|
|
|
sec_bus->parent_dev = dev;
|
2013-03-08 00:16:54 +01:00
|
|
|
sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
|
2011-09-06 19:58:22 +02:00
|
|
|
sec_bus->address_space_mem = &br->address_space_mem;
|
2013-11-06 19:23:26 +01:00
|
|
|
memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
|
2011-09-06 19:58:22 +02:00
|
|
|
sec_bus->address_space_io = &br->address_space_io;
|
2017-09-22 14:18:31 +02:00
|
|
|
memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
|
hw/pci/pci_bridge: Correct pci_bridge_io memory region size
memory_region_set_size() handle the 16 Exabytes limit by
special-casing the UINT64_MAX value. This is not a problem
for the 32-bit maximum, 4 GiB.
By using the UINT32_MAX value, the pci_bridge_io MemoryRegion
ends up missing 1 byte:
(qemu) info mtree
memory-region: pci_bridge_io
0000000000000000-00000000fffffffe (prio 0, i/o): pci_bridge_io
0000000000000060-0000000000000060 (prio 0, i/o): i8042-data
0000000000000064-0000000000000064 (prio 0, i/o): i8042-cmd
00000000000001ce-00000000000001d1 (prio 0, i/o): vbe
0000000000000378-000000000000037f (prio 0, i/o): parallel
00000000000003b4-00000000000003b5 (prio 0, i/o): vga
...
Fix by using the correct value. We now have:
memory-region: pci_bridge_io
0000000000000000-00000000ffffffff (prio 0, i/o): pci_bridge_io
0000000000000060-0000000000000060 (prio 0, i/o): i8042-data
0000000000000064-0000000000000064 (prio 0, i/o): i8042-cmd
...
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200601142930.29408-4-f4bug@amsat.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-01 16:29:25 +02:00
|
|
|
4 * GiB);
|
2012-10-25 12:37:57 +02:00
|
|
|
br->windows = pci_bridge_region_init(br);
|
2010-07-13 06:01:42 +02:00
|
|
|
QLIST_INIT(&sec_bus->child);
|
|
|
|
QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
|
2010-07-13 06:01:39 +02:00
|
|
|
}
|
|
|
|
|
2010-07-13 06:01:42 +02:00
|
|
|
/* default qdev clean up function for PCI-to-PCI bridge */
|
2012-07-04 06:39:27 +02:00
|
|
|
void pci_bridge_exitfn(PCIDevice *pci_dev)
|
2010-07-13 06:01:39 +02:00
|
|
|
{
|
2013-07-11 17:13:43 +02:00
|
|
|
PCIBridge *s = PCI_BRIDGE(pci_dev);
|
2010-07-13 06:01:41 +02:00
|
|
|
assert(QLIST_EMPTY(&s->sec_bus.child));
|
|
|
|
QLIST_REMOVE(&s->sec_bus, sibling);
|
2012-10-25 12:37:57 +02:00
|
|
|
pci_bridge_region_del(s, s->windows);
|
|
|
|
pci_bridge_region_cleanup(s, s->windows);
|
2013-12-18 17:15:51 +01:00
|
|
|
/* object_unparent() is called automatically during device deletion */
|
2010-07-13 06:01:39 +02:00
|
|
|
}
|
|
|
|
|
2010-07-13 06:01:42 +02:00
|
|
|
/*
|
|
|
|
* before qdev initialization(qdev_init()), this function sets bus_name and
|
2018-10-11 10:25:08 +02:00
|
|
|
* map_irq callback which are necessary for pci_bridge_initfn() to
|
2010-07-13 06:01:42 +02:00
|
|
|
* initialize bus.
|
|
|
|
*/
|
|
|
|
void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
|
|
|
|
pci_map_irq_fn map_irq)
|
2010-07-13 06:01:39 +02:00
|
|
|
{
|
2010-07-13 06:01:42 +02:00
|
|
|
br->map_irq = map_irq;
|
|
|
|
br->bus_name = bus_name;
|
2010-07-13 06:01:39 +02:00
|
|
|
}
|
2013-07-11 17:13:43 +02:00
|
|
|
|
2017-08-18 01:36:48 +02:00
|
|
|
|
|
|
|
int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
|
2018-08-21 05:18:06 +02:00
|
|
|
PCIResReserve res_reserve, Error **errp)
|
2017-08-18 01:36:48 +02:00
|
|
|
{
|
2018-08-21 05:18:06 +02:00
|
|
|
if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
|
|
|
|
res_reserve.mem_pref_64 != (uint64_t)-1) {
|
2017-08-18 01:36:48 +02:00
|
|
|
error_setg(errp,
|
|
|
|
"PCI resource reserve cap: PREF32 and PREF64 conflict");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2018-08-21 05:18:06 +02:00
|
|
|
if (res_reserve.mem_non_pref != (uint64_t)-1 &&
|
2020-06-01 16:29:26 +02:00
|
|
|
res_reserve.mem_non_pref >= 4 * GiB) {
|
2018-01-17 20:19:47 +01:00
|
|
|
error_setg(errp,
|
|
|
|
"PCI resource reserve cap: mem-reserve must be less than 4G");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2018-08-21 05:18:06 +02:00
|
|
|
if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
|
2020-06-01 16:29:26 +02:00
|
|
|
res_reserve.mem_pref_32 >= 4 * GiB) {
|
2018-01-17 20:19:47 +01:00
|
|
|
error_setg(errp,
|
|
|
|
"PCI resource reserve cap: pref32-reserve must be less than 4G");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2018-08-21 05:18:06 +02:00
|
|
|
if (res_reserve.bus == (uint32_t)-1 &&
|
|
|
|
res_reserve.io == (uint64_t)-1 &&
|
|
|
|
res_reserve.mem_non_pref == (uint64_t)-1 &&
|
|
|
|
res_reserve.mem_pref_32 == (uint64_t)-1 &&
|
|
|
|
res_reserve.mem_pref_64 == (uint64_t)-1) {
|
2017-08-18 01:36:48 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
size_t cap_len = sizeof(PCIBridgeQemuCap);
|
|
|
|
PCIBridgeQemuCap cap = {
|
|
|
|
.len = cap_len,
|
|
|
|
.type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
|
2021-10-20 11:48:54 +02:00
|
|
|
.bus_res = cpu_to_le32(res_reserve.bus),
|
|
|
|
.io = cpu_to_le64(res_reserve.io),
|
|
|
|
.mem = cpu_to_le32(res_reserve.mem_non_pref),
|
|
|
|
.mem_pref_32 = cpu_to_le32(res_reserve.mem_pref_32),
|
|
|
|
.mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64)
|
2017-08-18 01:36:48 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
|
|
|
|
cap_offset, cap_len, errp);
|
|
|
|
if (offset < 0) {
|
|
|
|
return offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(dev->config + offset + PCI_CAP_FLAGS,
|
|
|
|
(char *)&cap + PCI_CAP_FLAGS,
|
|
|
|
cap_len - PCI_CAP_FLAGS);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-07-11 17:13:43 +02:00
|
|
|
static const TypeInfo pci_bridge_type_info = {
|
|
|
|
.name = TYPE_PCI_BRIDGE,
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(PCIBridge),
|
|
|
|
.abstract = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void pci_bridge_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&pci_bridge_type_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(pci_bridge_register_types)
|