459 lines
14 KiB
C
459 lines
14 KiB
C
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/*
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* Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c
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*
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* Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
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* All rights reserved.
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*
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* Evgeny Voevodin <e.voevodin@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sysbus.h"
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#include "qemu-common.h"
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#include "irq.h"
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#include "exynos4210.h"
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enum ExtGicId {
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EXT_GIC_ID_MDMA_LCD0 = 66,
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EXT_GIC_ID_PDMA0,
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EXT_GIC_ID_PDMA1,
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EXT_GIC_ID_TIMER0,
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EXT_GIC_ID_TIMER1,
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EXT_GIC_ID_TIMER2,
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EXT_GIC_ID_TIMER3,
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EXT_GIC_ID_TIMER4,
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EXT_GIC_ID_MCT_L0,
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EXT_GIC_ID_WDT,
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EXT_GIC_ID_RTC_ALARM,
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EXT_GIC_ID_RTC_TIC,
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EXT_GIC_ID_GPIO_XB,
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EXT_GIC_ID_GPIO_XA,
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EXT_GIC_ID_MCT_L1,
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EXT_GIC_ID_IEM_APC,
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EXT_GIC_ID_IEM_IEC,
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EXT_GIC_ID_NFC,
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EXT_GIC_ID_UART0,
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EXT_GIC_ID_UART1,
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EXT_GIC_ID_UART2,
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EXT_GIC_ID_UART3,
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EXT_GIC_ID_UART4,
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EXT_GIC_ID_MCT_G0,
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EXT_GIC_ID_I2C0,
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EXT_GIC_ID_I2C1,
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EXT_GIC_ID_I2C2,
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EXT_GIC_ID_I2C3,
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EXT_GIC_ID_I2C4,
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EXT_GIC_ID_I2C5,
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EXT_GIC_ID_I2C6,
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EXT_GIC_ID_I2C7,
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EXT_GIC_ID_SPI0,
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EXT_GIC_ID_SPI1,
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EXT_GIC_ID_SPI2,
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EXT_GIC_ID_MCT_G1,
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EXT_GIC_ID_USB_HOST,
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EXT_GIC_ID_USB_DEVICE,
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EXT_GIC_ID_MODEMIF,
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EXT_GIC_ID_HSMMC0,
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EXT_GIC_ID_HSMMC1,
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EXT_GIC_ID_HSMMC2,
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EXT_GIC_ID_HSMMC3,
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EXT_GIC_ID_SDMMC,
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EXT_GIC_ID_MIPI_CSI_4LANE,
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EXT_GIC_ID_MIPI_DSI_4LANE,
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EXT_GIC_ID_MIPI_CSI_2LANE,
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EXT_GIC_ID_MIPI_DSI_2LANE,
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EXT_GIC_ID_ONENAND_AUDI,
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EXT_GIC_ID_ROTATOR,
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EXT_GIC_ID_FIMC0,
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EXT_GIC_ID_FIMC1,
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EXT_GIC_ID_FIMC2,
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EXT_GIC_ID_FIMC3,
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EXT_GIC_ID_JPEG,
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EXT_GIC_ID_2D,
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EXT_GIC_ID_PCIe,
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EXT_GIC_ID_MIXER,
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EXT_GIC_ID_HDMI,
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EXT_GIC_ID_HDMI_I2C,
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EXT_GIC_ID_MFC,
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EXT_GIC_ID_TVENC,
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};
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enum ExtInt {
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EXT_GIC_ID_EXTINT0 = 48,
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EXT_GIC_ID_EXTINT1,
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EXT_GIC_ID_EXTINT2,
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EXT_GIC_ID_EXTINT3,
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EXT_GIC_ID_EXTINT4,
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EXT_GIC_ID_EXTINT5,
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EXT_GIC_ID_EXTINT6,
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EXT_GIC_ID_EXTINT7,
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EXT_GIC_ID_EXTINT8,
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EXT_GIC_ID_EXTINT9,
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EXT_GIC_ID_EXTINT10,
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EXT_GIC_ID_EXTINT11,
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EXT_GIC_ID_EXTINT12,
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EXT_GIC_ID_EXTINT13,
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EXT_GIC_ID_EXTINT14,
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EXT_GIC_ID_EXTINT15
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};
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/*
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* External GIC sources which are not from External Interrupt Combiner or
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* External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ,
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* which is INTG16 in Internal Interrupt Combiner.
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*/
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static uint32_t
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combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
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/* int combiner groups 16-19 */
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{ }, { }, { }, { },
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/* int combiner group 20 */
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{ 0, EXT_GIC_ID_MDMA_LCD0 },
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/* int combiner group 21 */
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{ EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 },
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/* int combiner group 22 */
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{ EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2,
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EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 },
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/* int combiner group 23 */
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{ EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC },
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/* int combiner group 24 */
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{ EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA },
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/* int combiner group 25 */
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{ EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC },
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/* int combiner group 26 */
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{ EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UART3,
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EXT_GIC_ID_UART4 },
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/* int combiner group 27 */
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{ EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3,
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EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6,
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EXT_GIC_ID_I2C7 },
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/* int combiner group 28 */
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{ EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 },
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/* int combiner group 29 */
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{ EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2,
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EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC },
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/* int combiner group 30 */
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{ EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE },
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/* int combiner group 31 */
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{ EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE },
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/* int combiner group 32 */
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{ EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 },
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/* int combiner group 33 */
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{ EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 },
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/* int combiner group 34 */
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{ EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC },
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/* int combiner group 35 */
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{ 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
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/* int combiner group 36 */
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{ EXT_GIC_ID_MIXER },
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/* int combiner group 37 */
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{ EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6,
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EXT_GIC_ID_EXTINT7 },
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/* groups 38-50 */
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{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { },
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/* int combiner group 51 */
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{ EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
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/* group 52 */
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{ },
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/* int combiner group 53 */
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{ EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 },
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/* groups 54-63 */
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{ }, { }, { }, { }, { }, { }, { }, { }, { }, { }
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};
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#define EXYNOS4210_GIC_NIRQ 160
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#define NCPU EXYNOS4210_NCPUS
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#define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000
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#define EXYNOS4210_EXT_GIC_DIST_REGION_SIZE 0x10000
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#define EXYNOS4210_EXT_GIC_PER_CPU_OFFSET 0x8000
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#define EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(n) \
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((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)
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#define EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(n) \
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((n) * EXYNOS4210_EXT_GIC_PER_CPU_OFFSET)
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#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
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#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
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static void exynos4210_irq_handler(void *opaque, int irq, int level)
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{
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Exynos4210Irq *s = (Exynos4210Irq *)opaque;
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/* Bypass */
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qemu_set_irq(s->board_irqs[irq], level);
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return;
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}
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/*
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* Initialize exynos4210 IRQ subsystem stub.
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*/
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qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
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{
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return qemu_allocate_irqs(exynos4210_irq_handler, s,
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EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
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}
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/*
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* Initialize board IRQs.
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* These IRQs contain splitted Int/External Combiner and External Gic IRQs.
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*/
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void exynos4210_init_board_irqs(Exynos4210Irq *s)
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{
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uint32_t grp, bit, irq_id, n;
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for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
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s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
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s->ext_combiner_irq[n]);
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irq_id = 0;
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if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) ||
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n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) {
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/* MCT_G0 is passed to External GIC */
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irq_id = EXT_GIC_ID_MCT_G0;
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}
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if (n == EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) ||
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n == EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) {
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/* MCT_G1 is passed to External and GIC */
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irq_id = EXT_GIC_ID_MCT_G1;
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}
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if (irq_id) {
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s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
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s->ext_gic_irq[irq_id-32]);
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}
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}
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for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
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/* these IDs are passed to Internal Combiner and External GIC */
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grp = EXYNOS4210_COMBINER_GET_GRP_NUM(n);
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bit = EXYNOS4210_COMBINER_GET_BIT_NUM(n);
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irq_id = combiner_grp_to_gic_id[grp -
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EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
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if (irq_id) {
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s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n],
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s->ext_gic_irq[irq_id-32]);
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}
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}
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}
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/*
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* Get IRQ number from exynos4210 IRQ subsystem stub.
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* To identify IRQ source use internal combiner group and bit number
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* grp - group number
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* bit - bit number inside group
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*/
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uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
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{
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return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit);
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}
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/********* GIC part *********/
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static inline int
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gic_get_current_cpu(void)
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{
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return cpu_single_env->cpu_index;
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}
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#include "arm_gic.c"
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typedef struct {
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gic_state gic;
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MemoryRegion cpu_container;
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MemoryRegion dist_container;
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MemoryRegion cpu_alias[NCPU];
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MemoryRegion dist_alias[NCPU];
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uint32_t num_cpu;
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} Exynos4210GicState;
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static int exynos4210_gic_init(SysBusDevice *dev)
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{
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Exynos4210GicState *s = FROM_SYSBUSGIC(Exynos4210GicState, dev);
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uint32_t i;
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const char cpu_prefix[] = "exynos4210-gic-alias_cpu";
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const char dist_prefix[] = "exynos4210-gic-alias_dist";
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char cpu_alias_name[sizeof(cpu_prefix) + 3];
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char dist_alias_name[sizeof(cpu_prefix) + 3];
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gic_init(&s->gic, s->num_cpu, EXYNOS4210_GIC_NIRQ);
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memory_region_init(&s->cpu_container, "exynos4210-cpu-container",
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EXYNOS4210_EXT_GIC_CPU_REGION_SIZE);
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memory_region_init(&s->dist_container, "exynos4210-dist-container",
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EXYNOS4210_EXT_GIC_DIST_REGION_SIZE);
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for (i = 0; i < s->num_cpu; i++) {
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/* Map CPU interface per SMP Core */
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sprintf(cpu_alias_name, "%s%x", cpu_prefix, i);
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memory_region_init_alias(&s->cpu_alias[i],
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cpu_alias_name,
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&s->gic.cpuiomem[0],
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0,
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EXYNOS4210_GIC_CPU_REGION_SIZE);
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memory_region_add_subregion(&s->cpu_container,
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EXYNOS4210_EXT_GIC_CPU_GET_OFFSET(i), &s->cpu_alias[i]);
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/* Map Distributor per SMP Core */
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sprintf(dist_alias_name, "%s%x", dist_prefix, i);
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memory_region_init_alias(&s->dist_alias[i],
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dist_alias_name,
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&s->gic.iomem,
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|
0,
|
||
|
|
EXYNOS4210_GIC_DIST_REGION_SIZE);
|
||
|
|
memory_region_add_subregion(&s->dist_container,
|
||
|
|
EXYNOS4210_EXT_GIC_DIST_GET_OFFSET(i), &s->dist_alias[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
sysbus_init_mmio(dev, &s->cpu_container);
|
||
|
|
sysbus_init_mmio(dev, &s->dist_container);
|
||
|
|
|
||
|
|
gic_cpu_write(&s->gic, 1, 0, 1);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static Property exynos4210_gic_properties[] = {
|
||
|
|
DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1),
|
||
|
|
DEFINE_PROP_END_OF_LIST(),
|
||
|
|
};
|
||
|
|
|
||
|
|
static void exynos4210_gic_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
k->init = exynos4210_gic_init;
|
||
|
|
dc->props = exynos4210_gic_properties;
|
||
|
|
}
|
||
|
|
|
||
|
|
static TypeInfo exynos4210_gic_info = {
|
||
|
|
.name = "exynos4210.gic",
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(Exynos4210GicState),
|
||
|
|
.class_init = exynos4210_gic_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void exynos4210_gic_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&exynos4210_gic_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(exynos4210_gic_register_types)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* IRQGate struct.
|
||
|
|
* IRQ Gate represents OR gate between GICs to pass IRQ to PIC.
|
||
|
|
*/
|
||
|
|
typedef struct {
|
||
|
|
SysBusDevice busdev;
|
||
|
|
|
||
|
|
qemu_irq pic_irq[NCPU]; /* output IRQs to PICs */
|
||
|
|
uint32_t gpio_level[EXYNOS4210_IRQ_GATE_NINPUTS]; /* Input levels */
|
||
|
|
} Exynos4210IRQGateState;
|
||
|
|
|
||
|
|
static const VMStateDescription vmstate_exynos4210_irq_gate = {
|
||
|
|
.name = "exynos4210.irq_gate",
|
||
|
|
.version_id = 1,
|
||
|
|
.minimum_version_id = 1,
|
||
|
|
.minimum_version_id_old = 1,
|
||
|
|
.fields = (VMStateField[]) {
|
||
|
|
VMSTATE_UINT32_ARRAY(gpio_level, Exynos4210IRQGateState,
|
||
|
|
EXYNOS4210_IRQ_GATE_NINPUTS),
|
||
|
|
VMSTATE_END_OF_LIST()
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Process a change in an external IRQ input. */
|
||
|
|
static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
|
||
|
|
{
|
||
|
|
Exynos4210IRQGateState *s =
|
||
|
|
(Exynos4210IRQGateState *)opaque;
|
||
|
|
uint32_t odd, even;
|
||
|
|
|
||
|
|
if (irq & 1) {
|
||
|
|
odd = irq;
|
||
|
|
even = irq & ~1;
|
||
|
|
} else {
|
||
|
|
even = irq;
|
||
|
|
odd = irq | 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
assert(irq < EXYNOS4210_IRQ_GATE_NINPUTS);
|
||
|
|
s->gpio_level[irq] = level;
|
||
|
|
|
||
|
|
if (s->gpio_level[odd] >= 1 || s->gpio_level[even] >= 1) {
|
||
|
|
qemu_irq_raise(s->pic_irq[even >> 1]);
|
||
|
|
} else {
|
||
|
|
qemu_irq_lower(s->pic_irq[even >> 1]);
|
||
|
|
}
|
||
|
|
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void exynos4210_irq_gate_reset(DeviceState *d)
|
||
|
|
{
|
||
|
|
Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)d;
|
||
|
|
|
||
|
|
memset(&s->gpio_level, 0, sizeof(s->gpio_level));
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* IRQ Gate initialization.
|
||
|
|
*/
|
||
|
|
static int exynos4210_irq_gate_init(SysBusDevice *dev)
|
||
|
|
{
|
||
|
|
unsigned int i;
|
||
|
|
Exynos4210IRQGateState *s =
|
||
|
|
FROM_SYSBUS(Exynos4210IRQGateState, dev);
|
||
|
|
|
||
|
|
/* Allocate general purpose input signals and connect a handler to each of
|
||
|
|
* them */
|
||
|
|
qdev_init_gpio_in(&s->busdev.qdev, exynos4210_irq_gate_handler,
|
||
|
|
EXYNOS4210_IRQ_GATE_NINPUTS);
|
||
|
|
|
||
|
|
/* Connect SysBusDev irqs to device specific irqs */
|
||
|
|
for (i = 0; i < NCPU; i++) {
|
||
|
|
sysbus_init_irq(dev, &s->pic_irq[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
k->init = exynos4210_irq_gate_init;
|
||
|
|
dc->reset = exynos4210_irq_gate_reset;
|
||
|
|
dc->vmsd = &vmstate_exynos4210_irq_gate;
|
||
|
|
}
|
||
|
|
|
||
|
|
static TypeInfo exynos4210_irq_gate_info = {
|
||
|
|
.name = "exynos4210.irq_gate",
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(Exynos4210IRQGateState),
|
||
|
|
.class_init = exynos4210_irq_gate_class_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void exynos4210_irq_gate_register_types(void)
|
||
|
|
{
|
||
|
|
type_register_static(&exynos4210_irq_gate_info);
|
||
|
|
}
|
||
|
|
|
||
|
|
type_init(exynos4210_irq_gate_register_types)
|