2013-01-11 18:25:29 +01:00
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/*
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* QEMU TEWS TPCI200 IndustryPack carrier emulation
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*
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* Copyright (C) 2012 Igalia, S.L.
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* Author: Alberto Garcia <agarcia@igalia.com>
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*
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* This code is licensed under the GNU GPL v2 or (at your option) any
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* later version.
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*/
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2013-03-18 17:36:02 +01:00
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#include "ipack.h"
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci.h"
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2013-01-11 18:25:29 +01:00
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#include "qemu/bitops.h"
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#include <stdio.h>
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/* #define DEBUG_TPCI */
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#ifdef DEBUG_TPCI
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, "TPCI200: " fmt, ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do { } while (0)
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#endif
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#define N_MODULES 4
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#define IP_ID_SPACE 2
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#define IP_INT_SPACE 3
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#define IP_IO_SPACE_ADDR_MASK 0x7F
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#define IP_ID_SPACE_ADDR_MASK 0x3F
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#define IP_INT_SPACE_ADDR_MASK 0x3F
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#define STATUS_INT(IP, INTNO) BIT((IP) * 2 + (INTNO))
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2013-01-21 07:49:51 +01:00
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#define STATUS_TIME(IP) BIT((IP) + 12)
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2013-01-11 18:25:29 +01:00
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#define STATUS_ERR_ANY 0xF00
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#define CTRL_CLKRATE BIT(0)
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#define CTRL_RECOVER BIT(1)
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#define CTRL_TIME_INT BIT(2)
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#define CTRL_ERR_INT BIT(3)
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#define CTRL_INT_EDGE(INTNO) BIT(4 + (INTNO))
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#define CTRL_INT(INTNO) BIT(6 + (INTNO))
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#define REG_REV_ID 0x00
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#define REG_IP_A_CTRL 0x02
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#define REG_IP_B_CTRL 0x04
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#define REG_IP_C_CTRL 0x06
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#define REG_IP_D_CTRL 0x08
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#define REG_RESET 0x0A
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#define REG_STATUS 0x0C
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#define IP_N_FROM_REG(REG) ((REG) / 2 - 1)
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typedef struct {
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PCIDevice dev;
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IPackBus bus;
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MemoryRegion mmio;
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MemoryRegion io;
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MemoryRegion las0;
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MemoryRegion las1;
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MemoryRegion las2;
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MemoryRegion las3;
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bool big_endian[3];
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uint8_t ctrl[N_MODULES];
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uint16_t status;
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uint8_t int_set;
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} TPCI200State;
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#define TYPE_TPCI200 "tpci200"
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#define TPCI200(obj) \
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OBJECT_CHECK(TPCI200State, (obj), TYPE_TPCI200)
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static const uint8_t local_config_regs[] = {
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0x00, 0xFF, 0xFF, 0x0F, 0x00, 0xFC, 0xFF, 0x0F, 0x00, 0x00, 0x00,
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0x0E, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
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0x00, 0x08, 0x01, 0x00, 0x00, 0x04, 0x01, 0x00, 0x00, 0x00, 0x01,
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0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0xA0, 0x60, 0x41, 0xD4,
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0xA2, 0x20, 0x41, 0x14, 0xA2, 0x20, 0x41, 0x14, 0xA2, 0x20, 0x01,
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0x14, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x08, 0x01, 0x02,
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0x00, 0x04, 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02, 0x41,
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0x00, 0x00, 0x00, 0x00, 0x40, 0x7A, 0x00, 0x52, 0x92, 0x24, 0x02
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};
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static void adjust_addr(bool big_endian, hwaddr *addr, unsigned size)
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{
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/* During 8 bit access in big endian mode,
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odd and even addresses are swapped */
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if (big_endian && size == 1) {
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*addr ^= 1;
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}
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}
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static uint64_t adjust_value(bool big_endian, uint64_t *val, unsigned size)
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{
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/* Local spaces only support 8/16 bit access,
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* so there's no need to care for sizes > 2 */
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if (big_endian && size == 2) {
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*val = bswap16(*val);
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}
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return *val;
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}
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static void tpci200_set_irq(void *opaque, int intno, int level)
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{
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IPackDevice *ip = opaque;
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IPackBus *bus = IPACK_BUS(qdev_get_parent_bus(DEVICE(ip)));
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PCIDevice *pcidev = PCI_DEVICE(BUS(bus)->parent);
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TPCI200State *dev = TPCI200(pcidev);
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unsigned ip_n = ip->slot;
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uint16_t prev_status = dev->status;
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assert(ip->slot >= 0 && ip->slot < N_MODULES);
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/* The requested interrupt must be enabled in the IP CONTROL
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* register */
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if (!(dev->ctrl[ip_n] & CTRL_INT(intno))) {
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return;
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}
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/* Update the interrupt status in the IP STATUS register */
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if (level) {
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dev->status |= STATUS_INT(ip_n, intno);
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} else {
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dev->status &= ~STATUS_INT(ip_n, intno);
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}
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/* Return if there are no changes */
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if (dev->status == prev_status) {
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return;
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}
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DPRINTF("IP %u INT%u#: %u\n", ip_n, intno, level);
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/* Check if the interrupt is edge sensitive */
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if (dev->ctrl[ip_n] & CTRL_INT_EDGE(intno)) {
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if (level) {
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qemu_set_irq(dev->dev.irq[0], !dev->int_set);
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qemu_set_irq(dev->dev.irq[0], dev->int_set);
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}
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} else {
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unsigned i, j;
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uint16_t level_status = dev->status;
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/* Check if there are any level sensitive interrupts set by
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removing the ones that are edge sensitive from the status
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register */
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for (i = 0; i < N_MODULES; i++) {
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for (j = 0; j < 2; j++) {
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if (dev->ctrl[i] & CTRL_INT_EDGE(j)) {
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level_status &= ~STATUS_INT(i, j);
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}
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}
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}
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if (level_status && !dev->int_set) {
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qemu_irq_raise(dev->dev.irq[0]);
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dev->int_set = 1;
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} else if (!level_status && dev->int_set) {
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qemu_irq_lower(dev->dev.irq[0]);
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dev->int_set = 0;
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}
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}
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}
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static uint64_t tpci200_read_cfg(void *opaque, hwaddr addr, unsigned size)
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{
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TPCI200State *s = opaque;
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uint8_t ret = 0;
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if (addr < ARRAY_SIZE(local_config_regs)) {
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ret = local_config_regs[addr];
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}
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/* Endianness is stored in the first bit of these registers */
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if ((addr == 0x2b && s->big_endian[0]) ||
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(addr == 0x2f && s->big_endian[1]) ||
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(addr == 0x33 && s->big_endian[2])) {
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ret |= 1;
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}
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DPRINTF("Read from LCR 0x%x: 0x%x\n", (unsigned) addr, (unsigned) ret);
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return ret;
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}
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static void tpci200_write_cfg(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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TPCI200State *s = opaque;
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/* Endianness is stored in the first bit of these registers */
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if (addr == 0x2b || addr == 0x2f || addr == 0x33) {
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unsigned las = (addr - 0x2b) / 4;
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s->big_endian[las] = val & 1;
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DPRINTF("LAS%u big endian mode: %u\n", las, (unsigned) val & 1);
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} else {
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DPRINTF("Write to LCR 0x%x: 0x%x\n", (unsigned) addr, (unsigned) val);
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}
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}
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static uint64_t tpci200_read_las0(void *opaque, hwaddr addr, unsigned size)
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{
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TPCI200State *s = opaque;
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uint64_t ret = 0;
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switch (addr) {
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case REG_REV_ID:
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DPRINTF("Read REVISION ID\n"); /* Current value is 0x00 */
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break;
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case REG_IP_A_CTRL:
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case REG_IP_B_CTRL:
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case REG_IP_C_CTRL:
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case REG_IP_D_CTRL:
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{
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unsigned ip_n = IP_N_FROM_REG(addr);
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ret = s->ctrl[ip_n];
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DPRINTF("Read IP %c CONTROL: 0x%x\n", 'A' + ip_n, (unsigned) ret);
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}
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break;
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case REG_RESET:
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DPRINTF("Read RESET\n"); /* Not implemented */
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break;
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case REG_STATUS:
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ret = s->status;
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DPRINTF("Read STATUS: 0x%x\n", (unsigned) ret);
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break;
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/* Reserved */
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default:
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DPRINTF("Unsupported read from LAS0 0x%x\n", (unsigned) addr);
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break;
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}
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return adjust_value(s->big_endian[0], &ret, size);
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}
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static void tpci200_write_las0(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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TPCI200State *s = opaque;
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adjust_value(s->big_endian[0], &val, size);
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switch (addr) {
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case REG_REV_ID:
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DPRINTF("Write Revision ID: 0x%x\n", (unsigned) val); /* No effect */
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break;
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case REG_IP_A_CTRL:
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case REG_IP_B_CTRL:
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case REG_IP_C_CTRL:
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case REG_IP_D_CTRL:
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{
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unsigned ip_n = IP_N_FROM_REG(addr);
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s->ctrl[ip_n] = val;
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DPRINTF("Write IP %c CONTROL: 0x%x\n", 'A' + ip_n, (unsigned) val);
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}
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break;
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case REG_RESET:
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DPRINTF("Write RESET: 0x%x\n", (unsigned) val); /* Not implemented */
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break;
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case REG_STATUS:
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{
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unsigned i;
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for (i = 0; i < N_MODULES; i++) {
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IPackDevice *ip = ipack_device_find(&s->bus, i);
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if (ip != NULL) {
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if (val & STATUS_INT(i, 0)) {
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DPRINTF("Clear IP %c INT0# status\n", 'A' + i);
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qemu_irq_lower(ip->irq[0]);
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}
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if (val & STATUS_INT(i, 1)) {
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DPRINTF("Clear IP %c INT1# status\n", 'A' + i);
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qemu_irq_lower(ip->irq[1]);
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}
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}
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2013-01-21 07:49:51 +01:00
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if (val & STATUS_TIME(i)) {
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2013-01-11 18:25:29 +01:00
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DPRINTF("Clear IP %c timeout\n", 'A' + i);
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2013-01-21 07:49:51 +01:00
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s->status &= ~STATUS_TIME(i);
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2013-01-11 18:25:29 +01:00
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}
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}
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if (val & STATUS_ERR_ANY) {
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DPRINTF("Unexpected write to STATUS register: 0x%x\n",
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(unsigned) val);
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}
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}
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break;
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/* Reserved */
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default:
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DPRINTF("Unsupported write to LAS0 0x%x: 0x%x\n",
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(unsigned) addr, (unsigned) val);
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break;
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}
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}
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static uint64_t tpci200_read_las1(void *opaque, hwaddr addr, unsigned size)
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{
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TPCI200State *s = opaque;
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IPackDevice *ip;
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uint64_t ret = 0;
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unsigned ip_n, space;
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uint8_t offset;
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adjust_addr(s->big_endian[1], &addr, size);
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/*
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* The address is divided into the IP module number (0-4), the IP
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* address space (I/O, ID, INT) and the offset within that space.
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*/
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ip_n = addr >> 8;
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space = (addr >> 6) & 3;
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ip = ipack_device_find(&s->bus, ip_n);
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if (ip == NULL) {
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DPRINTF("Read LAS1: IP module %u not installed\n", ip_n);
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} else {
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IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
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switch (space) {
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case IP_ID_SPACE:
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offset = addr & IP_ID_SPACE_ADDR_MASK;
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if (k->id_read) {
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ret = k->id_read(ip, offset);
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}
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break;
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case IP_INT_SPACE:
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offset = addr & IP_INT_SPACE_ADDR_MASK;
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/* Read address 0 to ACK IP INT0# and address 2 to ACK IP INT1# */
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if (offset == 0 || offset == 2) {
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unsigned intno = offset / 2;
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bool int_set = s->status & STATUS_INT(ip_n, intno);
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bool int_edge_sensitive = s->ctrl[ip_n] & CTRL_INT_EDGE(intno);
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if (int_set && !int_edge_sensitive) {
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qemu_irq_lower(ip->irq[intno]);
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}
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}
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if (k->int_read) {
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ret = k->int_read(ip, offset);
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}
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break;
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default:
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|
offset = addr & IP_IO_SPACE_ADDR_MASK;
|
|
|
|
if (k->io_read) {
|
|
|
|
ret = k->io_read(ip, offset);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return adjust_value(s->big_endian[1], &ret, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tpci200_write_las1(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
TPCI200State *s = opaque;
|
|
|
|
IPackDevice *ip;
|
|
|
|
unsigned ip_n, space;
|
|
|
|
uint8_t offset;
|
|
|
|
|
|
|
|
adjust_addr(s->big_endian[1], &addr, size);
|
|
|
|
adjust_value(s->big_endian[1], &val, size);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The address is divided into the IP module number, the IP
|
|
|
|
* address space (I/O, ID, INT) and the offset within that space.
|
|
|
|
*/
|
|
|
|
ip_n = addr >> 8;
|
|
|
|
space = (addr >> 6) & 3;
|
|
|
|
ip = ipack_device_find(&s->bus, ip_n);
|
|
|
|
|
|
|
|
if (ip == NULL) {
|
|
|
|
DPRINTF("Write LAS1: IP module %u not installed\n", ip_n);
|
|
|
|
} else {
|
|
|
|
IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
|
|
|
|
switch (space) {
|
|
|
|
|
|
|
|
case IP_ID_SPACE:
|
|
|
|
offset = addr & IP_ID_SPACE_ADDR_MASK;
|
|
|
|
if (k->id_write) {
|
|
|
|
k->id_write(ip, offset, val);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case IP_INT_SPACE:
|
|
|
|
offset = addr & IP_INT_SPACE_ADDR_MASK;
|
|
|
|
if (k->int_write) {
|
|
|
|
k->int_write(ip, offset, val);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
offset = addr & IP_IO_SPACE_ADDR_MASK;
|
|
|
|
if (k->io_write) {
|
|
|
|
k->io_write(ip, offset, val);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t tpci200_read_las2(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
TPCI200State *s = opaque;
|
|
|
|
IPackDevice *ip;
|
|
|
|
uint64_t ret = 0;
|
|
|
|
unsigned ip_n;
|
|
|
|
uint32_t offset;
|
|
|
|
|
|
|
|
adjust_addr(s->big_endian[2], &addr, size);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The address is divided into the IP module number and the offset
|
|
|
|
* within the IP module MEM space.
|
|
|
|
*/
|
|
|
|
ip_n = addr >> 23;
|
|
|
|
offset = addr & 0x7fffff;
|
|
|
|
ip = ipack_device_find(&s->bus, ip_n);
|
|
|
|
|
|
|
|
if (ip == NULL) {
|
|
|
|
DPRINTF("Read LAS2: IP module %u not installed\n", ip_n);
|
|
|
|
} else {
|
|
|
|
IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
|
|
|
|
if (k->mem_read16) {
|
|
|
|
ret = k->mem_read16(ip, offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return adjust_value(s->big_endian[2], &ret, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tpci200_write_las2(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
TPCI200State *s = opaque;
|
|
|
|
IPackDevice *ip;
|
|
|
|
unsigned ip_n;
|
|
|
|
uint32_t offset;
|
|
|
|
|
|
|
|
adjust_addr(s->big_endian[2], &addr, size);
|
|
|
|
adjust_value(s->big_endian[2], &val, size);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The address is divided into the IP module number and the offset
|
|
|
|
* within the IP module MEM space.
|
|
|
|
*/
|
|
|
|
ip_n = addr >> 23;
|
|
|
|
offset = addr & 0x7fffff;
|
|
|
|
ip = ipack_device_find(&s->bus, ip_n);
|
|
|
|
|
|
|
|
if (ip == NULL) {
|
|
|
|
DPRINTF("Write LAS2: IP module %u not installed\n", ip_n);
|
|
|
|
} else {
|
|
|
|
IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
|
|
|
|
if (k->mem_write16) {
|
|
|
|
k->mem_write16(ip, offset, val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t tpci200_read_las3(void *opaque, hwaddr addr, unsigned size)
|
|
|
|
{
|
|
|
|
TPCI200State *s = opaque;
|
|
|
|
IPackDevice *ip;
|
|
|
|
uint64_t ret = 0;
|
|
|
|
/*
|
|
|
|
* The address is divided into the IP module number and the offset
|
|
|
|
* within the IP module MEM space.
|
|
|
|
*/
|
|
|
|
unsigned ip_n = addr >> 22;
|
|
|
|
uint32_t offset = addr & 0x3fffff;
|
|
|
|
|
|
|
|
ip = ipack_device_find(&s->bus, ip_n);
|
|
|
|
|
|
|
|
if (ip == NULL) {
|
|
|
|
DPRINTF("Read LAS3: IP module %u not installed\n", ip_n);
|
|
|
|
} else {
|
|
|
|
IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
|
|
|
|
if (k->mem_read8) {
|
|
|
|
ret = k->mem_read8(ip, offset);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tpci200_write_las3(void *opaque, hwaddr addr, uint64_t val,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
TPCI200State *s = opaque;
|
|
|
|
IPackDevice *ip;
|
|
|
|
/*
|
|
|
|
* The address is divided into the IP module number and the offset
|
|
|
|
* within the IP module MEM space.
|
|
|
|
*/
|
|
|
|
unsigned ip_n = addr >> 22;
|
|
|
|
uint32_t offset = addr & 0x3fffff;
|
|
|
|
|
|
|
|
ip = ipack_device_find(&s->bus, ip_n);
|
|
|
|
|
|
|
|
if (ip == NULL) {
|
|
|
|
DPRINTF("Write LAS3: IP module %u not installed\n", ip_n);
|
|
|
|
} else {
|
|
|
|
IPackDeviceClass *k = IPACK_DEVICE_GET_CLASS(ip);
|
|
|
|
if (k->mem_write8) {
|
|
|
|
k->mem_write8(ip, offset, val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps tpci200_cfg_ops = {
|
|
|
|
.read = tpci200_read_cfg,
|
|
|
|
.write = tpci200_write_cfg,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 4
|
|
|
|
},
|
|
|
|
.impl = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 1
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps tpci200_las0_ops = {
|
|
|
|
.read = tpci200_read_las0,
|
|
|
|
.write = tpci200_write_las0,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 2,
|
|
|
|
.max_access_size = 2
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps tpci200_las1_ops = {
|
|
|
|
.read = tpci200_read_las1,
|
|
|
|
.write = tpci200_write_las1,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 2
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps tpci200_las2_ops = {
|
|
|
|
.read = tpci200_read_las2,
|
|
|
|
.write = tpci200_write_las2,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 2
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps tpci200_las3_ops = {
|
|
|
|
.read = tpci200_read_las3,
|
|
|
|
.write = tpci200_write_las3,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 1,
|
|
|
|
.max_access_size = 1
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static int tpci200_initfn(PCIDevice *pci_dev)
|
|
|
|
{
|
|
|
|
TPCI200State *s = TPCI200(pci_dev);
|
|
|
|
uint8_t *c = s->dev.config;
|
|
|
|
|
|
|
|
pci_set_word(c + PCI_COMMAND, 0x0003);
|
|
|
|
pci_set_word(c + PCI_STATUS, 0x0280);
|
|
|
|
|
|
|
|
pci_set_byte(c + PCI_INTERRUPT_PIN, 0x01); /* Interrupt pin A */
|
|
|
|
|
|
|
|
pci_set_byte(c + PCI_CAPABILITY_LIST, 0x40);
|
|
|
|
pci_set_long(c + 0x40, 0x48014801);
|
|
|
|
pci_set_long(c + 0x48, 0x00024C06);
|
|
|
|
pci_set_long(c + 0x4C, 0x00000003);
|
|
|
|
|
|
|
|
memory_region_init_io(&s->mmio, &tpci200_cfg_ops,
|
|
|
|
s, "tpci200_mmio", 128);
|
|
|
|
memory_region_init_io(&s->io, &tpci200_cfg_ops,
|
|
|
|
s, "tpci200_io", 128);
|
|
|
|
memory_region_init_io(&s->las0, &tpci200_las0_ops,
|
|
|
|
s, "tpci200_las0", 256);
|
|
|
|
memory_region_init_io(&s->las1, &tpci200_las1_ops,
|
|
|
|
s, "tpci200_las1", 1024);
|
|
|
|
memory_region_init_io(&s->las2, &tpci200_las2_ops,
|
|
|
|
s, "tpci200_las2", 1024*1024*32);
|
|
|
|
memory_region_init_io(&s->las3, &tpci200_las3_ops,
|
|
|
|
s, "tpci200_las3", 1024*1024*16);
|
|
|
|
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
|
|
|
|
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
|
|
|
|
pci_register_bar(&s->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las0);
|
|
|
|
pci_register_bar(&s->dev, 3, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las1);
|
|
|
|
pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las2);
|
|
|
|
pci_register_bar(&s->dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->las3);
|
|
|
|
|
|
|
|
ipack_bus_new_inplace(&s->bus, DEVICE(&s->dev), NULL,
|
|
|
|
N_MODULES, tpci200_set_irq);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tpci200_exitfn(PCIDevice *pci_dev)
|
|
|
|
{
|
|
|
|
TPCI200State *s = TPCI200(pci_dev);
|
|
|
|
|
|
|
|
memory_region_destroy(&s->mmio);
|
|
|
|
memory_region_destroy(&s->io);
|
|
|
|
memory_region_destroy(&s->las0);
|
|
|
|
memory_region_destroy(&s->las1);
|
|
|
|
memory_region_destroy(&s->las2);
|
|
|
|
memory_region_destroy(&s->las3);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_tpci200 = {
|
|
|
|
.name = "tpci200",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_PCI_DEVICE(dev, TPCI200State),
|
|
|
|
VMSTATE_BOOL_ARRAY(big_endian, TPCI200State, 3),
|
|
|
|
VMSTATE_UINT8_ARRAY(ctrl, TPCI200State, N_MODULES),
|
|
|
|
VMSTATE_UINT16(status, TPCI200State),
|
|
|
|
VMSTATE_UINT8(int_set, TPCI200State),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static void tpci200_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->init = tpci200_initfn;
|
|
|
|
k->exit = tpci200_exitfn;
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_TEWS;
|
|
|
|
k->device_id = PCI_DEVICE_ID_TEWS_TPCI200;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_OTHER;
|
|
|
|
k->subsystem_vendor_id = PCI_VENDOR_ID_TEWS;
|
|
|
|
k->subsystem_id = 0x300A;
|
|
|
|
dc->desc = "TEWS TPCI200 IndustryPack carrier";
|
|
|
|
dc->vmsd = &vmstate_tpci200;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo tpci200_info = {
|
|
|
|
.name = TYPE_TPCI200,
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(TPCI200State),
|
|
|
|
.class_init = tpci200_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void tpci200_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&tpci200_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(tpci200_register_types)
|