2016-12-15 20:26:14 +01:00
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/*
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* HPPA emulation cpu helpers for qemu.
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2020-10-23 14:33:53 +02:00
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* version 2.1 of the License, or (at your option) any later version.
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2016-12-15 20:26:14 +01:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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2022-02-07 09:27:56 +01:00
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#include "qemu/log.h"
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2016-12-15 20:26:14 +01:00
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#include "cpu.h"
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#include "fpu/softfloat.h"
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2019-03-11 20:16:00 +01:00
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#include "exec/exec-all.h"
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2016-12-15 20:26:14 +01:00
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#include "exec/helper-proto.h"
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2019-04-17 21:18:02 +02:00
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#include "qemu/qemu-print.h"
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2016-12-15 20:26:14 +01:00
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2017-10-09 21:35:48 +02:00
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target_ureg cpu_hppa_get_psw(CPUHPPAState *env)
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2016-12-15 20:26:14 +01:00
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{
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2017-10-09 21:35:48 +02:00
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target_ureg psw;
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2016-12-15 20:26:14 +01:00
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/* Fold carry bits down to 8 consecutive bits. */
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/* ??? Needs tweaking for hppa64. */
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/* .......b...c...d...e...f...g...h */
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psw = (env->psw_cb >> 4) & 0x01111111;
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/* .......b..bc..cd..de..ef..fg..gh */
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psw |= psw >> 3;
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/* .............bcd............efgh */
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psw |= (psw >> 6) & 0x000f000f;
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/* .........................bcdefgh */
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psw |= (psw >> 12) & 0xf;
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psw |= env->psw_cb_msb << 7;
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2017-10-09 01:00:40 +02:00
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psw = (psw & 0xff) << 8;
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2016-12-15 20:26:14 +01:00
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2017-10-09 01:00:40 +02:00
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psw |= env->psw_n * PSW_N;
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psw |= (env->psw_v < 0) * PSW_V;
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psw |= env->psw;
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2016-12-15 20:26:14 +01:00
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return psw;
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}
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2017-10-09 21:35:48 +02:00
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void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw)
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2016-12-15 20:26:14 +01:00
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{
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2019-03-11 20:16:00 +01:00
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target_ureg old_psw = env->psw;
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2017-10-09 21:35:48 +02:00
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target_ureg cb = 0;
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2016-12-15 20:26:14 +01:00
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2017-10-09 01:00:40 +02:00
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env->psw = psw & ~(PSW_N | PSW_V | PSW_CB);
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env->psw_n = (psw / PSW_N) & 1;
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env->psw_v = -((psw / PSW_V) & 1);
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2016-12-15 20:26:14 +01:00
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env->psw_cb_msb = (psw >> 15) & 1;
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cb |= ((psw >> 14) & 1) << 28;
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cb |= ((psw >> 13) & 1) << 24;
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cb |= ((psw >> 12) & 1) << 20;
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cb |= ((psw >> 11) & 1) << 16;
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cb |= ((psw >> 10) & 1) << 12;
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cb |= ((psw >> 9) & 1) << 8;
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cb |= ((psw >> 8) & 1) << 4;
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env->psw_cb = cb;
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2019-03-11 20:16:00 +01:00
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/* If PSW_P changes, it affects how we translate addresses. */
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if ((psw ^ old_psw) & PSW_P) {
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#ifndef CONFIG_USER_ONLY
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2019-03-23 01:51:33 +01:00
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tlb_flush_by_mmuidx(env_cpu(env), 0xf);
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2019-03-11 20:16:00 +01:00
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#endif
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}
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2016-12-15 20:26:14 +01:00
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}
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2019-04-17 21:18:02 +02:00
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void hppa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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2016-12-15 20:26:14 +01:00
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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CPUHPPAState *env = &cpu->env;
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2017-10-09 21:35:48 +02:00
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target_ureg psw = cpu_hppa_get_psw(env);
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target_ureg psw_cb;
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2017-10-09 01:00:40 +02:00
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char psw_c[20];
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2016-12-15 20:26:14 +01:00
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int i;
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2022-09-18 21:45:49 +02:00
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qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx
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" IIR " TREG_FMT_lx "\n",
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2019-04-17 21:18:02 +02:00
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hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f),
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2022-09-18 21:45:49 +02:00
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hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b),
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env->cr[CR_IIR]);
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2017-10-09 01:00:40 +02:00
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psw_c[0] = (psw & PSW_W ? 'W' : '-');
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psw_c[1] = (psw & PSW_E ? 'E' : '-');
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psw_c[2] = (psw & PSW_S ? 'S' : '-');
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psw_c[3] = (psw & PSW_T ? 'T' : '-');
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psw_c[4] = (psw & PSW_H ? 'H' : '-');
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psw_c[5] = (psw & PSW_L ? 'L' : '-');
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psw_c[6] = (psw & PSW_N ? 'N' : '-');
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psw_c[7] = (psw & PSW_X ? 'X' : '-');
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psw_c[8] = (psw & PSW_B ? 'B' : '-');
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psw_c[9] = (psw & PSW_C ? 'C' : '-');
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psw_c[10] = (psw & PSW_V ? 'V' : '-');
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psw_c[11] = (psw & PSW_M ? 'M' : '-');
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psw_c[12] = (psw & PSW_F ? 'F' : '-');
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psw_c[13] = (psw & PSW_R ? 'R' : '-');
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psw_c[14] = (psw & PSW_Q ? 'Q' : '-');
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psw_c[15] = (psw & PSW_P ? 'P' : '-');
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psw_c[16] = (psw & PSW_D ? 'D' : '-');
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psw_c[17] = (psw & PSW_I ? 'I' : '-');
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psw_c[18] = '\0';
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psw_cb = ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28);
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2019-04-17 21:18:02 +02:00
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qemu_fprintf(f, "PSW " TREG_FMT_lx " CB " TREG_FMT_lx " %s\n",
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psw, psw_cb, psw_c);
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2017-10-09 01:00:40 +02:00
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for (i = 0; i < 32; i++) {
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2019-04-17 21:18:02 +02:00
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qemu_fprintf(f, "GR%02d " TREG_FMT_lx "%c", i, env->gr[i],
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(i & 3) == 3 ? '\n' : ' ');
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2017-10-10 07:54:12 +02:00
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}
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#ifndef CONFIG_USER_ONLY
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for (i = 0; i < 8; i++) {
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2019-04-17 21:18:02 +02:00
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qemu_fprintf(f, "SR%02d %08x%c", i, (uint32_t)(env->sr[i] >> 32),
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(i & 3) == 3 ? '\n' : ' ');
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2016-12-15 20:26:14 +01:00
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}
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2017-10-10 07:54:12 +02:00
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#endif
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2019-04-17 21:18:02 +02:00
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qemu_fprintf(f, "\n");
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2016-12-15 20:26:14 +01:00
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/* ??? FR */
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}
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