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qemu-e2k/target/xtensa/helper.h

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target-xtensa: switch to AREG0-free mode Add env parameter to every helper function that needs it, update 'configure' script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-10 09:33:12 +02:00
DEF_HELPER_2(exception, noreturn, env, i32)
DEF_HELPER_3(exception_cause, noreturn, env, i32, i32)
DEF_HELPER_4(exception_cause_vaddr, noreturn, env, i32, i32, i32)
DEF_HELPER_3(debug_exception, noreturn, env, i32, i32)
target-xtensa: implement instruction breakpoints Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and BREAK.N instructions and IBREAK breakpoints. IBREAK breakpoint address is considered constant for TB lifetime. On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-01-13 06:21:32 +01:00
target/xtensa: move WINDOW_BASE SR update to postprocessing Opcodes that modify WINDOW_BASE SR don't have dependency on opcodes that use windowed registers. If such opcodes are combined in a single instruction they may not be correctly ordered. Instead of adding said dependency use temporary register to store changed WINDOW_BASE value and do actual register window rotation as a postprocessing step. Not all opcodes that change WINDOW_BASE need this: retw, rfwo and rfwu are also jump opcodes, so they are guaranteed to be translated last and thus will not affect other opcodes in the same instruction. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-30 23:56:29 +01:00
DEF_HELPER_1(sync_windowbase, void, env)
target-xtensa: switch to AREG0-free mode Add env parameter to every helper function that needs it, update 'configure' script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-10 09:33:12 +02:00
DEF_HELPER_4(entry, void, env, i32, i32, i32)
target/xtensa: extract test for an illegal instruction - TB flags: add XTENSA_TBFLAG_CWOE that corresponds to the architectural CWOE state; - entry: move CWOE check from the helper to the test_ill_entry; - retw: move CWOE check from the helper to the test_ill_retw; - separate instruction disassembly loop and translation loop; save disassembly results in local array; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-28 06:43:43 +02:00
DEF_HELPER_2(test_ill_retw, void, env, i32)
target/xtensa: extract test for window underflow exception - mark retw and retw.n instructions; - extract window inderflow test from retw helper; - put underflow exception check generation right after the overflow check; Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-08-31 02:55:33 +02:00
DEF_HELPER_2(test_underflow_retw, void, env, i32)
target/xtensa: only rotate window in the retw helper Move return address calculation and WINDOW_START adjustment out of the retw helper to simplify logic a bit and avoid using registers directly. Pass a0 as a parameter to the helper. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-11 21:22:29 +01:00
DEF_HELPER_2(retw, void, env, i32)
target-xtensa: record available window in TB flags Record last valid 4-register window pane number in TB flags so that a window overflow exception throw point is known at the translation time. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-30 16:07:47 +01:00
DEF_HELPER_3(window_check, noreturn, env, i32, i32)
target-xtensa: switch to AREG0-free mode Add env parameter to every helper function that needs it, update 'configure' script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-10 09:33:12 +02:00
DEF_HELPER_1(restore_owb, void, env)
DEF_HELPER_2(movsp, void, env, i32)
target/xtensa: add linux-user support Import list of syscalls from the kernel source. Conditionalize code/data that is only used with softmmu. Implement exception handlers. Implement signal hander (only the core registers for now, no coprocessors or TIE). Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-25 19:54:11 +01:00
#ifndef CONFIG_USER_ONLY
target-xtensa: implement SIMCALL Tensilica iss provides support for applications running in freestanding environment through SIMCALL command. It is used by Tensilica libc to access argc/argv, for file I/O, etc. Note that simcalls that accept buffer addresses expect virtual addresses. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 01:55:47 +02:00
DEF_HELPER_1(simcall, void, env)
target/xtensa: add linux-user support Import list of syscalls from the kernel source. Conditionalize code/data that is only used with softmmu. Implement exception handlers. Implement signal hander (only the core registers for now, no coprocessors or TIE). Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-25 19:54:11 +01:00
#endif
target-xtensa: implement disas_xtensa_insn Set up disas_xtensa_insn switch structure, mark required options on high level groups. Implement arithmetic/bit logic/jump/call0. Implement code generation loop with single step/breakpoint checking. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 01:55:27 +02:00
target/xtensa: add linux-user support Import list of syscalls from the kernel source. Conditionalize code/data that is only used with softmmu. Implement exception handlers. Implement signal hander (only the core registers for now, no coprocessors or TIE). Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-25 19:54:11 +01:00
#ifndef CONFIG_USER_ONLY
target-xtensa: switch to AREG0-free mode Add env parameter to every helper function that needs it, update 'configure' script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-10 09:33:12 +02:00
DEF_HELPER_3(waiti, void, env, i32, i32)
target/xtensa: refactor CCOUNT/CCOMPARE Xtensa cores may have a register (CCOUNT) that counts core clock cycles. It may also have a number of registers (CCOMPAREx); when CCOUNT value passes the value of CCOMPAREx, timer interrupt x is raised. Currently xtensa target counts a number of completed instructions and assumes that for CCOUNT one instruction takes one cycle to complete. It calls helper function to update CCOUNT register at every TB end and raise timer interrupts. This scheme works very predictably and doesn't have noticeable performance impact, but it is hard to use with multiple synchronized processors, especially with coming MTTCG. Derive CCOUNT from the virtual simulation time, QEMU_CLOCK_VIRTUAL. Use native QEMU timers for CCOMPARE timers, one timer for each register. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-09-04 02:57:49 +02:00
DEF_HELPER_1(update_ccount, void, env)
DEF_HELPER_2(wsr_ccount, void, env, i32)
DEF_HELPER_2(update_ccompare, void, env, i32)
target-xtensa: implement interrupt option See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt option) and 4.4.8 (timer interrupt option) for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 01:55:48 +02:00
DEF_HELPER_1(check_interrupts, void, env)
target/xtensa: fix access to the INTERRUPT SR INTERRUPT special register may be changed both by the core (by writing to INTSET and INTCLEAR registers) and by external events (by triggering and clearing HW IRQs). In MTTCG this state must be protected from concurrent access, otherwise interrupts may be lost or spurious interrupts may be detected. Use atomic operations to change INTSET SR. Fix wsr.intset so that it soesn't clear any bits. Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-01-24 04:26:52 +01:00
DEF_HELPER_2(intset, void, env, i32)
DEF_HELPER_2(intclear, void, env, i32)
target-xtensa: implement ATOMCTL SR ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory type. See ISA, 4.3.12.4 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-05 04:15:20 +01:00
DEF_HELPER_3(check_atomctl, void, env, i32, i32)
target/xtensa: implement exclusive access option The Exclusive Instructions provide a general-purpose mechanism for atomic updates of memory-based synchronization variables that can be used for exclusion algorithms. Use cmpxchg-based implementation that is sufficient for the typical use of exclusive access in atomic operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-04-19 01:37:00 +02:00
DEF_HELPER_4(check_exclusive, void, env, i32, i32, i32)
target/xtensa: implement MEMCTL SR MEMCTL SR controls zero overhead loop buffer and number of ways enabled in L1 caches. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2016-11-12 07:40:18 +01:00
DEF_HELPER_2(wsr_memctl, void, env, i32)
target-xtensa: implement interrupt option See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt option) and 4.4.8 (timer interrupt option) for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 01:55:48 +02:00
target-xtensa: add basic checks to icache opcodes Check privilege level for privileged instructions (IHU, III, IIU and IPFL are privileged), memory accessibility for instructions that reference memory (IH* and IPFL) and windowed register validity for all instruction cache instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-07 12:57:22 +01:00
DEF_HELPER_2(itlb_hit_test, void, env, i32)
target-xtensa: switch to AREG0-free mode Add env parameter to every helper function that needs it, update 'configure' script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-10 09:33:12 +02:00
DEF_HELPER_2(wsr_rasid, void, env, i32)
target-xtensa: rename helper flags Rename helper flags to the new ones. This is purely a mechanical change, it's possible to use better flags by looking at the helpers. Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-09 21:53:09 +02:00
DEF_HELPER_FLAGS_3(rtlb0, TCG_CALL_NO_RWG_SE, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(rtlb1, TCG_CALL_NO_RWG_SE, i32, env, i32, i32)
target-xtensa: switch to AREG0-free mode Add env parameter to every helper function that needs it, update 'configure' script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-10 09:33:12 +02:00
DEF_HELPER_3(itlb, void, env, i32, i32)
DEF_HELPER_3(ptlb, i32, env, i32, i32)
DEF_HELPER_4(wtlb, void, env, i32, i32, i32)
target/xtensa: implement MPU option The Memory Protection Unit Option (MPU) is a combined instruction and data memory protection unit with more protection flexibility than the Region Protection Option or the Region Translation Option but without any translation capability. It does no demand paging and does not reference a memory-based page table. Add memory protection unit option, internal state, SRs and opcodes. Implement MPU entries dumping in dump_mmu. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-03-13 20:40:38 +01:00
DEF_HELPER_2(wsr_mpuenb, void, env, i32)
DEF_HELPER_3(wptlb, void, env, i32, i32)
DEF_HELPER_FLAGS_2(rptlb0, TCG_CALL_NO_RWG_SE, i32, env, i32)
DEF_HELPER_FLAGS_2(rptlb1, TCG_CALL_NO_RWG_SE, i32, env, i32)
DEF_HELPER_2(pptlb, i32, env, i32)
target-xtensa: implement memory protection options - TLB opcode group; - region protection option (ISA, 4.6.3); - region translation option (ISA, 4.6.4); - MMU option (ISA, 4.6.5). Cache control attribute bits are not used by this implementation. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-06 01:55:53 +02:00
target-xtensa: switch to AREG0-free mode Add env parameter to every helper function that needs it, update 'configure' script. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-10 09:33:12 +02:00
DEF_HELPER_2(wsr_ibreakenable, void, env, i32)
DEF_HELPER_3(wsr_ibreaka, void, env, i32, i32)
DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32)
DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32)
target/xtensa: add linux-user support Import list of syscalls from the kernel source. Conditionalize code/data that is only used with softmmu. Implement exception handlers. Implement signal hander (only the core registers for now, no coprocessors or TIE). Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-25 19:54:11 +01:00
#endif
target-xtensa: implement instruction breakpoints Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and BREAK.N instructions and IBREAK breakpoints. IBREAK breakpoint address is considered constant for TB lifetime. On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-01-13 06:21:32 +01:00
target/xtensa: rename FPU2000 translators and helpers Add _s suffix to all FPU2000 opcode translators and helpers that also have double-precision variant to unify naming and allow adding DFPU implementations. Add _fpu2k_ to the names of helpers that will have different implementation for the DFPU . Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2015-07-13 03:30:41 +02:00
DEF_HELPER_2(wur_fpu2k_fcr, void, env, i32)
target-xtensa: rename helper flags Rename helper flags to the new ones. This is purely a mechanical change, it's possible to use better flags by looking at the helpers. Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-09 21:53:09 +02:00
DEF_HELPER_FLAGS_1(abs_s, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_1(neg_s, TCG_CALL_NO_RWG_SE, f32, f32)
target/xtensa: rename FPU2000 translators and helpers Add _s suffix to all FPU2000 opcode translators and helpers that also have double-precision variant to unify naming and allow adding DFPU implementations. Add _fpu2k_ to the names of helpers that will have different implementation for the DFPU . Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2015-07-13 03:30:41 +02:00
DEF_HELPER_3(fpu2k_add_s, f32, env, f32, f32)
DEF_HELPER_3(fpu2k_sub_s, f32, env, f32, f32)
DEF_HELPER_3(fpu2k_mul_s, f32, env, f32, f32)
DEF_HELPER_4(fpu2k_madd_s, f32, env, f32, f32, f32)
DEF_HELPER_4(fpu2k_msub_s, f32, env, f32, f32, f32)
target/xtensa: add DFPU registers and opcodes DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA does not specify how single-precision values are stored in 64-bit registers. Existing implementations store them in the low half of the registers. Add value extraction and write back to single-precision opcodes. Add new double precision opcodes. Add 64-bit register file. Add 64-bit values dumping to the xtensa_cpu_dump_state. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-01 04:27:02 +02:00
DEF_HELPER_4(ftoi_s, i32, env, f32, i32, i32)
DEF_HELPER_4(ftoui_s, i32, env, f32, i32, i32)
target/xtensa: rename FPU2000 translators and helpers Add _s suffix to all FPU2000 opcode translators and helpers that also have double-precision variant to unify naming and allow adding DFPU implementations. Add _fpu2k_ to the names of helpers that will have different implementation for the DFPU . Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2015-07-13 03:30:41 +02:00
DEF_HELPER_3(itof_s, f32, env, i32, i32)
DEF_HELPER_3(uitof_s, f32, env, i32, i32)
target/xtensa: add DFPU registers and opcodes DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA does not specify how single-precision values are stored in 64-bit registers. Existing implementations store them in the low half of the registers. Add value extraction and write back to single-precision opcodes. Add new double precision opcodes. Add 64-bit register file. Add 64-bit values dumping to the xtensa_cpu_dump_state. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-01 04:27:02 +02:00
DEF_HELPER_2(cvtd_s, f64, env, f32)
target-xtensa: add FP registers There are 16 32-bit FP registers (f0 - f15), control and status user registers (fcr, fsr). See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-09-19 02:23:54 +02:00
target/xtensa: don't access BR regfile directly BR registers used in FPU comparison opcodes are available as opcode arguments for translators. Use them. This simplifies comparison helpers interface and makes them usable in FLIX bundles. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-06-30 16:50:14 +02:00
DEF_HELPER_3(un_s, i32, env, f32, f32)
DEF_HELPER_3(oeq_s, i32, env, f32, f32)
DEF_HELPER_3(ueq_s, i32, env, f32, f32)
DEF_HELPER_3(olt_s, i32, env, f32, f32)
DEF_HELPER_3(ult_s, i32, env, f32, f32)
DEF_HELPER_3(ole_s, i32, env, f32, f32)
DEF_HELPER_3(ule_s, i32, env, f32, f32)
target-xtensa: implement RER/WER instructions RER and WER are privileged instructions for accessing external registers. External register address space is local to processor core. There's no alignment requirements, addressable units are 32-bit wide registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-26 12:48:41 +01:00
target/xtensa: add DFPU registers and opcodes DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA does not specify how single-precision values are stored in 64-bit registers. Existing implementations store them in the low half of the registers. Add value extraction and write back to single-precision opcodes. Add new double precision opcodes. Add 64-bit register file. Add 64-bit values dumping to the xtensa_cpu_dump_state. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-01 04:27:02 +02:00
DEF_HELPER_2(wur_fpu_fcr, void, env, i32)
DEF_HELPER_1(rur_fpu_fsr, i32, env)
DEF_HELPER_2(wur_fpu_fsr, void, env, i32)
DEF_HELPER_FLAGS_1(abs_d, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_FLAGS_1(neg_d, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_3(add_d, f64, env, f64, f64)
DEF_HELPER_3(add_s, f32, env, f32, f32)
DEF_HELPER_3(sub_d, f64, env, f64, f64)
DEF_HELPER_3(sub_s, f32, env, f32, f32)
DEF_HELPER_3(mul_d, f64, env, f64, f64)
DEF_HELPER_3(mul_s, f32, env, f32, f32)
DEF_HELPER_4(madd_d, f64, env, f64, f64, f64)
DEF_HELPER_4(madd_s, f32, env, f32, f32, f32)
DEF_HELPER_4(msub_d, f64, env, f64, f64, f64)
DEF_HELPER_4(msub_s, f32, env, f32, f32, f32)
target/xtensa: implement FPU division and square root This does not implement all opcodes related to div/sqrt as specified in the xtensa ISA, partly because the official specification is not complete and partly because precise implementation is unnecessarily complex. Instead instructions specific to the div/sqrt sequences are implemented differently, most of them as nops, but the results of div/sqrt sequences is preserved. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-03-14 19:13:53 +01:00
DEF_HELPER_3(mkdadj_d, f64, env, f64, f64)
DEF_HELPER_3(mkdadj_s, f32, env, f32, f32)
DEF_HELPER_2(mksadj_d, f64, env, f64)
DEF_HELPER_2(mksadj_s, f32, env, f32)
target/xtensa: add DFPU registers and opcodes DFPU may be configured with 32-bit or with 64-bit registers. Xtensa ISA does not specify how single-precision values are stored in 64-bit registers. Existing implementations store them in the low half of the registers. Add value extraction and write back to single-precision opcodes. Add new double precision opcodes. Add 64-bit register file. Add 64-bit values dumping to the xtensa_cpu_dump_state. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-07-01 04:27:02 +02:00
DEF_HELPER_4(ftoi_d, i32, env, f64, i32, i32)
DEF_HELPER_4(ftoui_d, i32, env, f64, i32, i32)
DEF_HELPER_3(itof_d, f64, env, i32, i32)
DEF_HELPER_3(uitof_d, f64, env, i32, i32)
DEF_HELPER_2(cvts_d, f32, env, f64)
DEF_HELPER_3(un_d, i32, env, f64, f64)
DEF_HELPER_3(oeq_d, i32, env, f64, f64)
DEF_HELPER_3(ueq_d, i32, env, f64, f64)
DEF_HELPER_3(olt_d, i32, env, f64, f64)
DEF_HELPER_3(ult_d, i32, env, f64, f64)
DEF_HELPER_3(ole_d, i32, env, f64, f64)
DEF_HELPER_3(ule_d, i32, env, f64, f64)
target-xtensa: implement RER/WER instructions RER and WER are privileged instructions for accessing external registers. External register address space is local to processor core. There's no alignment requirements, addressable units are 32-bit wide registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-26 12:48:41 +01:00
DEF_HELPER_2(rer, i32, env, i32)
DEF_HELPER_3(wer, void, env, i32, i32)
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