2012-06-21 17:40:09 +02:00
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/*
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* Copyright (c) 2007, Neocleus Corporation.
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* Copyright (c) 2007, Intel Corporation.
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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* Alex Novik <alex@neocleus.com>
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* Allen Kay <allen.m.kay@intel.com>
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* Guy Zana <guy@neocleus.com>
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*
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* This file implements direct PCI assignment to a HVM guest
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*/
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/*
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* Interrupt Disable policy:
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*
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* INTx interrupt:
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* Initialize(register_real_device)
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* Map INTx(xc_physdev_map_pirq):
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* <fail>
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* - Set real Interrupt Disable bit to '1'.
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* - Set machine_irq and assigned_device->machine_irq to '0'.
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* * Don't bind INTx.
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*
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* Bind INTx(xc_domain_bind_pt_pci_irq):
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* <fail>
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* - Set real Interrupt Disable bit to '1'.
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* - Unmap INTx.
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* - Decrement xen_pt_mapped_machine_irq[machine_irq]
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* - Set assigned_device->machine_irq to '0'.
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*
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* Write to Interrupt Disable bit by guest software(xen_pt_cmd_reg_write)
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* Write '0'
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* - Set real bit to '0' if assigned_device->machine_irq isn't '0'.
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*
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* Write '1'
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* - Set real bit to '1'.
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2012-06-21 17:42:35 +02:00
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*
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* MSI interrupt:
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* Initialize MSI register(xen_pt_msi_setup, xen_pt_msi_update)
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* Bind MSI(xc_domain_update_msi_irq)
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* <fail>
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* - Unmap MSI.
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* - Set dev->msi->pirq to '-1'.
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*
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* MSI-X interrupt:
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* Initialize MSI-X register(xen_pt_msix_update_one)
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* Bind MSI-X(xc_domain_update_msi_irq)
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* <fail>
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* - Unmap MSI-X.
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* - Set entry->pirq to '-1'.
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2012-06-21 17:40:09 +02:00
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*/
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2016-01-26 19:17:06 +01:00
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#include "qemu/osdep.h"
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2012-06-21 17:40:09 +02:00
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#include <sys/ioctl.h>
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2013-02-04 15:40:22 +01:00
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#include "hw/pci/pci.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/xen/xen.h"
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2015-07-15 07:37:48 +02:00
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#include "hw/i386/pc.h"
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2013-02-05 17:06:20 +01:00
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#include "hw/xen/xen_backend.h"
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2013-03-18 17:36:02 +01:00
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#include "xen_pt.h"
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2012-12-17 18:20:00 +01:00
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#include "qemu/range.h"
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2012-12-17 18:19:49 +01:00
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#include "exec/address-spaces.h"
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2012-06-21 17:40:09 +02:00
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#define XEN_PT_NR_IRQS (256)
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static uint8_t xen_pt_mapped_machine_irq[XEN_PT_NR_IRQS] = {0};
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void xen_pt_log(const PCIDevice *d, const char *f, ...)
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{
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va_list ap;
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va_start(ap, f);
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if (d) {
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fprintf(stderr, "[%02x:%02x.%d] ", pci_bus_num(d->bus),
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PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
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}
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vfprintf(stderr, f, ap);
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va_end(ap);
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}
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/* Config Space */
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static int xen_pt_pci_config_access_check(PCIDevice *d, uint32_t addr, int len)
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{
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/* check offset range */
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if (addr >= 0xFF) {
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XEN_PT_ERR(d, "Failed to access register with offset exceeding 0xFF. "
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"(addr: 0x%02x, len: %d)\n", addr, len);
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return -1;
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}
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/* check read size */
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if ((len != 1) && (len != 2) && (len != 4)) {
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XEN_PT_ERR(d, "Failed to access register with invalid access length. "
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"(addr: 0x%02x, len: %d)\n", addr, len);
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return -1;
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}
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/* check offset alignment */
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if (addr & (len - 1)) {
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XEN_PT_ERR(d, "Failed to access register with invalid access size "
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"alignment. (addr: 0x%02x, len: %d)\n", addr, len);
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return -1;
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}
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return 0;
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}
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int xen_pt_bar_offset_to_index(uint32_t offset)
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{
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int index = 0;
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/* check Exp ROM BAR */
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if (offset == PCI_ROM_ADDRESS) {
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return PCI_ROM_SLOT;
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}
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/* calculate BAR index */
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index = (offset - PCI_BASE_ADDRESS_0) >> 2;
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if (index >= PCI_NUM_REGIONS) {
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return -1;
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}
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return index;
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}
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static uint32_t xen_pt_pci_read_config(PCIDevice *d, uint32_t addr, int len)
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{
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2015-05-13 02:43:26 +02:00
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XenPCIPassthroughState *s = XEN_PT_DEVICE(d);
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2012-06-21 17:40:09 +02:00
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uint32_t val = 0;
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XenPTRegGroup *reg_grp_entry = NULL;
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XenPTReg *reg_entry = NULL;
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int rc = 0;
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int emul_len = 0;
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uint32_t find_addr = addr;
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if (xen_pt_pci_config_access_check(d, addr, len)) {
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goto exit;
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}
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/* find register group entry */
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reg_grp_entry = xen_pt_find_reg_grp(s, addr);
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if (reg_grp_entry) {
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/* check 0-Hardwired register group */
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if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED) {
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/* no need to emulate, just return 0 */
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val = 0;
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goto exit;
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}
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}
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/* read I/O device register value */
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rc = xen_host_pci_get_block(&s->real_device, addr, (uint8_t *)&val, len);
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if (rc < 0) {
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XEN_PT_ERR(d, "pci_read_block failed. return value: %d.\n", rc);
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memset(&val, 0xff, len);
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}
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/* just return the I/O device register value for
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* passthrough type register group */
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if (reg_grp_entry == NULL) {
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goto exit;
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}
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/* adjust the read value to appropriate CFC-CFF window */
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val <<= (addr & 3) << 3;
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emul_len = len;
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/* loop around the guest requested size */
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while (emul_len > 0) {
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/* find register entry to be emulated */
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reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr);
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if (reg_entry) {
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XenPTRegInfo *reg = reg_entry->reg;
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uint32_t real_offset = reg_grp_entry->base_offset + reg->offset;
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uint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3);
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uint8_t *ptr_val = NULL;
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valid_mask <<= (find_addr - real_offset) << 3;
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ptr_val = (uint8_t *)&val + (real_offset & 3);
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/* do emulation based on register size */
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switch (reg->size) {
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case 1:
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if (reg->u.b.read) {
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rc = reg->u.b.read(s, reg_entry, ptr_val, valid_mask);
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}
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break;
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case 2:
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if (reg->u.w.read) {
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rc = reg->u.w.read(s, reg_entry,
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(uint16_t *)ptr_val, valid_mask);
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}
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break;
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case 4:
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if (reg->u.dw.read) {
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rc = reg->u.dw.read(s, reg_entry,
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(uint32_t *)ptr_val, valid_mask);
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}
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break;
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}
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if (rc < 0) {
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xen_shutdown_fatal_error("Internal error: Invalid read "
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"emulation. (%s, rc: %d)\n",
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__func__, rc);
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return 0;
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}
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/* calculate next address to find */
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emul_len -= reg->size;
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if (emul_len > 0) {
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find_addr = real_offset + reg->size;
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}
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} else {
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/* nothing to do with passthrough type register,
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* continue to find next byte */
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emul_len--;
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find_addr++;
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}
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}
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/* need to shift back before returning them to pci bus emulator */
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val >>= ((addr & 3) << 3);
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exit:
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XEN_PT_LOG_CONFIG(d, addr, val, len);
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return val;
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}
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static void xen_pt_pci_write_config(PCIDevice *d, uint32_t addr,
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uint32_t val, int len)
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{
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2015-05-13 02:43:26 +02:00
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XenPCIPassthroughState *s = XEN_PT_DEVICE(d);
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2012-06-21 17:40:09 +02:00
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int index = 0;
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XenPTRegGroup *reg_grp_entry = NULL;
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int rc = 0;
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2015-06-02 17:07:00 +02:00
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uint32_t read_val = 0, wb_mask;
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2012-06-21 17:40:09 +02:00
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int emul_len = 0;
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XenPTReg *reg_entry = NULL;
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uint32_t find_addr = addr;
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XenPTRegInfo *reg = NULL;
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2015-06-02 17:07:01 +02:00
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bool wp_flag = false;
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2012-06-21 17:40:09 +02:00
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if (xen_pt_pci_config_access_check(d, addr, len)) {
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return;
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}
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XEN_PT_LOG_CONFIG(d, addr, val, len);
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/* check unused BAR register */
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index = xen_pt_bar_offset_to_index(addr);
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2015-06-08 15:11:51 +02:00
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if ((index >= 0) && (val != 0)) {
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uint32_t chk = val;
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if (index == PCI_ROM_SLOT)
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chk |= (uint32_t)~PCI_ROM_ADDRESS_MASK;
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if ((chk != XEN_PT_BAR_ALLF) &&
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(s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED)) {
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XEN_PT_WARN(d, "Guest attempt to set address to unused "
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"Base Address Register. (addr: 0x%02x, len: %d)\n",
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addr, len);
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}
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2012-06-21 17:40:09 +02:00
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}
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/* find register group entry */
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reg_grp_entry = xen_pt_find_reg_grp(s, addr);
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if (reg_grp_entry) {
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/* check 0-Hardwired register group */
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if (reg_grp_entry->reg_grp->grp_type == XEN_PT_GRP_TYPE_HARDWIRED) {
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/* ignore silently */
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XEN_PT_WARN(d, "Access to 0-Hardwired register. "
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"(addr: 0x%02x, len: %d)\n", addr, len);
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return;
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}
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}
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rc = xen_host_pci_get_block(&s->real_device, addr,
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(uint8_t *)&read_val, len);
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if (rc < 0) {
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XEN_PT_ERR(d, "pci_read_block failed. return value: %d.\n", rc);
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memset(&read_val, 0xff, len);
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2015-06-02 17:07:00 +02:00
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wb_mask = 0;
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} else {
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wb_mask = 0xFFFFFFFF >> ((4 - len) << 3);
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2012-06-21 17:40:09 +02:00
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}
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/* pass directly to the real device for passthrough type register group */
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if (reg_grp_entry == NULL) {
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2015-06-02 17:07:01 +02:00
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if (!s->permissive) {
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wb_mask = 0;
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wp_flag = true;
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}
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2012-06-21 17:40:09 +02:00
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goto out;
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}
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memory_region_transaction_begin();
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pci_default_write_config(d, addr, val, len);
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/* adjust the read and write value to appropriate CFC-CFF window */
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read_val <<= (addr & 3) << 3;
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val <<= (addr & 3) << 3;
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emul_len = len;
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/* loop around the guest requested size */
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while (emul_len > 0) {
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/* find register entry to be emulated */
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reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr);
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if (reg_entry) {
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reg = reg_entry->reg;
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uint32_t real_offset = reg_grp_entry->base_offset + reg->offset;
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uint32_t valid_mask = 0xFFFFFFFF >> ((4 - emul_len) << 3);
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uint8_t *ptr_val = NULL;
|
2015-06-02 17:07:01 +02:00
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uint32_t wp_mask = reg->emu_mask | reg->ro_mask;
|
2012-06-21 17:40:09 +02:00
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valid_mask <<= (find_addr - real_offset) << 3;
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ptr_val = (uint8_t *)&val + (real_offset & 3);
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2015-06-02 17:07:01 +02:00
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if (!s->permissive) {
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wp_mask |= reg->res_mask;
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}
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if (wp_mask == (0xFFFFFFFF >> ((4 - reg->size) << 3))) {
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wb_mask &= ~((wp_mask >> ((find_addr - real_offset) << 3))
|
2015-06-02 17:07:00 +02:00
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<< ((len - emul_len) << 3));
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}
|
2012-06-21 17:40:09 +02:00
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/* do emulation based on register size */
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switch (reg->size) {
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case 1:
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if (reg->u.b.write) {
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rc = reg->u.b.write(s, reg_entry, ptr_val,
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read_val >> ((real_offset & 3) << 3),
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valid_mask);
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}
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break;
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case 2:
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if (reg->u.w.write) {
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rc = reg->u.w.write(s, reg_entry, (uint16_t *)ptr_val,
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|
|
(read_val >> ((real_offset & 3) << 3)),
|
|
|
|
valid_mask);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
if (reg->u.dw.write) {
|
|
|
|
rc = reg->u.dw.write(s, reg_entry, (uint32_t *)ptr_val,
|
|
|
|
(read_val >> ((real_offset & 3) << 3)),
|
|
|
|
valid_mask);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rc < 0) {
|
|
|
|
xen_shutdown_fatal_error("Internal error: Invalid write"
|
|
|
|
" emulation. (%s, rc: %d)\n",
|
|
|
|
__func__, rc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* calculate next address to find */
|
|
|
|
emul_len -= reg->size;
|
|
|
|
if (emul_len > 0) {
|
|
|
|
find_addr = real_offset + reg->size;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* nothing to do with passthrough type register,
|
|
|
|
* continue to find next byte */
|
2015-06-02 17:07:01 +02:00
|
|
|
if (!s->permissive) {
|
|
|
|
wb_mask &= ~(0xff << ((len - emul_len) << 3));
|
|
|
|
/* Unused BARs will make it here, but we don't want to issue
|
|
|
|
* warnings for writes to them (bogus writes get dealt with
|
|
|
|
* above).
|
|
|
|
*/
|
|
|
|
if (index < 0) {
|
|
|
|
wp_flag = true;
|
|
|
|
}
|
|
|
|
}
|
2012-06-21 17:40:09 +02:00
|
|
|
emul_len--;
|
|
|
|
find_addr++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-06-24 23:16:01 +02:00
|
|
|
/* need to shift back before passing them to xen_host_pci_set_block. */
|
2012-06-21 17:40:09 +02:00
|
|
|
val >>= (addr & 3) << 3;
|
|
|
|
|
|
|
|
memory_region_transaction_commit();
|
|
|
|
|
|
|
|
out:
|
2015-06-02 17:07:01 +02:00
|
|
|
if (wp_flag && !s->permissive_warned) {
|
|
|
|
s->permissive_warned = true;
|
|
|
|
xen_pt_log(d, "Write-back to unknown field 0x%02x (partially) inhibited (0x%0*x)\n",
|
|
|
|
addr, len * 2, wb_mask);
|
|
|
|
xen_pt_log(d, "If the device doesn't work, try enabling permissive mode\n");
|
|
|
|
xen_pt_log(d, "(unsafe) and if it helps report the problem to xen-devel\n");
|
|
|
|
}
|
2015-06-02 17:07:00 +02:00
|
|
|
for (index = 0; wb_mask; index += len) {
|
2012-06-21 17:40:09 +02:00
|
|
|
/* unknown regs are passed through */
|
2015-06-02 17:07:00 +02:00
|
|
|
while (!(wb_mask & 0xff)) {
|
|
|
|
index++;
|
|
|
|
wb_mask >>= 8;
|
|
|
|
}
|
|
|
|
len = 0;
|
|
|
|
do {
|
|
|
|
len++;
|
|
|
|
wb_mask >>= 8;
|
|
|
|
} while (wb_mask & 0xff);
|
|
|
|
rc = xen_host_pci_set_block(&s->real_device, addr + index,
|
|
|
|
(uint8_t *)&val + index, len);
|
2012-06-21 17:40:09 +02:00
|
|
|
|
|
|
|
if (rc < 0) {
|
2015-06-24 23:16:01 +02:00
|
|
|
XEN_PT_ERR(d, "xen_host_pci_set_block failed. return value: %d.\n", rc);
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* register regions */
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t xen_pt_bar_read(void *o, hwaddr addr,
|
2012-06-21 17:40:09 +02:00
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
PCIDevice *d = o;
|
|
|
|
/* if this function is called, that probably means that there is a
|
|
|
|
* misconfiguration of the IOMMU. */
|
|
|
|
XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"TARGET_FMT_plx"\n",
|
|
|
|
addr);
|
|
|
|
return 0;
|
|
|
|
}
|
2012-10-23 12:30:10 +02:00
|
|
|
static void xen_pt_bar_write(void *o, hwaddr addr, uint64_t val,
|
2012-06-21 17:40:09 +02:00
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
PCIDevice *d = o;
|
|
|
|
/* Same comment as xen_pt_bar_read function */
|
|
|
|
XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"TARGET_FMT_plx"\n",
|
|
|
|
addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps ops = {
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.read = xen_pt_bar_read,
|
|
|
|
.write = xen_pt_bar_write,
|
|
|
|
};
|
|
|
|
|
2015-03-31 16:18:03 +02:00
|
|
|
static int xen_pt_register_regions(XenPCIPassthroughState *s, uint16_t *cmd)
|
2012-06-21 17:40:09 +02:00
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
XenHostPCIDevice *d = &s->real_device;
|
|
|
|
|
|
|
|
/* Register PIO/MMIO BARs */
|
|
|
|
for (i = 0; i < PCI_ROM_SLOT; i++) {
|
|
|
|
XenHostPCIIORegion *r = &d->io_regions[i];
|
|
|
|
uint8_t type;
|
|
|
|
|
|
|
|
if (r->base_addr == 0 || r->size == 0) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
s->bases[i].access.u = r->base_addr;
|
|
|
|
|
|
|
|
if (r->type & XEN_HOST_PCI_REGION_TYPE_IO) {
|
|
|
|
type = PCI_BASE_ADDRESS_SPACE_IO;
|
2015-03-31 16:18:03 +02:00
|
|
|
*cmd |= PCI_COMMAND_IO;
|
2012-06-21 17:40:09 +02:00
|
|
|
} else {
|
|
|
|
type = PCI_BASE_ADDRESS_SPACE_MEMORY;
|
|
|
|
if (r->type & XEN_HOST_PCI_REGION_TYPE_PREFETCH) {
|
|
|
|
type |= PCI_BASE_ADDRESS_MEM_PREFETCH;
|
|
|
|
}
|
2012-10-03 15:46:23 +02:00
|
|
|
if (r->type & XEN_HOST_PCI_REGION_TYPE_MEM_64) {
|
|
|
|
type |= PCI_BASE_ADDRESS_MEM_TYPE_64;
|
|
|
|
}
|
2015-03-31 16:18:03 +02:00
|
|
|
*cmd |= PCI_COMMAND_MEMORY;
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&s->bar[i], OBJECT(s), &ops, &s->dev,
|
2012-06-21 17:40:09 +02:00
|
|
|
"xen-pci-pt-bar", r->size);
|
|
|
|
pci_register_bar(&s->dev, i, type, &s->bar[i]);
|
|
|
|
|
2014-01-10 16:52:54 +01:00
|
|
|
XEN_PT_LOG(&s->dev, "IO region %i registered (size=0x%08"PRIx64
|
|
|
|
" base_addr=0x%08"PRIx64" type: %#x)\n",
|
2012-06-21 17:40:09 +02:00
|
|
|
i, r->size, r->base_addr, type);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Register expansion ROM address */
|
|
|
|
if (d->rom.base_addr && d->rom.size) {
|
|
|
|
uint32_t bar_data = 0;
|
|
|
|
|
|
|
|
/* Re-set BAR reported by OS, otherwise ROM can't be read. */
|
|
|
|
if (xen_host_pci_get_long(d, PCI_ROM_ADDRESS, &bar_data)) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if ((bar_data & PCI_ROM_ADDRESS_MASK) == 0) {
|
|
|
|
bar_data |= d->rom.base_addr & PCI_ROM_ADDRESS_MASK;
|
|
|
|
xen_host_pci_set_long(d, PCI_ROM_ADDRESS, bar_data);
|
|
|
|
}
|
|
|
|
|
|
|
|
s->bases[PCI_ROM_SLOT].access.maddr = d->rom.base_addr;
|
|
|
|
|
2014-01-10 16:56:33 +01:00
|
|
|
memory_region_init_io(&s->rom, OBJECT(s), &ops, &s->dev,
|
|
|
|
"xen-pci-pt-rom", d->rom.size);
|
2012-06-21 17:40:09 +02:00
|
|
|
pci_register_bar(&s->dev, PCI_ROM_SLOT, PCI_BASE_ADDRESS_MEM_PREFETCH,
|
|
|
|
&s->rom);
|
|
|
|
|
|
|
|
XEN_PT_LOG(&s->dev, "Expansion ROM registered (size=0x%08"PRIx64
|
|
|
|
" base_addr=0x%08"PRIx64")\n",
|
|
|
|
d->rom.size, d->rom.base_addr);
|
|
|
|
}
|
|
|
|
|
2015-07-15 07:37:45 +02:00
|
|
|
xen_pt_register_vga_regions(d);
|
2012-06-21 17:40:09 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* region mapping */
|
|
|
|
|
|
|
|
static int xen_pt_bar_from_region(XenPCIPassthroughState *s, MemoryRegion *mr)
|
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < PCI_NUM_REGIONS - 1; i++) {
|
|
|
|
if (mr == &s->bar[i]) {
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (mr == &s->rom) {
|
|
|
|
return PCI_ROM_SLOT;
|
|
|
|
}
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function checks if an io_region overlaps an io_region from another
|
|
|
|
* device. The io_region to check is provided with (addr, size and type)
|
|
|
|
* A callback can be provided and will be called for every region that is
|
|
|
|
* overlapped.
|
|
|
|
* The return value indicates if the region is overlappsed */
|
|
|
|
struct CheckBarArgs {
|
|
|
|
XenPCIPassthroughState *s;
|
|
|
|
pcibus_t addr;
|
|
|
|
pcibus_t size;
|
|
|
|
uint8_t type;
|
|
|
|
bool rc;
|
|
|
|
};
|
|
|
|
static void xen_pt_check_bar_overlap(PCIBus *bus, PCIDevice *d, void *opaque)
|
|
|
|
{
|
|
|
|
struct CheckBarArgs *arg = opaque;
|
|
|
|
XenPCIPassthroughState *s = arg->s;
|
|
|
|
uint8_t type = arg->type;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (d->devfn == s->dev.devfn) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* xxx: This ignores bridges. */
|
|
|
|
for (i = 0; i < PCI_NUM_REGIONS; i++) {
|
|
|
|
const PCIIORegion *r = &d->io_regions[i];
|
|
|
|
|
|
|
|
if (!r->size) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if ((type & PCI_BASE_ADDRESS_SPACE_IO)
|
|
|
|
!= (r->type & PCI_BASE_ADDRESS_SPACE_IO)) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ranges_overlap(arg->addr, arg->size, r->addr, r->size)) {
|
|
|
|
XEN_PT_WARN(&s->dev,
|
|
|
|
"Overlapped to device [%02x:%02x.%d] Region: %i"
|
|
|
|
" (addr: %#"FMT_PCIBUS", len: %#"FMT_PCIBUS")\n",
|
|
|
|
pci_bus_num(bus), PCI_SLOT(d->devfn),
|
|
|
|
PCI_FUNC(d->devfn), i, r->addr, r->size);
|
|
|
|
arg->rc = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xen_pt_region_update(XenPCIPassthroughState *s,
|
|
|
|
MemoryRegionSection *sec, bool adding)
|
|
|
|
{
|
|
|
|
PCIDevice *d = &s->dev;
|
|
|
|
MemoryRegion *mr = sec->mr;
|
|
|
|
int bar = -1;
|
|
|
|
int rc;
|
|
|
|
int op = adding ? DPCI_ADD_MAPPING : DPCI_REMOVE_MAPPING;
|
|
|
|
struct CheckBarArgs args = {
|
|
|
|
.s = s,
|
|
|
|
.addr = sec->offset_within_address_space,
|
2013-05-27 10:08:27 +02:00
|
|
|
.size = int128_get64(sec->size),
|
2012-06-21 17:40:09 +02:00
|
|
|
.rc = false,
|
|
|
|
};
|
|
|
|
|
|
|
|
bar = xen_pt_bar_from_region(s, mr);
|
2012-06-21 17:42:35 +02:00
|
|
|
if (bar == -1 && (!s->msix || &s->msix->mmio != mr)) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->msix && &s->msix->mmio == mr) {
|
|
|
|
if (adding) {
|
|
|
|
s->msix->mmio_base_addr = sec->offset_within_address_space;
|
|
|
|
rc = xen_pt_msix_update_remap(s, s->msix->bar_index);
|
|
|
|
}
|
2012-06-21 17:40:09 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
args.type = d->io_regions[bar].type;
|
|
|
|
pci_for_each_device(d->bus, pci_bus_num(d->bus),
|
|
|
|
xen_pt_check_bar_overlap, &args);
|
|
|
|
if (args.rc) {
|
|
|
|
XEN_PT_WARN(d, "Region: %d (addr: %#"FMT_PCIBUS
|
|
|
|
", len: %#"FMT_PCIBUS") is overlapped.\n",
|
2013-10-14 14:53:53 +02:00
|
|
|
bar, sec->offset_within_address_space,
|
|
|
|
int128_get64(sec->size));
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (d->io_regions[bar].type & PCI_BASE_ADDRESS_SPACE_IO) {
|
|
|
|
uint32_t guest_port = sec->offset_within_address_space;
|
|
|
|
uint32_t machine_port = s->bases[bar].access.pio_base;
|
2013-05-27 10:08:27 +02:00
|
|
|
uint32_t size = int128_get64(sec->size);
|
2012-06-21 17:40:09 +02:00
|
|
|
rc = xc_domain_ioport_mapping(xen_xc, xen_domid,
|
|
|
|
guest_port, machine_port, size,
|
|
|
|
op);
|
|
|
|
if (rc) {
|
2015-06-05 14:04:18 +02:00
|
|
|
XEN_PT_ERR(d, "%s ioport mapping failed! (err: %i)\n",
|
|
|
|
adding ? "create new" : "remove old", errno);
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
} else {
|
|
|
|
pcibus_t guest_addr = sec->offset_within_address_space;
|
|
|
|
pcibus_t machine_addr = s->bases[bar].access.maddr
|
|
|
|
+ sec->offset_within_region;
|
2013-05-27 10:08:27 +02:00
|
|
|
pcibus_t size = int128_get64(sec->size);
|
2012-06-21 17:40:09 +02:00
|
|
|
rc = xc_domain_memory_mapping(xen_xc, xen_domid,
|
|
|
|
XEN_PFN(guest_addr + XC_PAGE_SIZE - 1),
|
|
|
|
XEN_PFN(machine_addr + XC_PAGE_SIZE - 1),
|
|
|
|
XEN_PFN(size + XC_PAGE_SIZE - 1),
|
|
|
|
op);
|
|
|
|
if (rc) {
|
2015-06-05 14:04:18 +02:00
|
|
|
XEN_PT_ERR(d, "%s mem mapping failed! (err: %i)\n",
|
|
|
|
adding ? "create new" : "remove old", errno);
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xen_pt_region_add(MemoryListener *l, MemoryRegionSection *sec)
|
|
|
|
{
|
|
|
|
XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState,
|
|
|
|
memory_listener);
|
|
|
|
|
2013-05-06 10:46:11 +02:00
|
|
|
memory_region_ref(sec->mr);
|
2012-06-21 17:40:09 +02:00
|
|
|
xen_pt_region_update(s, sec, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xen_pt_region_del(MemoryListener *l, MemoryRegionSection *sec)
|
|
|
|
{
|
|
|
|
XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState,
|
|
|
|
memory_listener);
|
|
|
|
|
|
|
|
xen_pt_region_update(s, sec, false);
|
2013-05-06 10:46:11 +02:00
|
|
|
memory_region_unref(sec->mr);
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
|
2012-09-30 22:21:11 +02:00
|
|
|
static void xen_pt_io_region_add(MemoryListener *l, MemoryRegionSection *sec)
|
|
|
|
{
|
|
|
|
XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState,
|
|
|
|
io_listener);
|
|
|
|
|
2013-05-06 10:46:11 +02:00
|
|
|
memory_region_ref(sec->mr);
|
2012-09-30 22:21:11 +02:00
|
|
|
xen_pt_region_update(s, sec, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void xen_pt_io_region_del(MemoryListener *l, MemoryRegionSection *sec)
|
|
|
|
{
|
|
|
|
XenPCIPassthroughState *s = container_of(l, XenPCIPassthroughState,
|
|
|
|
io_listener);
|
|
|
|
|
|
|
|
xen_pt_region_update(s, sec, false);
|
2013-05-06 10:46:11 +02:00
|
|
|
memory_region_unref(sec->mr);
|
2012-09-30 22:21:11 +02:00
|
|
|
}
|
|
|
|
|
2012-06-21 17:40:09 +02:00
|
|
|
static const MemoryListener xen_pt_memory_listener = {
|
|
|
|
.region_add = xen_pt_region_add,
|
|
|
|
.region_del = xen_pt_region_del,
|
|
|
|
.priority = 10,
|
|
|
|
};
|
|
|
|
|
2012-09-30 22:21:11 +02:00
|
|
|
static const MemoryListener xen_pt_io_listener = {
|
|
|
|
.region_add = xen_pt_io_region_add,
|
|
|
|
.region_del = xen_pt_io_region_del,
|
|
|
|
.priority = 10,
|
|
|
|
};
|
|
|
|
|
2015-07-15 07:37:48 +02:00
|
|
|
static void
|
|
|
|
xen_igd_passthrough_isa_bridge_create(XenPCIPassthroughState *s,
|
|
|
|
XenHostPCIDevice *dev)
|
|
|
|
{
|
|
|
|
uint16_t gpu_dev_id;
|
|
|
|
PCIDevice *d = &s->dev;
|
|
|
|
|
|
|
|
gpu_dev_id = dev->device_id;
|
|
|
|
igd_passthrough_isa_bridge_create(d->bus, gpu_dev_id);
|
|
|
|
}
|
|
|
|
|
2015-09-08 22:21:59 +02:00
|
|
|
/* destroy. */
|
|
|
|
static void xen_pt_destroy(PCIDevice *d) {
|
|
|
|
|
|
|
|
XenPCIPassthroughState *s = XEN_PT_DEVICE(d);
|
|
|
|
XenHostPCIDevice *host_dev = &s->real_device;
|
|
|
|
uint8_t machine_irq = s->machine_irq;
|
|
|
|
uint8_t intx;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (machine_irq && !xen_host_pci_device_closed(&s->real_device)) {
|
|
|
|
intx = xen_pt_pci_intx(s);
|
|
|
|
rc = xc_domain_unbind_pt_irq(xen_xc, xen_domid, machine_irq,
|
|
|
|
PT_IRQ_TYPE_PCI,
|
|
|
|
pci_bus_num(d->bus),
|
|
|
|
PCI_SLOT(s->dev.devfn),
|
|
|
|
intx,
|
|
|
|
0 /* isa_irq */);
|
|
|
|
if (rc < 0) {
|
|
|
|
XEN_PT_ERR(d, "unbinding of interrupt INT%c failed."
|
|
|
|
" (machine irq: %i, err: %d)"
|
|
|
|
" But bravely continuing on..\n",
|
|
|
|
'a' + intx, machine_irq, errno);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* N.B. xen_pt_config_delete takes care of freeing them. */
|
|
|
|
if (s->msi) {
|
|
|
|
xen_pt_msi_disable(s);
|
|
|
|
}
|
|
|
|
if (s->msix) {
|
|
|
|
xen_pt_msix_disable(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (machine_irq) {
|
|
|
|
xen_pt_mapped_machine_irq[machine_irq]--;
|
|
|
|
|
|
|
|
if (xen_pt_mapped_machine_irq[machine_irq] == 0) {
|
|
|
|
rc = xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq);
|
|
|
|
|
|
|
|
if (rc < 0) {
|
|
|
|
XEN_PT_ERR(d, "unmapping of interrupt %i failed. (err: %d)"
|
|
|
|
" But bravely continuing on..\n",
|
|
|
|
machine_irq, errno);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
s->machine_irq = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* delete all emulated config registers */
|
|
|
|
xen_pt_config_delete(s);
|
|
|
|
|
|
|
|
xen_pt_unregister_vga_regions(host_dev);
|
|
|
|
|
|
|
|
if (s->listener_set) {
|
|
|
|
memory_listener_unregister(&s->memory_listener);
|
|
|
|
memory_listener_unregister(&s->io_listener);
|
|
|
|
s->listener_set = false;
|
|
|
|
}
|
|
|
|
if (!xen_host_pci_device_closed(&s->real_device)) {
|
|
|
|
xen_host_pci_device_put(&s->real_device);
|
|
|
|
}
|
|
|
|
}
|
2012-06-21 17:40:09 +02:00
|
|
|
/* init */
|
|
|
|
|
2016-01-17 13:13:15 +01:00
|
|
|
static void xen_pt_realize(PCIDevice *d, Error **errp)
|
2012-06-21 17:40:09 +02:00
|
|
|
{
|
2015-05-13 02:43:26 +02:00
|
|
|
XenPCIPassthroughState *s = XEN_PT_DEVICE(d);
|
2016-01-17 13:13:15 +01:00
|
|
|
int i, rc = 0;
|
2015-06-29 20:01:13 +02:00
|
|
|
uint8_t machine_irq = 0, scratch;
|
2015-03-31 16:18:03 +02:00
|
|
|
uint16_t cmd = 0;
|
2012-06-21 17:40:09 +02:00
|
|
|
int pirq = XEN_PT_UNASSIGNED_PIRQ;
|
2016-01-17 13:13:12 +01:00
|
|
|
Error *err = NULL;
|
2012-06-21 17:40:09 +02:00
|
|
|
|
|
|
|
/* register real device */
|
|
|
|
XEN_PT_LOG(d, "Assigning real physical device %02x:%02x.%d"
|
|
|
|
" to devfn %#x\n",
|
|
|
|
s->hostaddr.bus, s->hostaddr.slot, s->hostaddr.function,
|
|
|
|
s->dev.devfn);
|
|
|
|
|
2016-01-17 13:13:12 +01:00
|
|
|
xen_host_pci_device_get(&s->real_device,
|
|
|
|
s->hostaddr.domain, s->hostaddr.bus,
|
|
|
|
s->hostaddr.slot, s->hostaddr.function,
|
|
|
|
&err);
|
|
|
|
if (err) {
|
|
|
|
error_append_hint(&err, "Failed to \"open\" the real pci device");
|
2016-01-17 13:13:15 +01:00
|
|
|
error_propagate(errp, err);
|
|
|
|
return;
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
s->is_virtfn = s->real_device.is_virtfn;
|
|
|
|
if (s->is_virtfn) {
|
|
|
|
XEN_PT_LOG(d, "%04x:%02x:%02x.%d is a SR-IOV Virtual Function\n",
|
2012-12-17 12:37:43 +01:00
|
|
|
s->real_device.domain, s->real_device.bus,
|
|
|
|
s->real_device.dev, s->real_device.func);
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize virtualized PCI configuration (Extended 256 Bytes) */
|
2015-07-08 21:58:41 +02:00
|
|
|
memset(d->config, 0, PCI_CONFIG_SPACE_SIZE);
|
2012-06-21 17:40:09 +02:00
|
|
|
|
|
|
|
s->memory_listener = xen_pt_memory_listener;
|
2012-09-30 22:21:11 +02:00
|
|
|
s->io_listener = xen_pt_io_listener;
|
2012-06-21 17:40:09 +02:00
|
|
|
|
2015-07-15 07:37:46 +02:00
|
|
|
/* Setup VGA bios for passthrough GFX */
|
|
|
|
if ((s->real_device.domain == 0) && (s->real_device.bus == 0) &&
|
|
|
|
(s->real_device.dev == 2) && (s->real_device.func == 0)) {
|
2015-07-15 07:37:48 +02:00
|
|
|
if (!is_igd_vga_passthrough(&s->real_device)) {
|
2016-01-17 13:13:15 +01:00
|
|
|
error_setg(errp, "Need to enable igd-passthru if you're trying"
|
|
|
|
" to passthrough IGD GFX");
|
2015-07-15 07:37:48 +02:00
|
|
|
xen_host_pci_device_put(&s->real_device);
|
2016-01-17 13:13:15 +01:00
|
|
|
return;
|
2015-07-15 07:37:48 +02:00
|
|
|
}
|
|
|
|
|
2016-01-17 13:13:13 +01:00
|
|
|
xen_pt_setup_vga(s, &s->real_device, &err);
|
|
|
|
if (err) {
|
|
|
|
error_append_hint(&err, "Setup VGA BIOS of passthrough"
|
|
|
|
" GFX failed");
|
2016-01-17 13:13:15 +01:00
|
|
|
error_propagate(errp, err);
|
2015-07-15 07:37:46 +02:00
|
|
|
xen_host_pci_device_put(&s->real_device);
|
2016-01-17 13:13:15 +01:00
|
|
|
return;
|
2015-07-15 07:37:46 +02:00
|
|
|
}
|
2015-07-15 07:37:48 +02:00
|
|
|
|
|
|
|
/* Register ISA bridge for passthrough GFX. */
|
|
|
|
xen_igd_passthrough_isa_bridge_create(s, &s->real_device);
|
2015-07-15 07:37:46 +02:00
|
|
|
}
|
|
|
|
|
2012-06-21 17:40:09 +02:00
|
|
|
/* Handle real device's MMIO/PIO BARs */
|
2015-03-31 16:18:03 +02:00
|
|
|
xen_pt_register_regions(s, &cmd);
|
2012-06-21 17:40:09 +02:00
|
|
|
|
2012-06-21 17:40:48 +02:00
|
|
|
/* reinitialize each config register to be emulated */
|
2016-01-17 13:13:14 +01:00
|
|
|
xen_pt_config_init(s, &err);
|
|
|
|
if (err) {
|
|
|
|
error_append_hint(&err, "PCI Config space initialisation failed");
|
|
|
|
error_report_err(err);
|
|
|
|
rc = -1;
|
2015-07-02 20:33:44 +02:00
|
|
|
goto err_out;
|
2012-06-21 17:40:48 +02:00
|
|
|
}
|
|
|
|
|
2012-06-21 17:40:09 +02:00
|
|
|
/* Bind interrupt */
|
2015-06-29 20:01:13 +02:00
|
|
|
rc = xen_host_pci_get_byte(&s->real_device, PCI_INTERRUPT_PIN, &scratch);
|
|
|
|
if (rc) {
|
2016-01-17 13:13:15 +01:00
|
|
|
error_setg_errno(errp, errno, "Failed to read PCI_INTERRUPT_PIN");
|
2015-07-02 20:33:44 +02:00
|
|
|
goto err_out;
|
2015-06-29 20:01:13 +02:00
|
|
|
}
|
|
|
|
if (!scratch) {
|
2016-01-17 13:13:15 +01:00
|
|
|
error_setg(errp, "no pin interrupt");
|
2012-06-21 17:40:09 +02:00
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
machine_irq = s->real_device.irq;
|
|
|
|
rc = xc_physdev_map_pirq(xen_xc, xen_domid, machine_irq, &pirq);
|
|
|
|
if (rc < 0) {
|
2016-01-17 13:13:15 +01:00
|
|
|
error_setg_errno(errp, errno, "Mapping machine irq %u to"
|
|
|
|
" pirq %i failed", machine_irq, pirq);
|
2012-06-21 17:40:09 +02:00
|
|
|
|
|
|
|
/* Disable PCI intx assertion (turn on bit10 of devctl) */
|
2015-05-15 14:46:11 +02:00
|
|
|
cmd |= PCI_COMMAND_INTX_DISABLE;
|
2012-06-21 17:40:09 +02:00
|
|
|
machine_irq = 0;
|
|
|
|
s->machine_irq = 0;
|
|
|
|
} else {
|
|
|
|
machine_irq = pirq;
|
|
|
|
s->machine_irq = pirq;
|
|
|
|
xen_pt_mapped_machine_irq[machine_irq]++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* bind machine_irq to device */
|
|
|
|
if (machine_irq != 0) {
|
|
|
|
uint8_t e_intx = xen_pt_pci_intx(s);
|
|
|
|
|
|
|
|
rc = xc_domain_bind_pt_pci_irq(xen_xc, xen_domid, machine_irq,
|
|
|
|
pci_bus_num(d->bus),
|
|
|
|
PCI_SLOT(d->devfn),
|
|
|
|
e_intx);
|
|
|
|
if (rc < 0) {
|
2016-01-17 13:13:15 +01:00
|
|
|
error_setg_errno(errp, errno, "Binding of interrupt %u failed",
|
|
|
|
e_intx);
|
2012-06-21 17:40:09 +02:00
|
|
|
|
|
|
|
/* Disable PCI intx assertion (turn on bit10 of devctl) */
|
2015-05-15 14:46:11 +02:00
|
|
|
cmd |= PCI_COMMAND_INTX_DISABLE;
|
2012-06-21 17:40:09 +02:00
|
|
|
xen_pt_mapped_machine_irq[machine_irq]--;
|
|
|
|
|
|
|
|
if (xen_pt_mapped_machine_irq[machine_irq] == 0) {
|
|
|
|
if (xc_physdev_unmap_pirq(xen_xc, xen_domid, machine_irq)) {
|
2016-01-17 13:13:15 +01:00
|
|
|
error_setg_errno(errp, errno, "Unmapping of machine"
|
|
|
|
" interrupt %u failed", machine_irq);
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
s->machine_irq = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
2015-03-31 16:18:03 +02:00
|
|
|
if (cmd) {
|
2015-06-29 20:01:13 +02:00
|
|
|
uint16_t val;
|
|
|
|
|
|
|
|
rc = xen_host_pci_get_word(&s->real_device, PCI_COMMAND, &val);
|
|
|
|
if (rc) {
|
2016-01-17 13:13:15 +01:00
|
|
|
error_setg_errno(errp, errno, "Failed to read PCI_COMMAND");
|
2015-07-02 20:33:44 +02:00
|
|
|
goto err_out;
|
2015-06-29 20:01:13 +02:00
|
|
|
} else {
|
|
|
|
val |= cmd;
|
|
|
|
rc = xen_host_pci_set_word(&s->real_device, PCI_COMMAND, val);
|
|
|
|
if (rc) {
|
2016-01-17 13:13:15 +01:00
|
|
|
error_setg_errno(errp, errno, "Failed to write PCI_COMMAND"
|
|
|
|
" val = 0x%x", val);
|
2015-07-02 20:33:44 +02:00
|
|
|
goto err_out;
|
2015-06-29 20:01:13 +02:00
|
|
|
}
|
|
|
|
}
|
2015-03-31 16:18:03 +02:00
|
|
|
}
|
|
|
|
|
2015-01-13 03:40:53 +01:00
|
|
|
memory_listener_register(&s->memory_listener, &s->dev.bus_master_as);
|
2012-10-02 20:13:51 +02:00
|
|
|
memory_listener_register(&s->io_listener, &address_space_io);
|
2015-09-08 22:21:29 +02:00
|
|
|
s->listener_set = true;
|
2013-07-24 19:48:56 +02:00
|
|
|
XEN_PT_LOG(d,
|
2016-01-17 13:13:15 +01:00
|
|
|
"Real physical device %02x:%02x.%d registered successfully\n",
|
2012-12-17 12:37:43 +01:00
|
|
|
s->hostaddr.bus, s->hostaddr.slot, s->hostaddr.function);
|
2012-06-21 17:40:09 +02:00
|
|
|
|
2016-01-17 13:13:15 +01:00
|
|
|
return;
|
2015-07-02 20:33:44 +02:00
|
|
|
|
|
|
|
err_out:
|
2016-01-17 13:13:15 +01:00
|
|
|
for (i = 0; i < PCI_ROM_SLOT; i++) {
|
|
|
|
object_unparent(OBJECT(&s->bar[i]));
|
|
|
|
}
|
|
|
|
object_unparent(OBJECT(&s->rom));
|
|
|
|
|
2015-07-02 20:33:44 +02:00
|
|
|
xen_pt_destroy(d);
|
|
|
|
assert(rc);
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
|
2012-08-01 12:19:09 +02:00
|
|
|
static void xen_pt_unregister_device(PCIDevice *d)
|
2012-06-21 17:40:09 +02:00
|
|
|
{
|
2015-09-08 22:21:59 +02:00
|
|
|
xen_pt_destroy(d);
|
2012-06-21 17:40:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static Property xen_pci_passthrough_properties[] = {
|
|
|
|
DEFINE_PROP_PCI_HOST_DEVADDR("hostaddr", XenPCIPassthroughState, hostaddr),
|
2015-06-02 17:07:01 +02:00
|
|
|
DEFINE_PROP_BOOL("permissive", XenPCIPassthroughState, permissive, false),
|
2012-06-21 17:40:09 +02:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void xen_pci_passthrough_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
2016-01-17 13:13:15 +01:00
|
|
|
k->realize = xen_pt_realize;
|
2012-06-21 17:40:09 +02:00
|
|
|
k->exit = xen_pt_unregister_device;
|
|
|
|
k->config_read = xen_pt_pci_read_config;
|
|
|
|
k->config_write = xen_pt_pci_write_config;
|
2013-07-29 16:17:45 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
|
2012-06-21 17:40:09 +02:00
|
|
|
dc->desc = "Assign an host PCI device with Xen";
|
|
|
|
dc->props = xen_pci_passthrough_properties;
|
|
|
|
};
|
|
|
|
|
2015-10-11 17:19:24 +02:00
|
|
|
static void xen_pci_passthrough_finalize(Object *obj)
|
|
|
|
{
|
|
|
|
XenPCIPassthroughState *s = XEN_PT_DEVICE(obj);
|
|
|
|
|
|
|
|
xen_pt_msix_delete(s);
|
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo xen_pci_passthrough_info = {
|
2015-05-13 02:43:26 +02:00
|
|
|
.name = TYPE_XEN_PT_DEVICE,
|
2012-06-21 17:40:09 +02:00
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(XenPCIPassthroughState),
|
2015-10-11 17:19:24 +02:00
|
|
|
.instance_finalize = xen_pci_passthrough_finalize,
|
2012-06-21 17:40:09 +02:00
|
|
|
.class_init = xen_pci_passthrough_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void xen_pci_passthrough_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&xen_pci_passthrough_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(xen_pci_passthrough_register_types)
|