2004-12-20 00:18:01 +01:00
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/*
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* QEMU Sparc SLAVIO timer controller emulation
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*
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2005-04-06 22:47:48 +02:00
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* Copyright (c) 2003-2005 Fabrice Bellard
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2007-09-16 23:08:06 +02:00
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*
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2004-12-20 00:18:01 +01:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2007-11-17 18:14:51 +01:00
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#include "hw.h"
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#include "sun4m.h"
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#include "qemu-timer.h"
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2004-12-20 00:18:01 +01:00
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//#define DEBUG_TIMER
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2005-04-06 22:47:48 +02:00
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#ifdef DEBUG_TIMER
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#define DPRINTF(fmt, args...) \
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do { printf("TIMER: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...)
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#endif
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2004-12-20 00:18:01 +01:00
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/*
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* Registers of hardware timer in sun4m.
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*
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* This is the timer/counter part of chip STP2001 (Slave I/O), also
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* produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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2007-09-16 23:08:06 +02:00
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*
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2004-12-20 00:18:01 +01:00
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* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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* are zero. Bit 31 is 1 when count has been reached.
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*
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2005-12-05 21:31:52 +01:00
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* Per-CPU timers interrupt local CPU, system timer uses normal
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* interrupt routing.
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*
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2004-12-20 00:18:01 +01:00
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*/
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2007-10-06 13:25:43 +02:00
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#define MAX_CPUS 16
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2004-12-20 00:18:01 +01:00
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typedef struct SLAVIO_TIMERState {
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2007-05-27 18:37:49 +02:00
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qemu_irq irq;
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2007-05-24 21:48:41 +02:00
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ptimer_state *timer;
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uint32_t count, counthigh, reached;
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uint64_t limit;
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2007-10-07 12:00:55 +02:00
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// processor only
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int running;
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struct SLAVIO_TIMERState *master;
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int slave_index;
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// system only
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2007-12-17 19:17:17 +01:00
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unsigned int num_slaves;
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2007-10-06 13:25:43 +02:00
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struct SLAVIO_TIMERState *slave[MAX_CPUS];
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uint32_t slave_mode;
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2004-12-20 00:18:01 +01:00
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} SLAVIO_TIMERState;
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#define TIMER_MAXADDR 0x1f
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2007-10-07 12:00:55 +02:00
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#define SYS_TIMER_SIZE 0x14
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2007-10-06 13:25:43 +02:00
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#define CPU_TIMER_SIZE 0x10
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2004-12-20 00:18:01 +01:00
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2007-12-01 16:58:22 +01:00
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#define SYS_TIMER_OFFSET 0x10000ULL
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#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
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#define TIMER_LIMIT 0
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#define TIMER_COUNTER 1
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#define TIMER_COUNTER_NORST 2
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#define TIMER_STATUS 3
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#define TIMER_MODE 4
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#define TIMER_COUNT_MASK32 0xfffffe00
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#define TIMER_LIMIT_MASK32 0x7fffffff
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#define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
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#define TIMER_MAX_COUNT32 0x7ffffe00ULL
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#define TIMER_REACHED 0x80000000
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#define TIMER_PERIOD 500ULL // 500ns
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#define LIMIT_TO_PERIODS(l) ((l) >> 9)
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#define PERIODS_TO_LIMIT(l) ((l) << 9)
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2007-10-07 12:00:55 +02:00
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static int slavio_timer_is_user(SLAVIO_TIMERState *s)
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{
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return s->master && (s->master->slave_mode & (1 << s->slave_index));
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}
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2004-12-20 00:18:01 +01:00
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// Update count, set irq, update expire_time
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2007-05-24 21:48:41 +02:00
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// Convert from ptimer countdown units
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2004-12-20 00:18:01 +01:00
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static void slavio_timer_get_out(SLAVIO_TIMERState *s)
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{
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2007-12-19 18:58:24 +01:00
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uint64_t count, limit;
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2004-12-20 00:18:01 +01:00
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2007-12-19 18:58:24 +01:00
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if (s->limit == 0) /* free-run processor or system counter */
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limit = TIMER_MAX_COUNT32;
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else
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limit = s->limit;
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2007-12-27 21:23:20 +01:00
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if (s->timer)
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count = limit - PERIODS_TO_LIMIT(ptimer_get_count(s->timer));
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else
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count = 0;
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2007-12-01 16:58:22 +01:00
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DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit,
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s->counthigh, s->count);
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s->count = count & TIMER_COUNT_MASK32;
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2007-05-24 21:48:41 +02:00
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s->counthigh = count >> 32;
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2004-12-20 00:18:01 +01:00
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}
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// timer callback
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static void slavio_timer_irq(void *opaque)
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{
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SLAVIO_TIMERState *s = opaque;
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slavio_timer_get_out(s);
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2007-05-24 21:48:41 +02:00
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DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
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2007-10-07 12:00:55 +02:00
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if (!slavio_timer_is_user(s)) {
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2007-12-01 16:58:22 +01:00
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s->reached = TIMER_REACHED;
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2007-10-06 13:28:21 +02:00
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qemu_irq_raise(s->irq);
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2007-10-07 12:00:55 +02:00
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}
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2004-12-20 00:18:01 +01:00
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}
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static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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SLAVIO_TIMERState *s = opaque;
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2007-05-24 21:48:41 +02:00
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uint32_t saddr, ret;
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2004-12-20 00:18:01 +01:00
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saddr = (addr & TIMER_MAXADDR) >> 2;
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switch (saddr) {
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2007-12-01 16:58:22 +01:00
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case TIMER_LIMIT:
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2007-10-06 13:28:21 +02:00
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// read limit (system counter mode) or read most signifying
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// part of counter (user mode)
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2007-10-07 12:00:55 +02:00
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if (slavio_timer_is_user(s)) {
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// read user timer MSW
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slavio_timer_get_out(s);
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ret = s->counthigh;
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} else {
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// read limit
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2007-10-06 13:28:21 +02:00
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// clear irq
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2007-05-27 18:37:49 +02:00
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qemu_irq_lower(s->irq);
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2007-10-06 13:28:21 +02:00
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s->reached = 0;
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2007-12-01 16:58:22 +01:00
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ret = s->limit & TIMER_LIMIT_MASK32;
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2007-10-06 13:28:21 +02:00
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}
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2007-05-24 21:48:41 +02:00
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break;
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2007-12-01 16:58:22 +01:00
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case TIMER_COUNTER:
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2007-10-06 13:28:21 +02:00
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// read counter and reached bit (system mode) or read lsbits
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// of counter (user mode)
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slavio_timer_get_out(s);
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2007-10-07 12:00:55 +02:00
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if (slavio_timer_is_user(s)) // read user timer LSW
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2007-12-01 16:58:22 +01:00
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ret = s->count & TIMER_COUNT_MASK32;
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2007-10-07 12:00:55 +02:00
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else // read limit
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2007-12-01 16:58:22 +01:00
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ret = (s->count & TIMER_MAX_COUNT32) | s->reached;
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2007-05-24 21:48:41 +02:00
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break;
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2007-12-01 16:58:22 +01:00
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case TIMER_STATUS:
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2007-10-07 12:00:55 +02:00
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// only available in processor counter/timer
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2007-10-06 13:28:21 +02:00
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// read start/stop status
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2007-10-07 12:00:55 +02:00
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ret = s->running;
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2007-05-24 21:48:41 +02:00
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break;
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2007-12-01 16:58:22 +01:00
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case TIMER_MODE:
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2007-10-07 12:00:55 +02:00
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// only available in system counter
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2007-10-06 13:28:21 +02:00
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// read user/system mode
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2007-10-06 13:25:43 +02:00
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ret = s->slave_mode;
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2007-05-24 21:48:41 +02:00
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break;
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2004-12-20 00:18:01 +01:00
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default:
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2007-10-07 12:00:55 +02:00
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DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
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2007-05-24 21:48:41 +02:00
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ret = 0;
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break;
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2004-12-20 00:18:01 +01:00
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}
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2007-05-24 21:48:41 +02:00
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DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
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return ret;
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2004-12-20 00:18:01 +01:00
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}
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2007-12-01 16:58:22 +01:00
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static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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2004-12-20 00:18:01 +01:00
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{
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SLAVIO_TIMERState *s = opaque;
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uint32_t saddr;
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2007-05-24 21:48:41 +02:00
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DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
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2004-12-20 00:18:01 +01:00
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saddr = (addr & TIMER_MAXADDR) >> 2;
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switch (saddr) {
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2007-12-01 16:58:22 +01:00
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case TIMER_LIMIT:
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2007-10-07 12:00:55 +02:00
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if (slavio_timer_is_user(s)) {
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// set user counter MSW, reset counter
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2007-10-06 13:25:43 +02:00
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qemu_irq_lower(s->irq);
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2007-12-01 16:58:22 +01:00
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s->limit = TIMER_MAX_COUNT64;
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2007-10-07 12:00:55 +02:00
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DPRINTF("processor %d user timer reset\n", s->slave_index);
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2007-12-27 21:23:20 +01:00
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if (s->timer)
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ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
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2007-10-07 12:00:55 +02:00
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} else {
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// set limit, reset counter
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qemu_irq_lower(s->irq);
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2007-12-01 16:58:22 +01:00
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s->limit = val & TIMER_MAX_COUNT32;
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2007-12-27 21:23:20 +01:00
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if (s->timer) {
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if (s->limit == 0) /* free-run */
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ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
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else
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ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
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}
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2007-10-06 13:25:43 +02:00
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}
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2007-10-07 12:00:55 +02:00
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break;
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2007-12-01 16:58:22 +01:00
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case TIMER_COUNTER:
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2007-10-07 12:00:55 +02:00
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if (slavio_timer_is_user(s)) {
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// set user counter LSW, reset counter
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qemu_irq_lower(s->irq);
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2007-12-01 16:58:22 +01:00
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s->limit = TIMER_MAX_COUNT64;
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2007-10-07 12:00:55 +02:00
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DPRINTF("processor %d user timer reset\n", s->slave_index);
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2007-12-27 21:23:20 +01:00
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if (s->timer)
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ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
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2007-10-07 12:00:55 +02:00
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} else
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DPRINTF("not user timer\n");
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break;
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2007-12-01 16:58:22 +01:00
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case TIMER_COUNTER_NORST:
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2007-10-06 13:28:21 +02:00
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// set limit without resetting counter
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2007-12-01 16:58:22 +01:00
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s->limit = val & TIMER_MAX_COUNT32;
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2007-12-27 21:23:20 +01:00
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if (s->timer) {
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if (s->limit == 0) /* free-run */
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ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
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else
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ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
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}
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2007-10-06 13:28:21 +02:00
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break;
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2007-12-01 16:58:22 +01:00
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case TIMER_STATUS:
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2007-10-07 12:00:55 +02:00
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if (slavio_timer_is_user(s)) {
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// start/stop user counter
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if ((val & 1) && !s->running) {
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DPRINTF("processor %d user timer started\n", s->slave_index);
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2007-12-27 21:23:20 +01:00
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if (s->timer)
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ptimer_run(s->timer, 0);
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2007-10-07 12:00:55 +02:00
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s->running = 1;
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} else if (!(val & 1) && s->running) {
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DPRINTF("processor %d user timer stopped\n", s->slave_index);
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2007-12-27 21:23:20 +01:00
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if (s->timer)
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ptimer_stop(s->timer);
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2007-10-07 12:00:55 +02:00
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s->running = 0;
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2007-10-06 13:28:21 +02:00
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}
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}
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break;
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2007-12-01 16:58:22 +01:00
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case TIMER_MODE:
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2007-10-07 12:00:55 +02:00
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if (s->master == NULL) {
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2007-10-06 13:25:43 +02:00
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unsigned int i;
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2007-12-17 19:17:17 +01:00
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for (i = 0; i < s->num_slaves; i++) {
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2007-10-06 13:25:43 +02:00
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if (val & (1 << i)) {
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qemu_irq_lower(s->slave[i]->irq);
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s->slave[i]->limit = -1ULL;
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2007-12-29 21:09:57 +01:00
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} else {
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ptimer_stop(s->slave[i]->timer);
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2007-10-06 13:25:43 +02:00
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}
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2007-10-07 12:00:55 +02:00
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if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
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ptimer_stop(s->slave[i]->timer);
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2007-12-01 16:58:22 +01:00
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ptimer_set_limit(s->slave[i]->timer,
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LIMIT_TO_PERIODS(s->slave[i]->limit), 1);
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DPRINTF("processor %d timer changed\n",
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s->slave[i]->slave_index);
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2007-10-07 12:00:55 +02:00
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ptimer_run(s->slave[i]->timer, 0);
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}
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2007-10-06 13:25:43 +02:00
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}
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2007-12-17 19:17:17 +01:00
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s->slave_mode = val & ((1 << s->num_slaves) - 1);
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2007-10-07 12:00:55 +02:00
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} else
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DPRINTF("not system timer\n");
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2004-12-20 00:18:01 +01:00
|
|
|
default:
|
2007-10-07 12:00:55 +02:00
|
|
|
DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2004-12-20 00:18:01 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
|
2008-01-01 18:06:38 +01:00
|
|
|
NULL,
|
|
|
|
NULL,
|
2004-12-20 00:18:01 +01:00
|
|
|
slavio_timer_mem_readl,
|
|
|
|
};
|
|
|
|
|
|
|
|
static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
|
2008-01-01 18:06:38 +01:00
|
|
|
NULL,
|
|
|
|
NULL,
|
2004-12-20 00:18:01 +01:00
|
|
|
slavio_timer_mem_writel,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void slavio_timer_save(QEMUFile *f, void *opaque)
|
|
|
|
{
|
|
|
|
SLAVIO_TIMERState *s = opaque;
|
|
|
|
|
2007-05-24 21:48:41 +02:00
|
|
|
qemu_put_be64s(f, &s->limit);
|
2004-12-20 00:18:01 +01:00
|
|
|
qemu_put_be32s(f, &s->count);
|
|
|
|
qemu_put_be32s(f, &s->counthigh);
|
|
|
|
qemu_put_be32s(f, &s->reached);
|
2007-10-07 12:00:55 +02:00
|
|
|
qemu_put_be32s(f, &s->running);
|
2007-12-27 21:23:20 +01:00
|
|
|
if (s->timer)
|
|
|
|
qemu_put_ptimer(f, s->timer);
|
2004-12-20 00:18:01 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
|
|
|
|
{
|
|
|
|
SLAVIO_TIMERState *s = opaque;
|
2007-09-17 10:09:54 +02:00
|
|
|
|
2007-12-27 21:23:20 +01:00
|
|
|
if (version_id != 3)
|
2004-12-20 00:18:01 +01:00
|
|
|
return -EINVAL;
|
|
|
|
|
2007-05-24 21:48:41 +02:00
|
|
|
qemu_get_be64s(f, &s->limit);
|
2004-12-20 00:18:01 +01:00
|
|
|
qemu_get_be32s(f, &s->count);
|
|
|
|
qemu_get_be32s(f, &s->counthigh);
|
|
|
|
qemu_get_be32s(f, &s->reached);
|
2007-10-07 12:00:55 +02:00
|
|
|
qemu_get_be32s(f, &s->running);
|
2007-12-27 21:23:20 +01:00
|
|
|
if (s->timer)
|
|
|
|
qemu_get_ptimer(f, s->timer);
|
2007-05-24 21:48:41 +02:00
|
|
|
|
2004-12-20 00:18:01 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void slavio_timer_reset(void *opaque)
|
|
|
|
{
|
|
|
|
SLAVIO_TIMERState *s = opaque;
|
|
|
|
|
2007-12-19 18:59:31 +01:00
|
|
|
s->limit = 0;
|
2004-12-20 00:18:01 +01:00
|
|
|
s->count = 0;
|
|
|
|
s->reached = 0;
|
2007-12-19 18:59:31 +01:00
|
|
|
s->slave_mode = 0;
|
2007-12-27 21:23:20 +01:00
|
|
|
if (!s->master || s->slave_index < s->master->num_slaves) {
|
|
|
|
ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
|
|
|
|
ptimer_run(s->timer, 0);
|
|
|
|
}
|
2007-10-07 12:00:55 +02:00
|
|
|
s->running = 1;
|
2007-05-27 18:37:49 +02:00
|
|
|
qemu_irq_lower(s->irq);
|
2004-12-20 00:18:01 +01:00
|
|
|
}
|
|
|
|
|
2007-10-06 13:25:43 +02:00
|
|
|
static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
|
2007-10-07 12:00:55 +02:00
|
|
|
qemu_irq irq,
|
|
|
|
SLAVIO_TIMERState *master,
|
|
|
|
int slave_index)
|
2004-12-20 00:18:01 +01:00
|
|
|
{
|
|
|
|
int slavio_timer_io_memory;
|
|
|
|
SLAVIO_TIMERState *s;
|
2007-05-24 21:48:41 +02:00
|
|
|
QEMUBH *bh;
|
2004-12-20 00:18:01 +01:00
|
|
|
|
|
|
|
s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
|
|
|
|
if (!s)
|
2007-10-06 13:25:43 +02:00
|
|
|
return s;
|
2004-12-20 00:18:01 +01:00
|
|
|
s->irq = irq;
|
2007-10-07 12:00:55 +02:00
|
|
|
s->master = master;
|
|
|
|
s->slave_index = slave_index;
|
2007-12-27 21:23:20 +01:00
|
|
|
if (!master || slave_index < master->num_slaves) {
|
|
|
|
bh = qemu_bh_new(slavio_timer_irq, s);
|
|
|
|
s->timer = ptimer_init(bh);
|
|
|
|
ptimer_set_period(s->timer, TIMER_PERIOD);
|
|
|
|
}
|
2004-12-20 00:18:01 +01:00
|
|
|
|
|
|
|
slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
|
2007-10-06 13:28:21 +02:00
|
|
|
slavio_timer_mem_write, s);
|
2007-10-07 12:00:55 +02:00
|
|
|
if (master)
|
2007-12-01 16:58:22 +01:00
|
|
|
cpu_register_physical_memory(addr, CPU_TIMER_SIZE,
|
|
|
|
slavio_timer_io_memory);
|
2007-10-06 13:25:43 +02:00
|
|
|
else
|
2007-12-01 16:58:22 +01:00
|
|
|
cpu_register_physical_memory(addr, SYS_TIMER_SIZE,
|
|
|
|
slavio_timer_io_memory);
|
2007-12-27 21:23:20 +01:00
|
|
|
register_savevm("slavio_timer", addr, 3, slavio_timer_save,
|
2007-12-01 16:58:22 +01:00
|
|
|
slavio_timer_load, s);
|
2004-12-20 00:18:01 +01:00
|
|
|
qemu_register_reset(slavio_timer_reset, s);
|
|
|
|
slavio_timer_reset(s);
|
2007-10-06 13:25:43 +02:00
|
|
|
|
|
|
|
return s;
|
|
|
|
}
|
|
|
|
|
|
|
|
void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
|
2007-12-17 19:17:17 +01:00
|
|
|
qemu_irq *cpu_irqs, unsigned int num_cpus)
|
2007-10-06 13:25:43 +02:00
|
|
|
{
|
|
|
|
SLAVIO_TIMERState *master;
|
|
|
|
unsigned int i;
|
|
|
|
|
2007-12-01 16:58:22 +01:00
|
|
|
master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0);
|
2007-10-06 13:25:43 +02:00
|
|
|
|
2007-12-17 19:17:17 +01:00
|
|
|
master->num_slaves = num_cpus;
|
|
|
|
|
2007-10-06 13:25:43 +02:00
|
|
|
for (i = 0; i < MAX_CPUS; i++) {
|
|
|
|
master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
|
2007-12-01 16:58:22 +01:00
|
|
|
CPU_TIMER_OFFSET(i),
|
2007-10-07 12:00:55 +02:00
|
|
|
cpu_irqs[i], master, i);
|
2007-10-06 13:25:43 +02:00
|
|
|
}
|
2004-12-20 00:18:01 +01:00
|
|
|
}
|