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qemu-e2k/hw/riscv/opentitan.c

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riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
/*
* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
*
* Copyright (c) 2020 Western Digital
*
* Provides a board compatible with the OpenTitan FPGA platform:
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-20 03:41:08 +02:00
#include "qemu/cutils.h"
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
#include "hw/riscv/opentitan.h"
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
riscv/opentitan: Fix the ROM size Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reported-by: Damien Hedde <damien.hedde@greensocs.com>
2020-06-10 01:08:29 +02:00
#include "qemu/units.h"
riscv/opentitan: Connect the PLIC device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-24 03:40:57 +02:00
#include "sysemu/sysemu.h"
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
hw/riscv/opentitan: bump opentitan This patch updates the OpenTitan model to match the specified register layout as per [1]. Which is also the latest commit of OpenTitan supported by TockOS. Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes any references to Padctrl. Note: OpenTitan doc [2] has not yet specified much detail regarding this, except for a note that states `TODO: this section needs to be updated to reflect the pinmux/padctrl merger` [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20221025043335.339815-2-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-10-25 06:33:36 +02:00
/*
* This version of the OpenTitan machine currently supports
* OpenTitan RTL version:
include/hw/riscv/opentitan: update opentitan IRQs Updates the opentitan IRQs to match the latest supported commit of Opentitan from TockOS. OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47 Memory layout as per [1] [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-23 07:36:21 +01:00
* <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
hw/riscv/opentitan: bump opentitan This patch updates the OpenTitan model to match the specified register layout as per [1]. Which is also the latest commit of OpenTitan supported by TockOS. Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes any references to Padctrl. Note: OpenTitan doc [2] has not yet specified much detail regarding this, except for a note that states `TODO: this section needs to be updated to reflect the pinmux/padctrl merger` [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/ [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20221025043335.339815-2-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-10-25 06:33:36 +02:00
*
* MMIO mapping as per (specified commit):
* lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
*/
hw/riscv: Drop 'struct MemmapEntry' There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210220144807.819-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-02-20 15:48:04 +01:00
static const MemMapEntry ibex_memmap[] = {
include/hw/riscv/opentitan: update opentitan IRQs Updates the opentitan IRQs to match the latest supported commit of Opentitan from TockOS. OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47 Memory layout as per [1] [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-23 07:36:21 +01:00
[IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
[IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
[IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
[IBEX_DEV_UART] = { 0x40000000, 0x40 },
[IBEX_DEV_GPIO] = { 0x40040000, 0x40 },
[IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 },
[IBEX_DEV_I2C] = { 0x40080000, 0x80 },
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 },
[IBEX_DEV_TIMER] = { 0x40100000, 0x200 },
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 },
[IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 },
[IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 },
[IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 },
[IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 },
[IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 },
[IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 },
[IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 },
[IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
[IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 },
[IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 },
[IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 },
[IBEX_DEV_AES] = { 0x41100000, 0x100 },
[IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
[IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
[IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
[IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 },
[IBEX_DEV_CSRNG] = { 0x41150000, 0x80 },
[IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 },
[IBEX_DEV_EDNO] = { 0x41170000, 0x80 },
[IBEX_DEV_EDN1] = { 0x41180000, 0x80 },
[IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 },
[IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 },
[IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 },
[IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
};
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
static void opentitan_board_init(MachineState *machine)
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
{
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-20 03:41:08 +02:00
MachineClass *mc = MACHINE_GET_CLASS(machine);
hw/riscv: Drop 'struct MemmapEntry' There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210220144807.819-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-02-20 15:48:04 +01:00
const MemMapEntry *memmap = ibex_memmap;
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
OpenTitanState *s = g_new0(OpenTitanState, 1);
MemoryRegion *sys_mem = get_system_memory();
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-20 03:41:08 +02:00
if (machine->ram_size != mc->default_ram_size) {
char *sz = size_to_str(mc->default_ram_size);
error_report("Invalid RAM size, should be %s", sz);
g_free(sz);
exit(EXIT_FAILURE);
}
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
qom: Less verbose object_initialize_child() All users of object_initialize_child() pass the obvious child size argument. Almost all pass &error_abort and no properties. Tiresome. Rename object_initialize_child() to object_initialize_child_with_props() to free the name. New convenience wrapper object_initialize_child() automates the size argument, and passes &error_abort and no properties. Rename object_initialize_childv() to object_initialize_child_with_propsv() for consistency. Convert callers with this Coccinelle script: @@ expression parent, propname, type; expression child, size; symbol error_abort; @@ - object_initialize_child(parent, propname, OBJECT(child), size, type, &error_abort, NULL) + object_initialize_child(parent, propname, child, size, type, &error_abort, NULL) @@ expression parent, propname, type; expression child; symbol error_abort; @@ - object_initialize_child(parent, propname, child, sizeof(*child), type, &error_abort, NULL) + object_initialize_child(parent, propname, child, type) @@ expression parent, propname, type; expression child; symbol error_abort; @@ - object_initialize_child(parent, propname, &child, sizeof(child), type, &error_abort, NULL) + object_initialize_child(parent, propname, &child, type) @@ expression parent, propname, type; expression child, size, err; expression list props; @@ - object_initialize_child(parent, propname, child, size, type, err, props) + object_initialize_child_with_props(parent, propname, child, size, type, err, props) Note that Coccinelle chokes on ARMSSE typedef vs. macro in hw/arm/armsse.c. Worked around by temporarily renaming the macro for the spatch run. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> [Rebased: machine opentitan is new (commit fe0fe4735e7)] Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-37-armbru@redhat.com>
2020-06-10 07:32:25 +02:00
TYPE_RISCV_IBEX_SOC);
hw/riscv: Use error_fatal for SoC realisation When realising the SoC use error_fatal instead of error_abort as the process can fail and report useful information to the user. Currently a user can see this: $ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display none -drive if=pflash QEMU 6.1.93 monitor - type 'help' for more information (qemu) Unexpected error in sifive_u_otp_realize() at ../hw/misc/sifive_u_otp.c:229: qemu-system-riscv64: OTP drive size < 16K Aborted (core dumped) Which this patch addresses Reported-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220105213937.1113508-8-alistair.francis@opensource.wdc.com>
2022-01-05 22:39:36 +01:00
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
memory_region_add_subregion(sys_mem,
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-20 03:41:08 +02:00
memmap[IBEX_DEV_RAM].base, machine->ram);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
if (machine->firmware) {
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
}
if (machine->kernel_filename) {
hw/riscv/boot.c: use MachineState in riscv_load_kernel() All callers are using kernel_filename as machine->kernel_filename. This will also simplify the changes in riscv_load_kernel() that we're going to do next. Cc: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230102115241.25733-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-02 12:52:39 +01:00
riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
}
}
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
static void opentitan_machine_init(MachineClass *mc)
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
{
mc->desc = "RISC-V Board compatible with OpenTitan";
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
mc->init = opentitan_board_init;
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
mc->max_cpus = 1;
mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-20 03:41:08 +02:00
mc->default_ram_id = "riscv.lowrisc.ibex.ram";
mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
}
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
DEFINE_MACHINE("opentitan", opentitan_machine_init)
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
static void lowrisc_ibex_soc_init(Object *obj)
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
{
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2 This is the same transformation as in the previous commit, except sysbus_init_child_obj() and realize are too separated for the commit's Coccinelle script to handle, typically because sysbus_init_child_obj() is in a device's instance_init() method, and the matching realize is in its realize() method. Perhaps a Coccinelle wizard could make it transform that pattern, but I'm just a bungler, and the best I can do is transforming the two separate parts separately: @@ expression errp; expression child; symbol true; @@ - object_property_set_bool(OBJECT(child), true, "realized", errp); + sysbus_realize(SYS_BUS_DEVICE(child), errp); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression errp; expression child; symbol true; @@ - object_property_set_bool(child, true, "realized", errp); + sysbus_realize(SYS_BUS_DEVICE(child), errp); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; @@ - qdev_init_nofail(DEVICE(child)); + sysbus_realize(SYS_BUS_DEVICE(child), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; expression dev; @@ dev = DEVICE(child); ... - qdev_init_nofail(dev); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression child; identifier dev; @@ DeviceState *dev = DEVICE(child); ... - qdev_init_nofail(dev); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); // only correct with a matching sysbus_init_child_obj() transformation! @@ expression parent, name, size, type; expression child; symbol true; @@ - sysbus_init_child_obj(parent, name, child, size, type); + sysbus_init_child_XXX(parent, name, child, size, type); @@ expression parent, propname, type; expression child; @@ - sysbus_init_child_XXX(parent, propname, child, sizeof(*child), type) + object_initialize_child(parent, propname, child, type) @@ expression parent, propname, type; expression child; @@ - sysbus_init_child_XXX(parent, propname, &child, sizeof(child), type) + object_initialize_child(parent, propname, &child, type) This script is *unsound*: we need to manually verify init and realize conversions are properly paired. This commit has only the pairs where object_initialize_child()'s @child and sysbus_realize()'s @dev argument text match exactly within the same source file. Note that Coccinelle chokes on ARMSSE typedef vs. macro in hw/arm/armsse.c. Worked around by temporarily renaming the macro for the spatch run. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-49-armbru@redhat.com>
2020-06-10 07:32:37 +02:00
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
riscv/opentitan: Connect the PLIC device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-24 03:40:57 +02:00
hw/riscv: opentitan: Update to the latest build Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
2021-10-18 04:38:39 +02:00
object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-23 23:08:45 +02:00
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Connect the Ibex timer to the OpenTitan machine. The timer can trigger the RISC-V MIE interrupt as well as a custom device interrupt. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
2021-06-18 09:28:01 +02:00
object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
riscv: opentitan: Connect opentitan SPI Host Connect spi host[1/0] to opentitan. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03 05:54:26 +01:00
for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
TYPE_IBEX_SPI_HOST);
}
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
}
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
{
hw/riscv: Drop 'struct MemmapEntry' There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210220144807.819-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-02-20 15:48:04 +01:00
const MemMapEntry *memmap = ibex_memmap;
riscv: opentitan: Connect opentitan SPI Host Connect spi host[1/0] to opentitan. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03 05:54:26 +01:00
DeviceState *dev;
SysBusDevice *busdev;
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
MachineState *ms = MACHINE(qdev_get_machine());
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
MemoryRegion *sys_mem = get_system_memory();
hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 0a76946981852f5bd15f0c37ab35b253371027a8.1630301632.git.alistair.francis@wdc.com
2021-08-30 07:34:49 +02:00
int i;
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
qom: Put name parameter before value / visitor parameter The object_property_set_FOO() setters take property name and value in an unusual order: void object_property_set_FOO(Object *obj, FOO_TYPE value, const char *name, Error **errp) Having to pass value before name feels grating. Swap them. Same for object_property_set(), object_property_get(), and object_property_parse(). Convert callers with this Coccinelle script: @@ identifier fun = { object_property_get, object_property_parse, object_property_set_str, object_property_set_link, object_property_set_bool, object_property_set_int, object_property_set_uint, object_property_set, object_property_set_qobject }; expression obj, v, name, errp; @@ - fun(obj, v, name, errp) + fun(obj, name, v, errp) Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error message "no position information". Convert that one manually. Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Convert manually. Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused by RXCPU being used both as typedef and function-like macro there. Convert manually. The other files using RXCPU that way don't need conversion. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20200707160613.848843-27-armbru@redhat.com> [Straightforwad conflict with commit 2336172d9b "audio: set default value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
&error_abort);
qom: Put name parameter before value / visitor parameter The object_property_set_FOO() setters take property name and value in an unusual order: void object_property_set_FOO(Object *obj, FOO_TYPE value, const char *name, Error **errp) Having to pass value before name feels grating. Swap them. Same for object_property_set(), object_property_get(), and object_property_parse(). Convert callers with this Coccinelle script: @@ identifier fun = { object_property_get, object_property_parse, object_property_set_str, object_property_set_link, object_property_set_bool, object_property_set_int, object_property_set_uint, object_property_set, object_property_set_qobject }; expression obj, v, name, errp; @@ - fun(obj, v, name, errp) + fun(obj, name, v, errp) Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error message "no position information". Convert that one manually. Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Convert manually. Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused by RXCPU being used both as typedef and function-like macro there. Convert manually. The other files using RXCPU that way don't need conversion. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20200707160613.848843-27-armbru@redhat.com> [Straightforwad conflict with commit 2336172d9b "audio: set default value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
&error_abort);
hw/riscv: opentitan: Expose the resetvec as a SoC property On the OpenTitan hardware the resetvec is fixed at the start of ROM. In QEMU we don't run the ROM code and instead just jump to the next stage. This means we need to be a little more flexible about what the resetvec is. This patch allows us to set the resetvec from the command line with something like this: -global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400 This way as the next stage changes we can update the resetvec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220914101108.82571-4-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-14 12:11:08 +02:00
object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
hw/riscv: opentitan: bump opentitan version The following patch updates opentitan to match the new configuration, as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c Note: with this patch we now skip the usage of the opentitan `boot_rom`. The Opentitan boot rom contains hw verification for devies which we are currently not supporting in qemu. As of now, the `boot_rom` has no major significance, however, would be good to support in the future. Tested by running utests from the latest tock [1] (that supports this version of OT). [1] https://github.com/tock/tock/pull/3056 Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220812005229.358850-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-08-12 02:52:30 +02:00
&error_abort);
hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan) If specified CPU configuration is not valid, not just it prints error message, it aborts and generates core dumps (depends on the operating system). This kind of error handling should be used only when a serious runtime error occurs. This commit makes error handling on CPU configuration more generous on sifive_e/u and opentitan machines. It now just prints error message and quits (without coredumps and aborts). This is separate from spike/virt because it involves different type (TYPE_RISCV_HART_ARRAY) on sifive_e/u and opentitan machines. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <09e61e58a7543da44bdb0e0f5368afc8903b4aa6.1652509778.git.research_trasio@irq.a4lg.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-05-14 08:29:41 +02:00
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
/* Boot ROM */
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_ROM].size, &error_fatal);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
memory_region_add_subregion(sys_mem,
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_ROM].base, &s->rom);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
/* Flash memory */
memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_FLASH].size, &error_fatal);
hw/riscv: opentitan: Add the flash alias OpenTitan has an alias of flash avaliable which is called virtual flash. Add support for that in the QEMU model. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com
2021-07-09 05:38:48 +02:00
memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
"riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
memmap[IBEX_DEV_FLASH_VIRTUAL].size);
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
&s->flash_mem);
hw/riscv: opentitan: Add the flash alias OpenTitan has an alias of flash avaliable which is called virtual flash. Add support for that in the QEMU model. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: c9cfbd2dd840fd0076877b8ea4d6dcfce60db5e9.1625801868.git.alistair.francis@wdc.com
2021-07-09 05:38:48 +02:00
memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
&s->flash_alias);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
riscv/opentitan: Connect the PLIC device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-24 03:40:57 +02:00
/* PLIC */
hw/riscv: opentitan: Update to the latest build Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
2021-10-18 04:38:39 +02:00
qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
riscv: opentitan: fixup plic stride len The following change was made to rectify incorrectly set stride length on the PLIC [1]. Where it should be 32bit and not 24bit (0x18). This was discovered whilst attempting to fix a bug where a timer_interrupt was not serviced on TockOS-OpenTitan. [1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/ Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20220111071025.4169189-1-alistair.francis@opensource.wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-11 08:10:24 +01:00
qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
hw/riscv: opentitan: Fixup the PLIC context addresses Fixup the PLIC context address to correctly support the threshold and claim register. Fixes: ef63100648 ("hw/riscv: opentitan: Update to the latest build") Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211025040657.262696-1-alistair.francis@opensource.wdc.com
2021-10-25 06:06:57 +02:00
qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
hw/riscv: opentitan: Update to the latest build Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
2021-10-18 04:38:39 +02:00
qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
error: Eliminate error_propagate() with Coccinelle, part 1 When all we do with an Error we receive into a local variable is propagating to somewhere else, we can just as well receive it there right away. Convert if (!foo(..., &err)) { ... error_propagate(errp, err); ... return ... } to if (!foo(..., errp)) { ... ... return ... } where nothing else needs @err. Coccinelle script: @rule1 forall@ identifier fun, err, errp, lbl; expression list args, args2; binary operator op; constant c1, c2; symbol false; @@ if ( ( - fun(args, &err, args2) + fun(args, errp, args2) | - !fun(args, &err, args2) + !fun(args, errp, args2) | - fun(args, &err, args2) op c1 + fun(args, errp, args2) op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; ) } @rule2 forall@ identifier fun, err, errp, lbl; expression list args, args2; expression var; binary operator op; constant c1, c2; symbol false; @@ - var = fun(args, &err, args2); + var = fun(args, errp, args2); ... when != err if ( ( var | !var | var op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; | return var; ) } @depends on rule1 || rule2@ identifier err; @@ - Error *err = NULL; ... when != err Not exactly elegant, I'm afraid. The "when != lbl:" is necessary to avoid transforming if (fun(args, &err)) { goto out } ... out: error_propagate(errp, err); even though other paths to label out still need the error_propagate(). For an actual example, see sclp_realize(). Without the "when strict", Coccinelle transforms vfio_msix_setup(), incorrectly. I don't know what exactly "when strict" does, only that it helps here. The match of return is narrower than what I want, but I can't figure out how to express "return where the operand doesn't use @err". For an example where it's too narrow, see vfio_intx_enable(). Silently fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Converted manually. Line breaks tidied up manually. One nested declaration of @local_err deleted manually. Preexisting unwanted blank line dropped in hw/riscv/sifive_e.c. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20200707160613.848843-35-armbru@redhat.com>
2020-07-07 18:06:02 +02:00
if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
riscv/opentitan: Connect the PLIC device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-24 03:40:57 +02:00
return;
}
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
riscv/opentitan: Connect the PLIC device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-24 03:40:57 +02:00
hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 0a76946981852f5bd15f0c37ab35b253371027a8.1630301632.git.alistair.francis@wdc.com
2021-08-30 07:34:49 +02:00
for (i = 0; i < ms->smp.cpus; i++) {
CPUState *cpu = qemu_get_cpu(i);
hw/riscv: opentitan: Update to the latest build Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
2021-10-18 04:38:39 +02:00
qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the external MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 0a76946981852f5bd15f0c37ab35b253371027a8.1630301632.git.alistair.francis@wdc.com
2021-08-30 07:34:49 +02:00
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
}
riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-23 23:08:45 +02:00
/* UART */
qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
error: Eliminate error_propagate() with Coccinelle, part 1 When all we do with an Error we receive into a local variable is propagating to somewhere else, we can just as well receive it there right away. Convert if (!foo(..., &err)) { ... error_propagate(errp, err); ... return ... } to if (!foo(..., errp)) { ... ... return ... } where nothing else needs @err. Coccinelle script: @rule1 forall@ identifier fun, err, errp, lbl; expression list args, args2; binary operator op; constant c1, c2; symbol false; @@ if ( ( - fun(args, &err, args2) + fun(args, errp, args2) | - !fun(args, &err, args2) + !fun(args, errp, args2) | - fun(args, &err, args2) op c1 + fun(args, errp, args2) op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; ) } @rule2 forall@ identifier fun, err, errp, lbl; expression list args, args2; expression var; binary operator op; constant c1, c2; symbol false; @@ - var = fun(args, &err, args2); + var = fun(args, errp, args2); ... when != err if ( ( var | !var | var op c1 ) ) { ... when != err when != lbl: when strict - error_propagate(errp, err); ... when != err ( return; | return c2; | return false; | return var; ) } @depends on rule1 || rule2@ identifier err; @@ - Error *err = NULL; ... when != err Not exactly elegant, I'm afraid. The "when != lbl:" is necessary to avoid transforming if (fun(args, &err)) { goto out } ... out: error_propagate(errp, err); even though other paths to label out still need the error_propagate(). For an actual example, see sclp_realize(). Without the "when strict", Coccinelle transforms vfio_msix_setup(), incorrectly. I don't know what exactly "when strict" does, only that it helps here. The match of return is narrower than what I want, but I can't figure out how to express "return where the operand doesn't use @err". For an example where it's too narrow, see vfio_intx_enable(). Silently fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Converted manually. Line breaks tidied up manually. One nested declaration of @local_err deleted manually. Preexisting unwanted blank line dropped in hw/riscv/sifive_e.c. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20200707160613.848843-35-armbru@redhat.com>
2020-07-07 18:06:02 +02:00
if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-23 23:08:45 +02:00
return;
}
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-23 23:08:45 +02:00
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
0, qdev_get_gpio_in(DEVICE(&s->plic),
hw/opentitan: Update the interrupt layout Update the OpenTitan interrupt layout to match the latest OpenTitan bitstreams. This involves changing the Ibex PLIC memory layout and the UART interrupts. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
2021-03-31 17:00:11 +02:00
IBEX_UART0_TX_WATERMARK_IRQ));
riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-23 23:08:45 +02:00
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
1, qdev_get_gpio_in(DEVICE(&s->plic),
hw/opentitan: Update the interrupt layout Update the OpenTitan interrupt layout to match the latest OpenTitan bitstreams. This involves changing the Ibex PLIC memory layout and the UART interrupts. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
2021-03-31 17:00:11 +02:00
IBEX_UART0_RX_WATERMARK_IRQ));
riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-23 23:08:45 +02:00
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
2, qdev_get_gpio_in(DEVICE(&s->plic),
hw/opentitan: Update the interrupt layout Update the OpenTitan interrupt layout to match the latest OpenTitan bitstreams. This involves changing the Ibex PLIC memory layout and the UART interrupts. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
2021-03-31 17:00:11 +02:00
IBEX_UART0_TX_EMPTY_IRQ));
riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-23 23:08:45 +02:00
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
3, qdev_get_gpio_in(DEVICE(&s->plic),
hw/opentitan: Update the interrupt layout Update the OpenTitan interrupt layout to match the latest OpenTitan bitstreams. This involves changing the Ibex PLIC memory layout and the UART interrupts. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
2021-03-31 17:00:11 +02:00
IBEX_UART0_RX_OVERFLOW_IRQ));
riscv/opentitan: Connect the UART device Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-04-23 23:08:45 +02:00
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Connect the Ibex timer to the OpenTitan machine. The timer can trigger the RISC-V MIE interrupt as well as a custom device interrupt. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
2021-06-18 09:28:01 +02:00
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_TIMER_TIMEREXPIRED0_0));
hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines Instead of using riscv_cpu_update_mip() let's instead use the new RISC-V CPU GPIO lines to set the timer MIP bits. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 84d5b1d5783d2e79eee69a2f7ac480cc0c070db3.1630301632.git.alistair.francis@wdc.com
2021-08-30 07:35:15 +02:00
qdev_connect_gpio_out(DEVICE(&s->timer), 0,
qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
IRQ_M_TIMER));
hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer Connect the Ibex timer to the OpenTitan machine. The timer can trigger the RISC-V MIE interrupt as well as a custom device interrupt. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
2021-06-18 09:28:01 +02:00
riscv: opentitan: Connect opentitan SPI Host Connect spi host[1/0] to opentitan. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-03 05:54:26 +01:00
/* SPI-Hosts */
for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
dev = DEVICE(&(s->spi_host[i]));
if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {
return;
}
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
switch (i) {
case OPENTITAN_SPI_HOST0:
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_SPI_HOST0_ERR_IRQ));
sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_SPI_HOST0_SPI_EVENT_IRQ));
break;
case OPENTITAN_SPI_HOST1:
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_SPI_HOST1_ERR_IRQ));
sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_SPI_HOST1_SPI_EVENT_IRQ));
break;
}
}
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
hw: riscv: opentitan: fixup SPI addresses This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1 base addresses. Also adds these as unimplemented devices. The address references can be found [1]. [1] https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107 Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-18 07:38:39 +01:00
create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
riscv/opentitan: Update the OpenTitan memory layout OpenTitan is currently only avalible on an FPGA platform and the memory addresses have changed. Update to use the new memory addresses. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
2020-12-15 02:56:54 +01:00
create_unimplemented_device("riscv.lowrisc.ibex.i2c",
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
hw/riscv: opentitan: bump opentitan version The following patch updates opentitan to match the new configuration, as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c Note: with this patch we now skip the usage of the opentitan `boot_rom`. The Opentitan boot rom contains hw verification for devies which we are currently not supporting in qemu. As of now, the `boot_rom` has no major significance, however, would be good to support in the future. Tested by running utests from the latest tock [1] (that supports this version of OT). [1] https://github.com/tock/tock/pull/3056 Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220812005229.358850-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-08-12 02:52:30 +02:00
create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl",
memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
riscv/opentitan: Update the OpenTitan memory layout OpenTitan is currently only avalible on an FPGA platform and the memory addresses have changed. Update to use the new memory addresses. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
2020-12-15 02:56:54 +01:00
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
hw/riscv/opentitan: add aon_timer base unimpl Adds the updated `aon_timer` base as an unimplemented device. This is used by TockOS, patch ensures the guest doesn't hit load faults. Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221025043335.339815-3-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-10-25 06:33:37 +02:00
create_unimplemented_device("riscv.lowrisc.ibex.aon_timer",
memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);
riscv/opentitan: Update the OpenTitan memory layout OpenTitan is currently only avalible on an FPGA platform and the memory addresses have changed. Update to use the new memory addresses. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
2020-12-15 02:56:54 +01:00
create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
create_unimplemented_device("riscv.lowrisc.ibex.aes",
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
create_unimplemented_device("riscv.lowrisc.ibex.hmac",
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
riscv/opentitan: Update the OpenTitan memory layout OpenTitan is currently only avalible on an FPGA platform and the memory addresses have changed. Update to use the new memory addresses. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
2020-12-15 02:56:54 +01:00
create_unimplemented_device("riscv.lowrisc.ibex.kmac",
memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
create_unimplemented_device("riscv.lowrisc.ibex.csrng",
memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
create_unimplemented_device("riscv.lowrisc.ibex.entropy",
memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
create_unimplemented_device("riscv.lowrisc.ibex.edn0",
memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
create_unimplemented_device("riscv.lowrisc.ibex.edn1",
memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
opentitan: Rename memmap enum constants Some of the enum constant names conflict with the QOM type check macros (IBEX_PLIC, IBEX_UART). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to IBEX_DEV_*, to avoid conflicts. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Tested-By: Roman Bolshakov <r.bolshakov@yadro.com> Message-Id: <20200825192110.3528606-8-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-08-25 21:20:03 +02:00
memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
include/hw/riscv/opentitan: update opentitan IRQs Updates the opentitan IRQs to match the latest supported commit of Opentitan from TockOS. OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47 Memory layout as per [1] [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-23 07:36:21 +01:00
create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
riscv/opentitan: Update the OpenTitan memory layout OpenTitan is currently only avalible on an FPGA platform and the memory addresses have changed. Update to use the new memory addresses. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 8eb65314830a75d0fea3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
2020-12-15 02:56:54 +01:00
create_unimplemented_device("riscv.lowrisc.ibex.otbn",
memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
include/hw/riscv/opentitan: update opentitan IRQs Updates the opentitan IRQs to match the latest supported commit of Opentitan from TockOS. OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47 Memory layout as per [1] [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-23 07:36:21 +01:00
create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
}
hw/riscv: opentitan: Expose the resetvec as a SoC property On the OpenTitan hardware the resetvec is fixed at the start of ROM. In QEMU we don't run the ROM code and instead just jump to the next stage. This means we need to be a little more flexible about what the resetvec is. This patch allows us to set the resetvec from the command line with something like this: -global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400 This way as the next stage changes we can update the resetvec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220914101108.82571-4-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-14 12:11:08 +02:00
static Property lowrisc_ibex_soc_props[] = {
DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),
DEFINE_PROP_END_OF_LIST()
};
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
{
DeviceClass *dc = DEVICE_CLASS(oc);
hw/riscv: opentitan: Expose the resetvec as a SoC property On the OpenTitan hardware the resetvec is fixed at the start of ROM. In QEMU we don't run the ROM code and instead just jump to the next stage. This means we need to be a little more flexible about what the resetvec is. This patch allows us to set the resetvec from the command line with something like this: -global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400 This way as the next stage changes we can update the resetvec. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220914101108.82571-4-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-14 12:11:08 +02:00
device_class_set_props(dc, lowrisc_ibex_soc_props);
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
dc->realize = lowrisc_ibex_soc_realize;
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
}
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
static const TypeInfo lowrisc_ibex_soc_type_info = {
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
.name = TYPE_RISCV_IBEX_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(LowRISCIbexSoCState),
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
.instance_init = lowrisc_ibex_soc_init,
.class_init = lowrisc_ibex_soc_class_init,
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
};
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
static void lowrisc_ibex_soc_register_types(void)
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
{
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
type_register_static(&lowrisc_ibex_soc_type_info);
riscv: Initial commit of OpenTitan machine This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-04-23 20:30:50 +02:00
}
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-08 16:17:31 +02:00
type_init(lowrisc_ibex_soc_register_types)
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