368 lines
10 KiB
C
368 lines
10 KiB
C
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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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//#define DEBUG_PCI
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typedef struct PCIBridge {
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uint32_t config_reg;
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PCIDevice **pci_bus[256];
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} PCIBridge;
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static PCIBridge pci_bridge;
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target_phys_addr_t pci_mem_base;
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/* -1 for devfn means auto assign */
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PCIDevice *pci_register_device(const char *name, int instance_size,
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int bus_num, int devfn,
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PCIConfigReadFunc *config_read,
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PCIConfigWriteFunc *config_write)
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{
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PCIBridge *s = &pci_bridge;
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PCIDevice *pci_dev, **bus;
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if (!s->pci_bus[bus_num]) {
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s->pci_bus[bus_num] = qemu_mallocz(256 * sizeof(PCIDevice *));
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if (!s->pci_bus[bus_num])
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return NULL;
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}
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bus = s->pci_bus[bus_num];
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if (devfn < 0) {
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for(devfn = 0 ; devfn < 256; devfn += 8) {
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if (!bus[devfn])
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goto found;
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}
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return NULL;
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found: ;
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}
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pci_dev = qemu_mallocz(instance_size);
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if (!pci_dev)
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return NULL;
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pci_dev->bus_num = bus_num;
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pci_dev->devfn = devfn;
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pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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pci_dev->config_read = config_read;
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pci_dev->config_write = config_write;
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bus[devfn] = pci_dev;
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return pci_dev;
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}
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void pci_register_io_region(PCIDevice *pci_dev, int region_num,
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func)
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{
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PCIIORegion *r;
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if ((unsigned int)region_num >= 6)
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return;
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r = &pci_dev->io_regions[region_num];
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r->addr = -1;
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r->size = size;
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r->type = type;
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r->map_func = map_func;
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}
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static void pci_config_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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PCIBridge *s = opaque;
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s->config_reg = val;
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}
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static uint32_t pci_config_readl(void* opaque, uint32_t addr)
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{
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PCIBridge *s = opaque;
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return s->config_reg;
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}
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static void unmap_region(PCIIORegion *r)
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{
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if (r->addr == -1)
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return;
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#ifdef DEBUG_PCI
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printf("unmap addr=%08x size=%08x\n", r->addr, r->size);
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#endif
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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isa_unassign_ioport(r->addr, r->size);
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} else {
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cpu_register_physical_memory(r->addr + pci_mem_base, r->size,
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IO_MEM_UNASSIGNED);
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}
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}
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static void pci_data_write(void *opaque, uint32_t addr,
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uint32_t val, int len)
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{
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PCIBridge *s = opaque;
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PCIDevice **bus, *pci_dev;
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int config_addr, reg;
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#if defined(DEBUG_PCI) && 0
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printf("pci_data_write: addr=%08x val=%08x len=%d\n",
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s->config_reg, val, len);
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#endif
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if (!(s->config_reg & (1 << 31))) {
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return;
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}
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if ((s->config_reg & 0x3) != 0) {
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return;
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}
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bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
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if (!bus)
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return;
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pci_dev = bus[(s->config_reg >> 8) & 0xff];
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if (!pci_dev)
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return;
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config_addr = (s->config_reg & 0xfc) | (addr & 3);
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#if defined(DEBUG_PCI)
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printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
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pci_dev->name, config_addr, val, len);
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#endif
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if (len == 4 && (config_addr >= 0x10 && config_addr < 0x10 + 4 * 6)) {
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PCIIORegion *r;
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reg = (config_addr - 0x10) >> 2;
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r = &pci_dev->io_regions[reg];
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if (r->size == 0)
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goto default_config;
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if (val != 0xffffffff && val != 0) {
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/* XXX: the memory assignment should be global to handle
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overlaps, but it is not needed at this stage */
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/* first unmap the old region */
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unmap_region(r);
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/* change the address */
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if (r->type & PCI_ADDRESS_SPACE_IO)
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r->addr = val & ~0x3;
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else
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r->addr = val & ~0xf;
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#ifdef DEBUG_PCI
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printf("map addr=%08x size=%08x type=%d\n",
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r->addr, r->size, r->type);
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#endif
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r->map_func(pci_dev, reg, r->addr, r->size, r->type);
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}
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/* now compute the stored value */
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val &= ~(r->size - 1);
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val |= r->type;
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*(uint32_t *)(pci_dev->config + 0x10 + reg * 4) = cpu_to_le32(val);
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} else {
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default_config:
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pci_dev->config_write(pci_dev, config_addr, val, len);
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}
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}
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static uint32_t pci_data_read(void *opaque, uint32_t addr,
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int len)
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{
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PCIBridge *s = opaque;
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PCIDevice **bus, *pci_dev;
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int config_addr;
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uint32_t val;
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if (!(s->config_reg & (1 << 31)))
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goto fail;
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if ((s->config_reg & 0x3) != 0)
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goto fail;
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bus = s->pci_bus[(s->config_reg >> 16) & 0xff];
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if (!bus)
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goto fail;
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pci_dev = bus[(s->config_reg >> 8) & 0xff];
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if (!pci_dev) {
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fail:
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val = 0;
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goto the_end;
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}
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config_addr = (s->config_reg & 0xfc) | (addr & 3);
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val = pci_dev->config_read(pci_dev, config_addr, len);
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#if defined(DEBUG_PCI)
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printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
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pci_dev->name, config_addr, val, len);
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#endif
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the_end:
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#if defined(DEBUG_PCI) && 0
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printf("pci_data_read: addr=%08x val=%08x len=%d\n",
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s->config_reg, val, len);
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#endif
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return val;
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}
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static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
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{
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pci_data_write(opaque, addr, val, 1);
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}
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static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
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{
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pci_data_write(opaque, addr, val, 2);
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}
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static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
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{
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pci_data_write(opaque, addr, val, 4);
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}
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static uint32_t pci_data_readb(void* opaque, uint32_t addr)
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{
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return pci_data_read(opaque, addr, 1);
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}
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static uint32_t pci_data_readw(void* opaque, uint32_t addr)
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{
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return pci_data_read(opaque, addr, 2);
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}
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static uint32_t pci_data_readl(void* opaque, uint32_t addr)
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{
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return pci_data_read(opaque, addr, 4);
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}
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/* i440FX PCI bridge */
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static uint32_t i440_read_config(PCIDevice *d,
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uint32_t address, int len)
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{
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uint32_t val;
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val = 0;
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memcpy(&val, d->config + address, len);
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return val;
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}
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static void i440_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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memcpy(d->config + address, &val, len);
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}
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void i440fx_init(void)
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{
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PCIBridge *s = &pci_bridge;
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PCIDevice *d;
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register_ioport_write(0xcf8, 4, 4, pci_config_writel, s);
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register_ioport_read(0xcf8, 4, 4, pci_config_readl, s);
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register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
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register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
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register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
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register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
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register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
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register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
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d = pci_register_device("i440FX", sizeof(PCIDevice), 0, 0,
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i440_read_config, i440_write_config);
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d->config[0x00] = 0x86; // vendor_id
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d->config[0x01] = 0x80;
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d->config[0x02] = 0x37; // device_id
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d->config[0x03] = 0x12;
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d->config[0x08] = 0x02; // revision
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d->config[0x0a] = 0x04; // class_sub = pci2pci
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0c] = 0x01; // line_size in 32 bit words
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d->config[0x0e] = 0x01; // header_type
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}
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/* NOTE: the following should be done by the BIOS */
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static uint32_t pci_bios_io_addr;
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static uint32_t pci_bios_mem_addr;
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static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
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{
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PCIBridge *s = &pci_bridge;
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PCIIORegion *r;
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s->config_reg = 0x80000000 | (d->bus_num << 16) |
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(d->devfn << 8) | (0x10 + region_num * 4);
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pci_data_write(s, 0, addr, 4);
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r = &d->io_regions[region_num];
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/* enable memory mappings */
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if (r->type & PCI_ADDRESS_SPACE_IO)
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d->config[0x04] |= 1;
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else
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d->config[0x04] |= 2;
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}
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static void pci_bios_init_device(PCIDevice *d)
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{
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int class;
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PCIIORegion *r;
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uint32_t *paddr;
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int i;
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class = d->config[0x0a] | (d->config[0x0b] << 8);
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switch(class) {
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case 0x0101:
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/* IDE: we map it as in ISA mode */
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pci_set_io_region_addr(d, 0, 0x1f0);
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pci_set_io_region_addr(d, 1, 0x3f4);
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pci_set_io_region_addr(d, 2, 0x170);
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pci_set_io_region_addr(d, 3, 0x374);
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break;
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default:
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/* default memory mappings */
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for(i = 0; i < 6; i++) {
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r = &d->io_regions[i];
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if (r->size) {
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if (r->type & PCI_ADDRESS_SPACE_IO)
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paddr = &pci_bios_io_addr;
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else
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paddr = &pci_bios_mem_addr;
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*paddr = (*paddr + r->size - 1) & ~(r->size - 1);
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pci_set_io_region_addr(d, i, *paddr);
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*paddr += r->size;
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}
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}
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break;
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}
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}
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/*
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* This function initializes the PCI devices as a normal PCI BIOS
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* would do. It is provided just in case the BIOS has no support for
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* PCI.
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*/
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void pci_bios_init(void)
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{
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PCIBridge *s = &pci_bridge;
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PCIDevice **bus;
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int bus_num, devfn;
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pci_bios_io_addr = 0xc000;
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pci_bios_mem_addr = 0xf0000000;
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for(bus_num = 0; bus_num < 256; bus_num++) {
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bus = s->pci_bus[bus_num];
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if (bus) {
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|
|
for(devfn = 0; devfn < 256; devfn++) {
|
||
|
|
if (bus[devfn])
|
||
|
|
pci_bios_init_device(bus[devfn]);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|