311 lines
14 KiB
Plaintext
311 lines
14 KiB
Plaintext
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PCI EXPRESS GUIDELINES
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======================
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1. Introduction
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================
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The doc proposes best practices on how to use PCI Express/PCI device
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in PCI Express based machines and explains the reasoning behind them.
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The following presentations accompany this document:
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(1) Q35 overview.
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http://wiki.qemu.org/images/4/4e/Q35.pdf
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(2) A comparison between PCI and PCI Express technologies.
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http://wiki.qemu.org/images/f/f6/PCIvsPCIe.pdf
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Note: The usage examples are not intended to replace the full
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documentation, please use QEMU help to retrieve all options.
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2. Device placement strategy
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============================
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QEMU does not have a clear socket-device matching mechanism
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and allows any PCI/PCI Express device to be plugged into any
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PCI/PCI Express slot.
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Plugging a PCI device into a PCI Express slot might not always work and
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is weird anyway since it cannot be done for "bare metal".
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Plugging a PCI Express device into a PCI slot will hide the Extended
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Configuration Space thus is also not recommended.
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The recommendation is to separate the PCI Express and PCI hierarchies.
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PCI Express devices should be plugged only into PCI Express Root Ports and
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PCI Express Downstream ports.
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2.1 Root Bus (pcie.0)
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=====================
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Place only the following kinds of devices directly on the Root Complex:
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(1) PCI Devices (e.g. network card, graphics card, IDE controller),
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not controllers. Place only legacy PCI devices on
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the Root Complex. These will be considered Integrated Endpoints.
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Note: Integrated Endpoints are not hot-pluggable.
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Although the PCI Express spec does not forbid PCI Express devices as
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Integrated Endpoints, existing hardware mostly integrates legacy PCI
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devices with the Root Complex. Guest OSes are suspected to behave
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strangely when PCI Express devices are integrated
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with the Root Complex.
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(2) PCI Express Root Ports (ioh3420), for starting exclusively PCI Express
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hierarchies.
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(3) DMI-PCI Bridges (i82801b11-bridge), for starting legacy PCI
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hierarchies.
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(4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses
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are needed.
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pcie.0 bus
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----------------------------------------------------------------------------
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----------- ------------------ ------------------ --------------
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| PCI Dev | | PCIe Root Port | | DMI-PCI Bridge | | pxb-pcie |
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----------- ------------------ ------------------ --------------
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2.1.1 To plug a device into pcie.0 as a Root Complex Integrated Endpoint use:
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-device <dev>[,bus=pcie.0]
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2.1.2 To expose a new PCI Express Root Bus use:
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-device pxb-pcie,id=pcie.1,bus_nr=x[,numa_node=y][,addr=z]
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Only PCI Express Root Ports and DMI-PCI bridges can be connected
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to the pcie.1 bus:
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-device ioh3420,id=root_port1[,bus=pcie.1][,chassis=x][,slot=y][,addr=z] \
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-device i82801b11-bridge,id=dmi_pci_bridge1,bus=pcie.1
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2.2 PCI Express only hierarchy
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==============================
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Always use PCI Express Root Ports to start PCI Express hierarchies.
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A PCI Express Root bus supports up to 32 devices. Since each
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PCI Express Root Port is a function and a multi-function
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device may support up to 8 functions, the maximum possible
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number of PCI Express Root Ports per PCI Express Root Bus is 256.
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Prefer grouping PCI Express Root Ports into multi-function devices
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to keep a simple flat hierarchy that is enough for most scenarios.
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Only use PCI Express Switches (x3130-upstream, xio3130-downstream)
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if there is no more room for PCI Express Root Ports.
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Please see section 4. for further justifications.
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Plug only PCI Express devices into PCI Express Ports.
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pcie.0 bus
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----------------------------------------------------------------------------------
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------------- ------------- -------------
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| Root Port | | Root Port | | Root Port |
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------------ ------------- -------------
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| -------------------------|------------------------
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------------ | ----------------- |
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| PCIe Dev | | PCI Express | Upstream Port | |
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------------ | Switch ----------------- |
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| ------------------- ------------------- |
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| | Downstream Port | | Downstream Port | |
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| ------------------- ------------------- |
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-------------|-----------------------|------------
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------------
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| PCIe Dev |
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------------
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2.2.1 Plugging a PCI Express device into a PCI Express Root Port:
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-device ioh3420,id=root_port1,chassis=x,slot=y[,bus=pcie.0][,addr=z] \
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-device <dev>,bus=root_port1
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2.2.2 Using multi-function PCI Express Root Ports:
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-device ioh3420,id=root_port1,multifunction=on,chassis=x,slot=y[,bus=pcie.0][,addr=z.0] \
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-device ioh3420,id=root_port2,chassis=x1,slot=y1[,bus=pcie.0][,addr=z.1] \
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-device ioh3420,id=root_port3,chassis=x2,slot=y2[,bus=pcie.0][,addr=z.2] \
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2.2.2 Plugging a PCI Express device into a Switch:
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-device ioh3420,id=root_port1,chassis=x,slot=y[,bus=pcie.0][,addr=z] \
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-device x3130-upstream,id=upstream_port1,bus=root_port1[,addr=x] \
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-device xio3130-downstream,id=downstream_port1,bus=upstream_port1,chassis=x1,slot=y1[,addr=z1]] \
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-device <dev>,bus=downstream_port1
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Notes:
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- (slot, chassis) pair is mandatory and must be
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unique for each PCI Express Root Port.
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- 'addr' parameter can be 0 for all the examples above.
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2.3 PCI only hierarchy
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======================
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Legacy PCI devices can be plugged into pcie.0 as Integrated Endpoints,
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but, as mentioned in section 5, doing so means the legacy PCI
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device in question will be incapable of hot-unplugging.
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Besides that use DMI-PCI Bridges (i82801b11-bridge) in combination
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with PCI-PCI Bridges (pci-bridge) to start PCI hierarchies.
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Prefer flat hierarchies. For most scenarios a single DMI-PCI Bridge
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(having 32 slots) and several PCI-PCI Bridges attached to it
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(each supporting also 32 slots) will support hundreds of legacy devices.
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The recommendation is to populate one PCI-PCI Bridge under the DMI-PCI Bridge
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until is full and then plug a new PCI-PCI Bridge...
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pcie.0 bus
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----------------------------------------------
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----------- ------------------
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| PCI Dev | | DMI-PCI BRIDGE |
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---------- ------------------
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------------------ ------------------
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| PCI-PCI Bridge | | PCI-PCI Bridge | ...
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------------------ ------------------
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----------- -----------
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| PCI Dev | | PCI Dev |
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----------- -----------
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2.3.1 To plug a PCI device into pcie.0 as an Integrated Endpoint use:
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-device <dev>[,bus=pcie.0]
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2.3.2 Plugging a PCI device into a PCI-PCI Bridge:
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-device i82801b11-bridge,id=dmi_pci_bridge1[,bus=pcie.0] \
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-device pci-bridge,id=pci_bridge1,bus=dmi_pci_bridge1[,chassis_nr=x][,addr=y] \
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-device <dev>,bus=pci_bridge1[,addr=x]
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Note that 'addr' cannot be 0 unless shpc=off parameter is passed to
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the PCI Bridge.
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3. IO space issues
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===================
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The PCI Express Root Ports and PCI Express Downstream ports are seen by
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Firmware/Guest OS as PCI-PCI Bridges. As required by the PCI spec, each
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such Port should be reserved a 4K IO range for, even though only one
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(multifunction) device can be plugged into each Port. This results in
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poor IO space utilization.
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The firmware used by QEMU (SeaBIOS/OVMF) may try further optimizations
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by not allocating IO space for each PCI Express Root / PCI Express
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Downstream port if:
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(1) the port is empty, or
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(2) the device behind the port has no IO BARs.
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The IO space is very limited, to 65536 byte-wide IO ports, and may even be
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fragmented by fixed IO ports owned by platform devices resulting in at most
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10 PCI Express Root Ports or PCI Express Downstream Ports per system
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if devices with IO BARs are used in the PCI Express hierarchy. Using the
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proposed device placing strategy solves this issue by using only
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PCI Express devices within PCI Express hierarchy.
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The PCI Express spec requires that PCI Express devices work properly
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without using IO ports. The PCI hierarchy has no such limitations.
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4. Bus numbers issues
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======================
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Each PCI domain can have up to only 256 buses and the QEMU PCI Express
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machines do not support multiple PCI domains even if extra Root
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Complexes (pxb-pcie) are used.
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Each element of the PCI Express hierarchy (Root Complexes,
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PCI Express Root Ports, PCI Express Downstream/Upstream ports)
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uses one bus number. Since only one (multifunction) device
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can be attached to a PCI Express Root Port or PCI Express Downstream
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Port it is advised to plan in advance for the expected number of
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devices to prevent bus number starvation.
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Avoiding PCI Express Switches (and thereby striving for a 'flatter' PCI
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Express hierarchy) enables the hierarchy to not spend bus numbers on
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Upstream Ports.
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The bus_nr properties of the pxb-pcie devices partition the 0..255 bus
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number space. All bus numbers assigned to the buses recursively behind a
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given pxb-pcie device's root bus must fit between the bus_nr property of
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that pxb-pcie device, and the lowest of the higher bus_nr properties
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that the command line sets for other pxb-pcie devices.
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5. Hot-plug
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============
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The PCI Express root buses (pcie.0 and the buses exposed by pxb-pcie devices)
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do not support hot-plug, so any devices plugged into Root Complexes
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cannot be hot-plugged/hot-unplugged:
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(1) PCI Express Integrated Endpoints
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(2) PCI Express Root Ports
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(3) DMI-PCI Bridges
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(4) pxb-pcie
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Be aware that PCI Express Downstream Ports can't be hot-plugged into
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an existing PCI Express Upstream Port.
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PCI devices can be hot-plugged into PCI-PCI Bridges. The PCI hot-plug is ACPI
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based and can work side by side with the PCI Express native hot-plug.
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PCI Express devices can be natively hot-plugged/hot-unplugged into/from
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PCI Express Root Ports (and PCI Express Downstream Ports).
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5.1 Planning for hot-plug:
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(1) PCI hierarchy
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Leave enough PCI-PCI Bridge slots empty or add one
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or more empty PCI-PCI Bridges to the DMI-PCI Bridge.
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For each such PCI-PCI Bridge the Guest Firmware is expected to reserve
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4K IO space and 2M MMIO range to be used for all devices behind it.
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Because of the hard IO limit of around 10 PCI Bridges (~ 40K space)
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per system don't use more than 9 PCI-PCI Bridges, leaving 4K for the
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Integrated Endpoints. (The PCI Express Hierarchy needs no IO space).
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(2) PCI Express hierarchy:
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Leave enough PCI Express Root Ports empty. Use multifunction
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PCI Express Root Ports (up to 8 ports per pcie.0 slot)
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on the Root Complex(es), for keeping the
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hierarchy as flat as possible, thereby saving PCI bus numbers.
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Don't use PCI Express Switches if you don't have
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to, each one of those uses an extra PCI bus (for its Upstream Port)
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that could be put to better use with another Root Port or Downstream
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Port, which may come handy for hot-plugging another device.
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5.3 Hot-plug example:
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Using HMP: (add -monitor stdio to QEMU command line)
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device_add <dev>,id=<id>,bus=<PCI Express Root Port Id/PCI Express Downstream Port Id/PCI-PCI Bridge Id/>
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6. Device assignment
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====================
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Host devices are mostly PCI Express and should be plugged only into
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PCI Express Root Ports or PCI Express Downstream Ports.
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PCI-PCI Bridge slots can be used for legacy PCI host devices.
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6.1 How to detect if a device is PCI Express:
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> lspci -s 03:00.0 -v (as root)
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03:00.0 Network controller: Intel Corporation Wireless 7260 (rev 83)
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Subsystem: Intel Corporation Dual Band Wireless-AC 7260
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Flags: bus master, fast devsel, latency 0, IRQ 50
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Memory at f0400000 (64-bit, non-prefetchable) [size=8K]
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Capabilities: [c8] Power Management version 3
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Capabilities: [d0] MSI: Enable+ Count=1/1 Maskable- 64bit+
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Capabilities: [40] Express Endpoint, MSI 00
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Capabilities: [100] Advanced Error Reporting
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Capabilities: [140] Device Serial Number 7c-7a-91-ff-ff-90-db-20
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Capabilities: [14c] Latency Tolerance Reporting
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Capabilities: [154] Vendor Specific Information: ID=cafe Rev=1 Len=014
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If you can see the "Express Endpoint" capability in the
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output, then the device is indeed PCI Express.
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7. Virtio devices
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=================
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Virtio devices plugged into the PCI hierarchy or as Integrated Endpoints
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will remain PCI and have transitional behaviour as default.
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Transitional virtio devices work in both IO and MMIO modes depending on
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the guest support. The Guest firmware will assign both IO and MMIO resources
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to transitional virtio devices.
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Virtio devices plugged into PCI Express ports are PCI Express devices and
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have "1.0" behavior by default without IO support.
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In both cases disable-legacy and disable-modern properties can be used
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to override the behaviour.
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Note that setting disable-legacy=off will enable legacy mode (enabling
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legacy behavior) for PCI Express virtio devices causing them to
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require IO space, which, given the limited available IO space, may quickly
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lead to resource exhaustion, and is therefore strongly discouraged.
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8. Conclusion
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==============
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The proposal offers a usage model that is easy to understand and follow
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and at the same time overcomes the PCI Express architecture limitations.
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