2010-03-29 21:23:52 +02:00
|
|
|
#ifndef QEMU_ARCH_INIT_H
|
|
|
|
#define QEMU_ARCH_INIT_H
|
|
|
|
|
2012-08-15 05:17:36 +02:00
|
|
|
|
2010-03-29 21:23:52 +02:00
|
|
|
enum {
|
|
|
|
QEMU_ARCH_ALL = -1,
|
2014-09-21 13:07:21 +02:00
|
|
|
QEMU_ARCH_ALPHA = (1 << 0),
|
|
|
|
QEMU_ARCH_ARM = (1 << 1),
|
|
|
|
QEMU_ARCH_CRIS = (1 << 2),
|
|
|
|
QEMU_ARCH_I386 = (1 << 3),
|
|
|
|
QEMU_ARCH_M68K = (1 << 4),
|
|
|
|
QEMU_ARCH_MICROBLAZE = (1 << 6),
|
|
|
|
QEMU_ARCH_MIPS = (1 << 7),
|
|
|
|
QEMU_ARCH_PPC = (1 << 8),
|
|
|
|
QEMU_ARCH_S390X = (1 << 9),
|
|
|
|
QEMU_ARCH_SH4 = (1 << 10),
|
|
|
|
QEMU_ARCH_SPARC = (1 << 11),
|
|
|
|
QEMU_ARCH_XTENSA = (1 << 12),
|
|
|
|
QEMU_ARCH_OPENRISC = (1 << 13),
|
|
|
|
QEMU_ARCH_TRICORE = (1 << 16),
|
2017-01-18 23:01:46 +01:00
|
|
|
QEMU_ARCH_NIOS2 = (1 << 17),
|
2017-10-01 22:11:45 +02:00
|
|
|
QEMU_ARCH_HPPA = (1 << 18),
|
2018-03-02 13:32:59 +01:00
|
|
|
QEMU_ARCH_RISCV = (1 << 19),
|
2019-01-21 14:18:59 +01:00
|
|
|
QEMU_ARCH_RX = (1 << 20),
|
2020-01-24 01:51:21 +01:00
|
|
|
QEMU_ARCH_AVR = (1 << 21),
|
2021-07-30 12:59:44 +02:00
|
|
|
QEMU_ARCH_HEXAGON = (1 << 22),
|
2010-03-29 21:23:52 +02:00
|
|
|
};
|
|
|
|
|
|
|
|
extern const uint32_t arch_type;
|
|
|
|
|
|
|
|
#endif
|