75 lines
2.0 KiB
C
75 lines
2.0 KiB
C
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/*
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* ARM Generic Interrupt Controller v3
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*
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* Copyright (c) 2015 Huawei.
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* Copyright (c) 2016 Linaro Limited
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* Written by Shlomo Pongratz, Peter Maydell
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*
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* This code is licensed under the GPL, version 2 or (at your option)
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* any later version.
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*/
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/* This file contains implementation code for an interrupt controller
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* which implements the GICv3 architecture. Specifically this is where
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* the device class itself and the functions for handling interrupts
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* coming in and going out live.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/intc/arm_gicv3.h"
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#include "gicv3_internal.h"
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/* Process a change in an external IRQ input. */
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static void gicv3_set_irq(void *opaque, int irq, int level)
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{
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/* Meaning of the 'irq' parameter:
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* [0..N-1] : external interrupts
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* [N..N+31] : PPI (internal) interrupts for CPU 0
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* [N+32..N+63] : PPI (internal interrupts for CPU 1
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* ...
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*/
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/* Do nothing for now */
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}
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static void arm_gic_realize(DeviceState *dev, Error **errp)
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{
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/* Device instance realize function for the GIC sysbus device */
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GICv3State *s = ARM_GICV3(dev);
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ARMGICv3Class *agc = ARM_GICV3_GET_CLASS(s);
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Error *local_err = NULL;
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agc->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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gicv3_init_irqs_and_mmio(s, gicv3_set_irq, NULL);
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}
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static void arm_gicv3_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ARMGICv3Class *agc = ARM_GICV3_CLASS(klass);
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agc->parent_realize = dc->realize;
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dc->realize = arm_gic_realize;
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}
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static const TypeInfo arm_gicv3_info = {
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.name = TYPE_ARM_GICV3,
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.parent = TYPE_ARM_GICV3_COMMON,
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.instance_size = sizeof(GICv3State),
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.class_init = arm_gicv3_class_init,
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.class_size = sizeof(ARMGICv3Class),
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};
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static void arm_gicv3_register_types(void)
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{
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type_register_static(&arm_gicv3_info);
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}
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type_init(arm_gicv3_register_types)
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