2020-09-01 03:39:00 +02:00
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/*
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* Microchip PolarFire SoC MMUART emulation
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_MCHP_PFSOC_MMUART_H
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#define HW_MCHP_PFSOC_MMUART_H
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2021-09-25 15:34:07 +02:00
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#include "hw/sysbus.h"
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2020-09-01 03:39:00 +02:00
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#include "hw/char/serial.h"
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2021-09-25 15:34:05 +02:00
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#define MCHP_PFSOC_MMUART_REG_COUNT 13
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2020-09-01 03:39:00 +02:00
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2021-09-25 15:34:07 +02:00
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#define TYPE_MCHP_PFSOC_UART "mchp.pfsoc.uart"
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OBJECT_DECLARE_SIMPLE_TYPE(MchpPfSoCMMUartState, MCHP_PFSOC_UART)
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2020-09-01 03:39:00 +02:00
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typedef struct MchpPfSoCMMUartState {
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2021-09-25 15:34:07 +02:00
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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hw/char/mchp_pfsoc_mmuart: Use a MemoryRegion container
Our device have 2 different I/O regions:
- a 16550 UART mapped for 32-bit accesses
- 13 extra registers
Instead of mapping each region on the main bus, introduce
a container, map the 2 devices regions on the container,
and map the container on the main bus.
Before:
(qemu) info mtree
...
0000000020100000-000000002010001f (prio 0, i/o): serial
0000000020100020-000000002010101f (prio 0, i/o): mchp.pfsoc.mmuart
0000000020102000-000000002010201f (prio 0, i/o): serial
0000000020102020-000000002010301f (prio 0, i/o): mchp.pfsoc.mmuart
0000000020104000-000000002010401f (prio 0, i/o): serial
0000000020104020-000000002010501f (prio 0, i/o): mchp.pfsoc.mmuart
0000000020106000-000000002010601f (prio 0, i/o): serial
0000000020106020-000000002010701f (prio 0, i/o): mchp.pfsoc.mmuart
After:
(qemu) info mtree
...
0000000020100000-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart
0000000020100000-000000002010001f (prio 0, i/o): serial
0000000020100020-0000000020100fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
0000000020102000-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart
0000000020102000-000000002010201f (prio 0, i/o): serial
0000000020102020-0000000020102fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
0000000020104000-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart
0000000020104000-000000002010401f (prio 0, i/o): serial
0000000020104020-0000000020104fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
0000000020106000-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart
0000000020106000-000000002010601f (prio 0, i/o): serial
0000000020106020-0000000020106fff (prio 0, i/o): mchp.pfsoc.mmuart.regs
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: 20210925133407.1259392-3-f4bug@amsat.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-25 15:34:06 +02:00
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MemoryRegion container;
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2020-09-01 03:39:00 +02:00
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MemoryRegion iomem;
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2021-09-25 15:34:07 +02:00
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SerialMM serial_mm;
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2020-09-01 03:39:00 +02:00
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2021-09-25 15:34:05 +02:00
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uint32_t reg[MCHP_PFSOC_MMUART_REG_COUNT];
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2020-09-01 03:39:00 +02:00
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} MchpPfSoCMMUartState;
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/**
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* mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART
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*
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* This is a helper routine for board to create a MMUART device that is
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* compatible with Microchip PolarFire SoC.
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*
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* @sysmem: system memory region to map
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* @base: base address of the MMUART registers
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* @irq: IRQ number of the MMUART device
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* @chr: character device to associate to
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*
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* @return: a pointer to the device specific control structure
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*/
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MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
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hwaddr base, qemu_irq irq, Chardev *chr);
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#endif /* HW_MCHP_PFSOC_MMUART_H */
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