2022-05-01 07:49:43 +02:00
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/*
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* QEMU ARM CP Register access and descriptions
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*
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* Copyright (c) 2022 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#ifndef TARGET_ARM_CPREGS_H
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#define TARGET_ARM_CPREGS_H
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/*
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* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
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* special-behaviour cp reg and bits [11..8] indicate what behaviour
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* it has. Otherwise it is a simple cp reg, where CONST indicates that
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* TCG can assume the value to be constant (ie load at translate time)
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* and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
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* indicates that the TB should not be ended after a write to this register
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* (the default is that the TB ends after cp writes). OVERRIDE permits
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* a register definition to override a previous definition for the
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* same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
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* old must have the OVERRIDE bit set.
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* ALIAS indicates that this register is an alias view of some underlying
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* state which is also visible via another register, and that the other
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* register is handling migration and reset; registers marked ALIAS will not be
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* migrated but may have their state set by syncing of register state from KVM.
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* NO_RAW indicates that this register has no underlying state and does not
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* support raw access for state saving/loading; it will not be used for either
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* migration or KVM state synchronization. (Typically this is for "registers"
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* which are actually used as instructions for cache maintenance and so on.)
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* IO indicates that this register does I/O and therefore its accesses
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* need to be marked with gen_io_start() and also end the TB. In particular,
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* registers which implement clocks or timers require this.
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* RAISES_EXC is for when the read or write hook might raise an exception;
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* the generated code will synchronize the CPU state before calling the hook
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* so that it is safe for the hook to call raise_exception().
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* NEWEL is for writes to registers that might change the exception
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* level - typically on older ARM chips. For those cases we need to
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* re-read the new el when recomputing the translation flags.
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*/
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#define ARM_CP_SPECIAL 0x0001
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#define ARM_CP_CONST 0x0002
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#define ARM_CP_64BIT 0x0004
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#define ARM_CP_SUPPRESS_TB_END 0x0008
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#define ARM_CP_OVERRIDE 0x0010
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#define ARM_CP_ALIAS 0x0020
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#define ARM_CP_IO 0x0040
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#define ARM_CP_NO_RAW 0x0080
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#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
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#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
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#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
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#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
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#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
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#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600)
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#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700)
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#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA
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#define ARM_CP_FPU 0x1000
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#define ARM_CP_SVE 0x2000
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#define ARM_CP_NO_GDB 0x4000
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#define ARM_CP_RAISES_EXC 0x8000
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#define ARM_CP_NEWEL 0x10000
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/* Mask of only the flag bits in a type field */
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#define ARM_CP_FLAG_MASK 0x1f0ff
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/*
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* Valid values for ARMCPRegInfo state field, indicating which of
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* the AArch32 and AArch64 execution states this register is visible in.
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* If the reginfo doesn't explicitly specify then it is AArch32 only.
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* If the reginfo is declared to be visible in both states then a second
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* reginfo is synthesised for the AArch32 view of the AArch64 register,
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* such that the AArch32 view is the lower 32 bits of the AArch64 one.
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* Note that we rely on the values of these enums as we iterate through
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* the various states in some places.
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*/
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enum {
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ARM_CP_STATE_AA32 = 0,
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ARM_CP_STATE_AA64 = 1,
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ARM_CP_STATE_BOTH = 2,
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};
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/*
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* ARM CP register secure state flags. These flags identify security state
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* attributes for a given CP register entry.
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* The existence of both or neither secure and non-secure flags indicates that
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* the register has both a secure and non-secure hash entry. A single one of
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* these flags causes the register to only be hashed for the specified
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* security state.
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* Although definitions may have any combination of the S/NS bits, each
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* registered entry will only have one to identify whether the entry is secure
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* or non-secure.
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*/
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enum {
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ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
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ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
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};
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/*
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* Access rights:
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* We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
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* defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
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* PL2 (hyp). The other level which has Read and Write bits is Secure PL1
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* (ie any of the privileged modes in Secure state, or Monitor mode).
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* If a register is accessible in one privilege level it's always accessible
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* in higher privilege levels too. Since "Secure PL1" also follows this rule
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* (ie anything visible in PL2 is visible in S-PL1, some things are only
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* visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
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* terminology a little and call this PL3.
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* In AArch64 things are somewhat simpler as the PLx bits line up exactly
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* with the ELx exception levels.
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*
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* If access permissions for a register are more complex than can be
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* described with these bits, then use a laxer set of restrictions, and
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* do the more restrictive/complex check inside a helper function.
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*/
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#define PL3_R 0x80
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#define PL3_W 0x40
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#define PL2_R (0x20 | PL3_R)
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#define PL2_W (0x10 | PL3_W)
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#define PL1_R (0x08 | PL2_R)
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#define PL1_W (0x04 | PL2_W)
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#define PL0_R (0x02 | PL1_R)
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#define PL0_W (0x01 | PL1_W)
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/*
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* For user-mode some registers are accessible to EL0 via a kernel
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* trap-and-emulate ABI. In this case we define the read permissions
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* as actually being PL0_R. However some bits of any given register
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* may still be masked.
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*/
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#ifdef CONFIG_USER_ONLY
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#define PL0U_R PL0_R
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#else
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#define PL0U_R PL1_R
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#endif
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#define PL3_RW (PL3_R | PL3_W)
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#define PL2_RW (PL2_R | PL2_W)
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#define PL1_RW (PL1_R | PL1_W)
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#define PL0_RW (PL0_R | PL0_W)
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typedef enum CPAccessResult {
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/* Access is permitted */
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CP_ACCESS_OK = 0,
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2022-05-01 07:49:44 +02:00
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/*
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* Combined with one of the following, the low 2 bits indicate the
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* target exception level. If 0, the exception is taken to the usual
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* target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
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*/
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CP_ACCESS_EL_MASK = 3,
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2022-05-01 07:49:43 +02:00
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/*
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* Access fails due to a configurable trap or enable which would
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* result in a categorized exception syndrome giving information about
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* the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
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2022-05-01 07:49:44 +02:00
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* 0xc or 0x18).
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2022-05-01 07:49:43 +02:00
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*/
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2022-05-01 07:49:44 +02:00
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CP_ACCESS_TRAP = (1 << 2),
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CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
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CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
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2022-05-01 07:49:43 +02:00
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/*
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* Access fails and results in an exception syndrome 0x0 ("uncategorized").
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* Note that this is not a catch-all case -- the set of cases which may
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* result in this failure is specifically defined by the architecture.
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*/
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2022-05-01 07:49:44 +02:00
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CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
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CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = CP_ACCESS_TRAP_UNCATEGORIZED | 2,
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CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = CP_ACCESS_TRAP_UNCATEGORIZED | 3,
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2022-05-01 07:49:43 +02:00
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} CPAccessResult;
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typedef struct ARMCPRegInfo ARMCPRegInfo;
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/*
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* Access functions for coprocessor registers. These cannot fail and
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* may not raise exceptions.
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*/
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typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
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typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
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uint64_t value);
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/* Access permission check functions for coprocessor registers. */
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typedef CPAccessResult CPAccessFn(CPUARMState *env,
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const ARMCPRegInfo *opaque,
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bool isread);
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/* Hook function for register reset */
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typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
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#define CP_ANY 0xff
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/* Definition of an ARM coprocessor register */
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struct ARMCPRegInfo {
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/* Name of register (useful mainly for debugging, need not be unique) */
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const char *name;
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/*
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* Location of register: coprocessor number and (crn,crm,opc1,opc2)
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* tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
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* 'wildcard' field -- any value of that field in the MRC/MCR insn
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* will be decoded to this register. The register read and write
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* callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
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* used by the program, so it is possible to register a wildcard and
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* then behave differently on read/write if necessary.
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* For 64 bit registers, only crm and opc1 are relevant; crn and opc2
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* must both be zero.
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* For AArch64-visible registers, opc0 is also used.
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* Since there are no "coprocessors" in AArch64, cp is purely used as a
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* way to distinguish (for KVM's benefit) guest-visible system registers
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* from demuxed ones provided to preserve the "no side effects on
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* KVM register read/write from QEMU" semantics. cp==0x13 is guest
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* visible (to match KVM's encoding); cp==0 will be converted to
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* cp==0x13 when the ARMCPRegInfo is registered, for convenience.
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*/
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uint8_t cp;
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uint8_t crn;
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uint8_t crm;
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uint8_t opc0;
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uint8_t opc1;
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uint8_t opc2;
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/* Execution state in which this register is visible: ARM_CP_STATE_* */
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int state;
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/* Register type: ARM_CP_* bits/values */
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int type;
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/* Access rights: PL*_[RW] */
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int access;
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/* Security state: ARM_CP_SECSTATE_* bits/values */
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int secure;
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/*
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* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
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* this register was defined: can be used to hand data through to the
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* register read/write functions, since they are passed the ARMCPRegInfo*.
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*/
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void *opaque;
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/*
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* Value of this register, if it is ARM_CP_CONST. Otherwise, if
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* fieldoffset is non-zero, the reset value of the register.
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*/
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uint64_t resetvalue;
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/*
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* Offset of the field in CPUARMState for this register.
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* This is not needed if either:
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* 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
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* 2. both readfn and writefn are specified
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*/
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ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
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/*
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* Offsets of the secure and non-secure fields in CPUARMState for the
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* register if it is banked. These fields are only used during the static
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* registration of a register. During hashing the bank associated
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* with a given security state is copied to fieldoffset which is used from
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* there on out.
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*
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* It is expected that register definitions use either fieldoffset or
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* bank_fieldoffsets in the definition but not both. It is also expected
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* that both bank offsets are set when defining a banked register. This
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* use indicates that a register is banked.
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*/
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ptrdiff_t bank_fieldoffsets[2];
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/*
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* Function for making any access checks for this register in addition to
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* those specified by the 'access' permissions bits. If NULL, no extra
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* checks required. The access check is performed at runtime, not at
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* translate time.
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*/
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CPAccessFn *accessfn;
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/*
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* Function for handling reads of this register. If NULL, then reads
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* will be done by loading from the offset into CPUARMState specified
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* by fieldoffset.
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*/
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CPReadFn *readfn;
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/*
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* Function for handling writes of this register. If NULL, then writes
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* will be done by writing to the offset into CPUARMState specified
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* by fieldoffset.
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*/
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CPWriteFn *writefn;
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/*
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* Function for doing a "raw" read; used when we need to copy
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* coprocessor state to the kernel for KVM or out for
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* migration. This only needs to be provided if there is also a
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* readfn and it has side effects (for instance clear-on-read bits).
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*/
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CPReadFn *raw_readfn;
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/*
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* Function for doing a "raw" write; used when we need to copy KVM
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* kernel coprocessor state into userspace, or for inbound
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* migration. This only needs to be provided if there is also a
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* writefn and it masks out "unwritable" bits or has write-one-to-clear
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* or similar behaviour.
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*/
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CPWriteFn *raw_writefn;
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/*
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* Function for resetting the register. If NULL, then reset will be done
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* by writing resetvalue to the field specified in fieldoffset. If
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* fieldoffset is 0 then no reset will be done.
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*/
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CPResetFn *resetfn;
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/*
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* "Original" writefn and readfn.
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* For ARMv8.1-VHE register aliases, we overwrite the read/write
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* accessor functions of various EL1/EL0 to perform the runtime
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* check for which sysreg should actually be modified, and then
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* forwards the operation. Before overwriting the accessors,
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* the original function is copied here, so that accesses that
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* really do go to the EL1/EL0 version proceed normally.
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* (The corresponding EL2 register is linked via opaque.)
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*/
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CPReadFn *orig_readfn;
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CPWriteFn *orig_writefn;
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};
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/*
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* Macros which are lvalues for the field in CPUARMState for the
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* ARMCPRegInfo *ri.
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*/
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#define CPREG_FIELD32(env, ri) \
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(*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
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#define CPREG_FIELD64(env, ri) \
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(*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
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2022-05-01 07:49:45 +02:00
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void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
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void *opaque);
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2022-05-01 07:49:43 +02:00
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static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
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{
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2022-05-01 07:49:45 +02:00
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define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
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2022-05-01 07:49:43 +02:00
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}
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2022-05-01 07:49:45 +02:00
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void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
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void *opaque, size_t len);
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#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \
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do { \
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QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
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define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \
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ARRAY_SIZE(REGS)); \
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} while (0)
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#define define_arm_cp_regs(CPU, REGS) \
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define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
|
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|
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2022-05-01 07:49:43 +02:00
|
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const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
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|
|
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|
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/*
|
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|
|
* Definition of an ARM co-processor register as viewed from
|
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|
|
* userspace. This is used for presenting sanitised versions of
|
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|
|
* registers to userspace when emulating the Linux AArch64 CPU
|
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|
|
* ID/feature ABI (advertised as HWCAP_CPUID).
|
|
|
|
*/
|
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|
|
typedef struct ARMCPRegUserSpaceInfo {
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|
|
/* Name of register */
|
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|
|
const char *name;
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|
|
|
|
|
|
/* Is the name actually a glob pattern */
|
|
|
|
bool is_glob;
|
|
|
|
|
|
|
|
/* Only some bits are exported to user space */
|
|
|
|
uint64_t exported_bits;
|
|
|
|
|
|
|
|
/* Fixed bits are applied after the mask */
|
|
|
|
uint64_t fixed_bits;
|
|
|
|
} ARMCPRegUserSpaceInfo;
|
|
|
|
|
2022-05-01 07:49:45 +02:00
|
|
|
void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
|
|
|
|
const ARMCPRegUserSpaceInfo *mods,
|
|
|
|
size_t mods_len);
|
2022-05-01 07:49:43 +02:00
|
|
|
|
2022-05-01 07:49:45 +02:00
|
|
|
#define modify_arm_cp_regs(REGS, MODS) \
|
|
|
|
do { \
|
|
|
|
QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
|
|
|
|
QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \
|
|
|
|
modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \
|
|
|
|
MODS, ARRAY_SIZE(MODS)); \
|
|
|
|
} while (0)
|
2022-05-01 07:49:43 +02:00
|
|
|
|
|
|
|
/* CPWriteFn that can be used to implement writes-ignored behaviour */
|
|
|
|
void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
|
|
|
|
uint64_t value);
|
|
|
|
/* CPReadFn that can be used for read-as-zero behaviour */
|
|
|
|
uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CPResetFn that does nothing, for use if no reset is required even
|
|
|
|
* if fieldoffset is non zero.
|
|
|
|
*/
|
|
|
|
void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Return true if this reginfo struct's field in the cpu state struct
|
|
|
|
* is 64 bits wide.
|
|
|
|
*/
|
|
|
|
static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
|
|
|
|
{
|
|
|
|
return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool cp_access_ok(int current_el,
|
|
|
|
const ARMCPRegInfo *ri, int isread)
|
|
|
|
{
|
|
|
|
return (ri->access >> ((current_el * 2) + isread)) & 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Raw read of a coprocessor register (as needed for migration, etc) */
|
|
|
|
uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
|
|
|
|
|
|
|
|
#endif /* TARGET_ARM_CPREGS_H */
|