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qemu-e2k/target/xtensa/core-test_mmuhifi_c3/gdb-config.c.inc

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target/xtensa: add test_mmuhifi_c3 core test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-12-04 01:45:30 +01:00
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
target/xtensa: regenerate and re-import test_mmuhifi_c3 core Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in it. Fix that by regenerating test_mmuhifi_c3 core overlay and re-importing it. Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-10-09 04:03:33 +02:00
Copyright (c) 2003-2019 Tensilica Inc.
target/xtensa: add test_mmuhifi_c3 core test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-12-04 01:45:30 +01:00
target/xtensa: regenerate and re-import test_mmuhifi_c3 core Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in it. Fix that by regenerating test_mmuhifi_c3 core overlay and re-importing it. Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-10-09 04:03:33 +02:00
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
target/xtensa: add test_mmuhifi_c3 core test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-12-04 01:45:30 +01:00
target/xtensa: regenerate and re-import test_mmuhifi_c3 core Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in it. Fix that by regenerating test_mmuhifi_c3 core overlay and re-importing it. Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-10-09 04:03:33 +02:00
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
target/xtensa: add test_mmuhifi_c3 core test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-12-04 01:45:30 +01:00
target/xtensa: regenerate and re-import test_mmuhifi_c3 core Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in it. Fix that by regenerating test_mmuhifi_c3 core overlay and re-importing it. Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-10-09 04:03:33 +02:00
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
target/xtensa: add test_mmuhifi_c3 core test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-12-04 01:45:30 +01:00
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase, 0,0,0,0,0,0)
XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
target/xtensa: regenerate and re-import test_mmuhifi_c3 core Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in it. Fix that by regenerating test_mmuhifi_c3 core overlay and re-importing it. Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-10-09 04:03:33 +02:00
XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
target/xtensa: add test_mmuhifi_c3 core test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-12-04 01:45:30 +01:00
XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
XTREG( 45,180,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
XTREG( 46,184,48, 8, 8,0x0060,0x0006, 1, 4,0x0101,aep0,
"03:04:84:b2","03:04:84:a7",0,0,0,0)
XTREG( 47,192,48, 8, 8,0x0061,0x0006, 1, 4,0x0101,aep1,
"03:04:94:b2","03:04:94:a7",0,0,0,0)
XTREG( 48,200,48, 8, 8,0x0062,0x0006, 1, 4,0x0101,aep2,
"03:04:a4:b2","03:04:a4:a7",0,0,0,0)
XTREG( 49,208,48, 8, 8,0x0063,0x0006, 1, 4,0x0101,aep3,
"03:04:b4:b2","03:04:b4:a7",0,0,0,0)
XTREG( 50,216,48, 8, 8,0x0064,0x0006, 1, 4,0x0101,aep4,
"03:04:c4:b2","03:04:c4:a7",0,0,0,0)
XTREG( 51,224,48, 8, 8,0x0065,0x0006, 1, 4,0x0101,aep5,
"03:04:d4:b2","03:04:d4:a7",0,0,0,0)
XTREG( 52,232,48, 8, 8,0x0066,0x0006, 1, 4,0x0101,aep6,
"03:04:e4:b2","03:04:e4:a7",0,0,0,0)
XTREG( 53,240,48, 8, 8,0x0067,0x0006, 1, 4,0x0101,aep7,
"03:04:f4:b2","03:04:f4:a7",0,0,0,0)
XTREG( 54,248,56, 8, 8,0x0068,0x0006, 1, 4,0x0101,aeq0,
"03:04:04:c3","03:04:04:c1",0,0,0,0)
XTREG( 55,256,56, 8, 8,0x0069,0x0006, 1, 4,0x0101,aeq1,
"03:04:14:c3","03:04:44:c1",0,0,0,0)
XTREG( 56,264,56, 8, 8,0x006a,0x0006, 1, 4,0x0101,aeq2,
"03:04:24:c3","03:04:84:c1",0,0,0,0)
XTREG( 57,272,56, 8, 8,0x006b,0x0006, 1, 4,0x0101,aeq3,
"03:04:34:c3","03:04:c4:c1",0,0,0,0)
XTREG( 58,280, 7, 4, 4,0x03f0,0x0006, 1, 3,0x0100,ae_ovf_sar, 0,0,0,0,0,0)
XTREG( 59,284,32, 4, 4,0x03f1,0x0006, 1, 3,0x0110,ae_bithead, 0,0,0,0,0,0)
XTREG( 60,288,16, 4, 4,0x03f2,0x0006, 1, 3,0x0100,ae_ts_fts_bu_bp,0,0,0,0,0,0)
XTREG( 61,292,28, 4, 4,0x03f3,0x0006, 1, 3,0x0100,ae_sd_no, 0,0,0,0,0,0)
XTREG( 62,296,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
XTREG( 63,300,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
XTREG( 64,304,18, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
XTREG( 65,308,18, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
XTREG( 66,312, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
XTREG( 67,316,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
XTREG( 68,320,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
XTREG( 69,324,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
XTREG( 70,328,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
XTREG( 71,332,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
XTREG( 72,336,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
XTREG( 73,340,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
XTREG( 74,344, 2, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
XTREG( 75,348,12, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
XTREG( 76,352,12, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
XTREG( 77,356,12, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
XTREG( 78,360,12, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
XTREG( 79,364,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
XTREG( 80,368, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
XTREG( 81,372,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
XTREG( 82,376,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
XTREG( 83,380,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
XTREG( 84,384,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
XTREG( 85,388, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
XTREG( 86,392,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
XTREG( 87,396,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
XTREG( 88,400,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
XTREG( 89,404,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
XTREG( 90,408,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
XTREG( 91,412,32, 4, 4,0x0000,0x0006,-2, 8,0x0100,a0, 0,0,0,0,0,0)
XTREG( 92,416,32, 4, 4,0x0001,0x0006,-2, 8,0x0100,a1, 0,0,0,0,0,0)
XTREG( 93,420,32, 4, 4,0x0002,0x0006,-2, 8,0x0100,a2, 0,0,0,0,0,0)
XTREG( 94,424,32, 4, 4,0x0003,0x0006,-2, 8,0x0100,a3, 0,0,0,0,0,0)
XTREG( 95,428,32, 4, 4,0x0004,0x0006,-2, 8,0x0100,a4, 0,0,0,0,0,0)
XTREG( 96,432,32, 4, 4,0x0005,0x0006,-2, 8,0x0100,a5, 0,0,0,0,0,0)
XTREG( 97,436,32, 4, 4,0x0006,0x0006,-2, 8,0x0100,a6, 0,0,0,0,0,0)
XTREG( 98,440,32, 4, 4,0x0007,0x0006,-2, 8,0x0100,a7, 0,0,0,0,0,0)
XTREG( 99,444,32, 4, 4,0x0008,0x0006,-2, 8,0x0100,a8, 0,0,0,0,0,0)
XTREG(100,448,32, 4, 4,0x0009,0x0006,-2, 8,0x0100,a9, 0,0,0,0,0,0)
XTREG(101,452,32, 4, 4,0x000a,0x0006,-2, 8,0x0100,a10, 0,0,0,0,0,0)
XTREG(102,456,32, 4, 4,0x000b,0x0006,-2, 8,0x0100,a11, 0,0,0,0,0,0)
XTREG(103,460,32, 4, 4,0x000c,0x0006,-2, 8,0x0100,a12, 0,0,0,0,0,0)
XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13, 0,0,0,0,0,0)
XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14, 0,0,0,0,0,0)
XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15, 0,0,0,0,0,0)
target/xtensa: regenerate and re-import test_mmuhifi_c3 core Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in it. Fix that by regenerating test_mmuhifi_c3 core overlay and re-importing it. Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core") Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-10-09 04:03:33 +02:00
XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
0,0,&xtensa_mask0,0,0,0)
XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
0,0,&xtensa_mask1,0,0,0)
XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
0,0,&xtensa_mask2,0,0,0)
XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
0,0,&xtensa_mask3,0,0,0)
XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
0,0,&xtensa_mask4,0,0,0)
XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
0,0,&xtensa_mask5,0,0,0)
XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
0,0,&xtensa_mask6,0,0,0)
XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
0,0,&xtensa_mask7,0,0,0)
XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
0,0,&xtensa_mask8,0,0,0)
XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
0,0,&xtensa_mask9,0,0,0)
XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
0,0,&xtensa_mask10,0,0,0)
XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
0,0,&xtensa_mask11,0,0,0)
XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
0,0,&xtensa_mask12,0,0,0)
XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
0,0,&xtensa_mask13,0,0,0)
XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
0,0,&xtensa_mask14,0,0,0)
XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
0,0,&xtensa_mask15,0,0,0)
XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
0,0,&xtensa_mask16,0,0,0)
XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
0,0,&xtensa_mask17,0,0,0)
XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
0,0,&xtensa_mask18,0,0,0)
XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
0,0,&xtensa_mask19,0,0,0)
XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
0,0,&xtensa_mask20,0,0,0)
XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
0,0,&xtensa_mask21,0,0,0)
XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
0,0,&xtensa_mask22,0,0,0)
XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
0,0,&xtensa_mask23,0,0,0)
XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
0,0,&xtensa_mask24,0,0,0)
XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
0,0,&xtensa_mask25,0,0,0)
XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
0,0,&xtensa_mask26,0,0,0)
XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
0,0,&xtensa_mask27,0,0,0)
XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
0,0,&xtensa_mask28,0,0,0)
XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
0,0,&xtensa_mask29,0,0,0)
XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
0,0,&xtensa_mask30,0,0,0)
XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
0,0,&xtensa_mask31,0,0,0)
XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
0,0,&xtensa_mask32,0,0,0)
XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
0,0,&xtensa_mask33,0,0,0)
XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
0,0,&xtensa_mask34,0,0,0)
XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
0,0,&xtensa_mask35,0,0,0)
XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
0,0,&xtensa_mask36,0,0,0)
XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
0,0,&xtensa_mask37,0,0,0)
XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
0,0,&xtensa_mask38,0,0,0)
target/xtensa: add test_mmuhifi_c3 core test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-12-04 01:45:30 +01:00
XTREG_END