2016-12-15 20:26:14 +01:00
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/*
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* QEMU HPPA CPU
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*
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* Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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2019-04-17 21:17:57 +02:00
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#include "qemu/qemu-print.h"
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2022-02-07 09:27:54 +01:00
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#include "qemu/timer.h"
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2016-12-15 20:26:14 +01:00
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#include "cpu.h"
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2019-05-23 16:35:07 +02:00
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#include "qemu/module.h"
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2016-12-15 20:26:14 +01:00
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#include "exec/exec-all.h"
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2018-01-19 19:24:22 +01:00
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#include "fpu/softfloat.h"
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2016-12-15 20:26:14 +01:00
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static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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cpu->env.iaoq_f = value;
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cpu->env.iaoq_b = value + 4;
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}
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2022-09-30 19:31:21 +02:00
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static vaddr hppa_cpu_get_pc(CPUState *cs)
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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return cpu->env.iaoq_f;
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}
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2020-10-29 20:30:01 +01:00
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static void hppa_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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2016-12-15 20:26:14 +01:00
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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2017-10-22 07:53:35 +02:00
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#ifdef CONFIG_USER_ONLY
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2022-08-15 22:16:06 +02:00
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cpu->env.iaoq_f = tb_pc(tb);
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2016-12-15 20:26:14 +01:00
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cpu->env.iaoq_b = tb->cs_base;
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2017-10-22 07:53:35 +02:00
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#else
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/* Recover the IAOQ values from the GVA + PRIV. */
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uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3;
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target_ulong cs_base = tb->cs_base;
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target_ulong iasq_f = cs_base & ~0xffffffffull;
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int32_t diff = cs_base;
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cpu->env.iasq_f = iasq_f;
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2022-08-15 22:16:06 +02:00
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cpu->env.iaoq_f = (tb_pc(tb) & ~iasq_f) + priv;
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2017-10-22 07:53:35 +02:00
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if (diff) {
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cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
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}
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#endif
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2017-10-09 19:17:24 +02:00
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cpu->env.psw_n = (tb->flags & PSW_N) != 0;
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2016-12-15 20:26:14 +01:00
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}
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2022-10-24 12:13:57 +02:00
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static void hppa_restore_state_to_opc(CPUState *cs,
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const TranslationBlock *tb,
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const uint64_t *data)
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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cpu->env.iaoq_f = data[0];
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if (data[1] != (target_ureg)-1) {
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cpu->env.iaoq_b = data[1];
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}
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/*
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* Since we were executing the instruction at IAOQ_F, and took some
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* sort of action that provoked the cpu_restore_state, we can infer
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* that the instruction was not nullified.
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*/
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cpu->env.psw_n = 0;
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}
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2017-12-29 02:36:45 +01:00
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static bool hppa_cpu_has_work(CPUState *cs)
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{
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2022-01-05 23:09:04 +01:00
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return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
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2017-12-29 02:36:45 +01:00
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}
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2016-12-15 20:26:14 +01:00
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static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
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{
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info->mach = bfd_mach_hppa20;
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info->print_insn = print_insn_hppa;
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}
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2021-02-04 17:39:19 +01:00
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#ifndef CONFIG_USER_ONLY
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2022-04-20 15:26:02 +02:00
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static G_NORETURN
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void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr)
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2017-10-29 16:31:08 +01:00
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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CPUHPPAState *env = &cpu->env;
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cs->exception_index = EXCP_UNALIGN;
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if (env->psw & PSW_Q) {
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/* ??? Needs tweaking for hppa64. */
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env->cr[CR_IOR] = addr;
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env->cr[CR_ISR] = addr >> 32;
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}
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cpu_loop_exit_restore(cs, retaddr);
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}
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2021-02-04 17:39:19 +01:00
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#endif /* CONFIG_USER_ONLY */
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2017-10-29 16:31:08 +01:00
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2016-12-15 20:26:14 +01:00
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static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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acc->parent_realize(dev, errp);
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2017-12-29 02:50:14 +01:00
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#ifndef CONFIG_USER_ONLY
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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hppa_cpu_alarm_timer, cpu);
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}
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#endif
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2016-12-15 20:26:14 +01:00
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}
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static void hppa_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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HPPACPU *cpu = HPPA_CPU(obj);
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CPUHPPAState *env = &cpu->env;
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2019-03-28 22:26:22 +01:00
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cpu_set_cpustate_pointers(cpu);
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2017-10-11 22:19:11 +02:00
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cs->exception_index = -1;
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2016-12-15 20:26:14 +01:00
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cpu_hppa_loaded_fr0(env);
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2017-10-11 22:19:11 +02:00
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cpu_hppa_put_psw(env, PSW_W);
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2016-12-15 20:26:14 +01:00
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}
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2017-08-24 18:31:33 +02:00
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static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
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2016-12-15 20:26:14 +01:00
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{
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2017-08-24 18:31:33 +02:00
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return object_class_by_name(TYPE_HPPA_CPU);
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2016-12-15 20:26:14 +01:00
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}
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2021-05-17 12:51:31 +02:00
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#ifndef CONFIG_USER_ONLY
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps hppa_sysemu_ops = {
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2021-05-17 12:51:37 +02:00
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.get_phys_page_debug = hppa_cpu_get_phys_page_debug,
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2021-05-17 12:51:31 +02:00
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};
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#endif
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2021-02-04 17:39:23 +01:00
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#include "hw/core/tcg-cpu-ops.h"
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2021-02-28 00:21:17 +01:00
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static const struct TCGCPUOps hppa_tcg_ops = {
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2021-02-04 17:39:23 +01:00
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.initialize = hppa_translate_init,
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.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
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2022-10-24 12:13:57 +02:00
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.restore_state_to_opc = hppa_restore_state_to_opc,
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2021-02-04 17:39:23 +01:00
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#ifndef CONFIG_USER_ONLY
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2021-09-15 01:39:34 +02:00
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.tlb_fill = hppa_cpu_tlb_fill,
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2021-09-11 18:54:19 +02:00
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.cpu_exec_interrupt = hppa_cpu_exec_interrupt,
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2021-02-04 17:39:23 +01:00
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.do_interrupt = hppa_cpu_do_interrupt,
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.do_unaligned_access = hppa_cpu_do_unaligned_access,
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#endif /* !CONFIG_USER_ONLY */
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};
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2016-12-15 20:26:14 +01:00
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static void hppa_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
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2018-01-14 03:04:12 +01:00
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device_class_set_parent_realize(dc, hppa_cpu_realizefn,
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&acc->parent_realize);
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2016-12-15 20:26:14 +01:00
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2017-08-24 18:31:33 +02:00
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cc->class_by_name = hppa_cpu_class_by_name;
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2017-12-29 02:36:45 +01:00
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cc->has_work = hppa_cpu_has_work;
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2016-12-15 20:26:14 +01:00
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cc->dump_state = hppa_cpu_dump_state;
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cc->set_pc = hppa_cpu_set_pc;
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2022-09-30 19:31:21 +02:00
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cc->get_pc = hppa_cpu_get_pc;
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2016-12-15 20:26:14 +01:00
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cc->gdb_read_register = hppa_cpu_gdb_read_register;
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cc->gdb_write_register = hppa_cpu_gdb_write_register;
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2019-04-02 10:30:10 +02:00
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#ifndef CONFIG_USER_ONLY
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2017-11-20 11:06:04 +01:00
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dc->vmsd = &vmstate_hppa_cpu;
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2021-05-17 12:51:31 +02:00
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cc->sysemu_ops = &hppa_sysemu_ops;
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2017-10-01 22:11:45 +02:00
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#endif
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2016-12-15 20:26:14 +01:00
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cc->disas_set_info = hppa_cpu_disas_set_info;
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cc->gdb_num_core_regs = 128;
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2021-02-04 17:39:23 +01:00
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cc->tcg_ops = &hppa_tcg_ops;
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2016-12-15 20:26:14 +01:00
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}
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static const TypeInfo hppa_cpu_type_info = {
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.name = TYPE_HPPA_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(HPPACPU),
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.instance_init = hppa_cpu_initfn,
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.abstract = false,
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.class_size = sizeof(HPPACPUClass),
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.class_init = hppa_cpu_class_init,
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};
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static void hppa_cpu_register_types(void)
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{
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type_register_static(&hppa_cpu_type_info);
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}
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type_init(hppa_cpu_register_types)
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