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qemu-e2k/target/sparc/insns.decode

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target/sparc: Add decodetree infrastructure Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-01 23:56:04 +02:00
# SPDX-License-Identifier: LGPL-2.0+
#
# Sparc instruction decode definitions.
# Copyright (c) 2023 Richard Henderson <rth@twiddle.net>
target/sparc: Move SETHI to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 01:48:18 +02:00
##
## Major Opcodes 00 and 01 -- branches, call, and sethi.
##
target/sparc: Move BPcc and Bicc to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 00:57:34 +02:00
&bcc i a cond cc
BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc
Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0
target/sparc: Move FBPfcc and FBfcc to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-04 22:00:53 +02:00
FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc
FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0
target/sparc: Move BPcc and Bicc to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 00:57:34 +02:00
target/sparc: Move BPr to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 01:23:14 +02:00
%d16 20:s2 0:14
BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16
target/sparc: Move FBPfcc and FBfcc to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-04 22:00:53 +02:00
NCP 00 - ---- 111 ---------------------- # CBcc
target/sparc: Move SETHI to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 01:48:18 +02:00
SETHI 00 rd:5 100 i:22
target/sparc: Move CALL to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 00:11:00 +02:00
CALL 01 i:s30
target/sparc: Move Tcc to decodetree Use the new delay_exceptionv function in the implementation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 03:29:42 +02:00
target/sparc: Move WRASR to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 09:25:46 +02:00
##
## Major Opcode 10 -- integer, floating-point, vis, and system insns.
##
&r_r_ri rd rs1 rs2_or_imm imm:bool
@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0
target/sparc: Move basic arithmetic to decodetree Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 06:49:43 +02:00
&r_r_ri_cc rd rs1 rs2_or_imm imm:bool cc:bool
@r_r_ri_cc .. rd:5 . cc:1 .... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc
target/sparc: Move MULX to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 07:46:24 +02:00
@r_r_ri_cc0 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=0
target/sparc: Move TADD, TSUB, MULS to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 23:40:04 +02:00
@r_r_ri_cc1 .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_cc cc=1
target/sparc: Move basic arithmetic to decodetree Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 06:49:43 +02:00
target/sparc: Move RDASR, STBAR, MEMBAR to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 04:21:38 +02:00
{
[
STBAR 10 00000 101000 01111 0 0000000000000
MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4
RDCCR 10 rd:5 101000 00010 0 0000000000000
RDASI 10 rd:5 101000 00011 0 0000000000000
RDTICK 10 rd:5 101000 00100 0 0000000000000
RDPC 10 rd:5 101000 00101 0 0000000000000
RDFPRS 10 rd:5 101000 00110 0 0000000000000
RDASR17 10 rd:5 101000 10001 0 0000000000000
RDGSR 10 rd:5 101000 10011 0 0000000000000
RDSOFTINT 10 rd:5 101000 10110 0 0000000000000
RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000
RDSTICK 10 rd:5 101000 11000 0 0000000000000
RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000
RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000
]
# Before v8, all rs1 accepted; otherwise rs1==0.
RDY 10 rd:5 101000 rs1:5 0 0000000000000
}
target/sparc: Move WRASR to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 09:25:46 +02:00
{
[
WRY 10 00000 110000 ..... . ............. @n_r_ri
WRCCR 10 00010 110000 ..... . ............. @n_r_ri
WRASI 10 00011 110000 ..... . ............. @n_r_ri
WRFPRS 10 00110 110000 ..... . ............. @n_r_ri
{
WRGSR 10 10011 110000 ..... . ............. @n_r_ri
WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri
}
WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri
WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri
WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri
WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri
WRSTICK 10 11000 110000 ..... . ............. @n_r_ri
WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri
]
# Before v8, rs1==0 was WRY, and the rest executed as nop.
[
NOP_v7 10 ----- 110000 ----- 0 00000000 -----
NOP_v7 10 ----- 110000 ----- 1 -------- -----
]
}
target/sparc: Move RDPSR, RDHPR to decodetree Implement htstate in the obvious way. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/847 Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 05:34:14 +02:00
{
RDPSR 10 rd:5 101001 00000 0 0000000000000
RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000
}
RDHPR_htstate 10 rd:5 101001 00001 0 0000000000000
RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000
RDHPR_htba 10 rd:5 101001 00101 0 0000000000000
RDHPR_hver 10 rd:5 101001 00110 0 0000000000000
RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000
target/sparc: Move WRPSR, SAVED, RESTORED to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 16:38:42 +02:00
{
WRPSR 10 00000 110001 ..... . ............. @n_r_ri
SAVED 10 00000 110001 00000 0 0000000000000
}
RESTORED 10 00001 110001 00000 0 0000000000000
# UA2005 ALLCLEAN
# UA2005 OTHERW
# UA2005 NORMALW
# UA2005 INVALW
target/sparc: Move RDWIM, RDPR to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 06:21:43 +02:00
{
RDWIM 10 rd:5 101010 00000 0 0000000000000
RDPR_tpc 10 rd:5 101010 00000 0 0000000000000
}
RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000
RDPR_tstate 10 rd:5 101010 00010 0 0000000000000
RDPR_tt 10 rd:5 101010 00011 0 0000000000000
RDPR_tick 10 rd:5 101010 00100 0 0000000000000
RDPR_tba 10 rd:5 101010 00101 0 0000000000000
RDPR_pstate 10 rd:5 101010 00110 0 0000000000000
RDPR_tl 10 rd:5 101010 00111 0 0000000000000
RDPR_pil 10 rd:5 101010 01000 0 0000000000000
RDPR_cwp 10 rd:5 101010 01001 0 0000000000000
RDPR_cansave 10 rd:5 101010 01010 0 0000000000000
RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000
RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000
RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000
RDPR_wstate 10 rd:5 101010 01110 0 0000000000000
RDPR_gl 10 rd:5 101010 10000 0 0000000000000
RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000
RDPR_ver 10 rd:5 101010 11111 0 0000000000000
target/sparc: Move WRWIM, WRPR to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 22:31:20 +02:00
{
WRWIM 10 00000 110010 ..... . ............. @n_r_ri
WRPR_tpc 10 00000 110010 ..... . ............. @n_r_ri
}
WRPR_tnpc 10 00001 110010 ..... . ............. @n_r_ri
WRPR_tstate 10 00010 110010 ..... . ............. @n_r_ri
WRPR_tt 10 00011 110010 ..... . ............. @n_r_ri
WRPR_tick 10 00100 110010 ..... . ............. @n_r_ri
WRPR_tba 10 00101 110010 ..... . ............. @n_r_ri
WRPR_pstate 10 00110 110010 ..... . ............. @n_r_ri
WRPR_tl 10 00111 110010 ..... . ............. @n_r_ri
WRPR_pil 10 01000 110010 ..... . ............. @n_r_ri
WRPR_cwp 10 01001 110010 ..... . ............. @n_r_ri
WRPR_cansave 10 01010 110010 ..... . ............. @n_r_ri
WRPR_canrestore 10 01011 110010 ..... . ............. @n_r_ri
WRPR_cleanwin 10 01100 110010 ..... . ............. @n_r_ri
WRPR_otherwin 10 01101 110010 ..... . ............. @n_r_ri
WRPR_wstate 10 01110 110010 ..... . ............. @n_r_ri
WRPR_gl 10 10000 110010 ..... . ............. @n_r_ri
WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri
target/sparc: Move RDTBR, FLUSHW to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 06:29:10 +02:00
{
FLUSHW 10 00000 101011 00000 0 0000000000000
RDTBR 10 rd:5 101011 00000 0 0000000000000
}
target/sparc: Move WRTBR, WRHPR to decodetree Implement htstate in the obvious way. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 22:46:42 +02:00
{
WRTBR 10 00000 110011 ..... . ............. @n_r_ri
WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri
}
WRHPR_htstate 10 00001 110011 ..... . ............. @n_r_ri
WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri
WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri
WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri
target/sparc: Move basic arithmetic to decodetree Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 06:49:43 +02:00
ADD 10 ..... 0.0000 ..... . ............. @r_r_ri_cc
AND 10 ..... 0.0001 ..... . ............. @r_r_ri_cc
OR 10 ..... 0.0010 ..... . ............. @r_r_ri_cc
XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc
SUB 10 ..... 0.0100 ..... . ............. @r_r_ri_cc
ANDN 10 ..... 0.0101 ..... . ............. @r_r_ri_cc
ORN 10 ..... 0.0110 ..... . ............. @r_r_ri_cc
XORN 10 ..... 0.0111 ..... . ............. @r_r_ri_cc
target/sparc: Move ADDC to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-21 04:20:44 +02:00
ADDC 10 ..... 0.1000 ..... . ............. @r_r_ri_cc
target/sparc: Move SUBC to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 08:11:50 +02:00
SUBC 10 ..... 0.1100 ..... . ............. @r_r_ri_cc
target/sparc: Move basic arithmetic to decodetree Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 06:49:43 +02:00
target/sparc: Move MULX to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 07:46:24 +02:00
MULX 10 ..... 001001 ..... . ............. @r_r_ri_cc0
target/sparc: Move UMUL, SMUL to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 07:55:04 +02:00
UMUL 10 ..... 0.1010 ..... . ............. @r_r_ri_cc
SMUL 10 ..... 0.1011 ..... . ............. @r_r_ri_cc
target/sparc: Move TADD, TSUB, MULS to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 23:40:04 +02:00
MULScc 10 ..... 100100 ..... . ............. @r_r_ri_cc1
target/sparc: Move MULX to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 07:46:24 +02:00
target/sparc: Move UDIVX, SDIVX to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 08:34:14 +02:00
UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0
target/sparc: Move UDIV, SDIV to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 08:46:47 +02:00
UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc
SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc
target/sparc: Move UDIVX, SDIVX to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 08:34:14 +02:00
target/sparc: Move TADD, TSUB, MULS to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 23:40:04 +02:00
TADDcc 10 ..... 100000 ..... . ............. @r_r_ri_cc1
TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri_cc1
TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri_cc1
TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri_cc1
target/sparc: Move SLL, SRL, SRA to decodetree Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 23:48:10 +02:00
&shiftr rd rs1 rs2 x:bool
@shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr
SLL_r 10 ..... 100101 ..... 0 . 0000000 ..... @shiftr
SRL_r 10 ..... 100110 ..... 0 . 0000000 ..... @shiftr
SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr
&shifti rd rs1 i x:bool
@shifti .. rd:5 ...... rs1:5 . x:1 ...... i:6 &shifti
SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti
SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti
SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti
target/sparc: Move Tcc to decodetree Use the new delay_exceptionv function in the implementation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-02 03:29:42 +02:00
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
# For v7, the entire simm13 field is present, but masked to 7 bits.
# For v8, [12:7] are reserved. However, a compatibility note for
# the Tcc insn in the v9 manual suggests that the v8 reserved field
# was ignored and did not produce traps.
Tcc_i_v7 10 0 cond:4 111010 rs1:5 1 ------ i:7
# For v9, bits [12:11] are cc1 and cc0 (and cc0 must be 0).
# Bits [10:8] are reserved and the OSA2011 manual says they must be 0.
Tcc_i_v9 10 0 cond:4 111010 rs1:5 1 cc:1 0 000 i:8
}
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