2003-11-23 15:55:54 +01:00
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/*
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2005-07-02 22:59:34 +02:00
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* PowerPC emulation micro-operations for qemu.
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2003-11-23 15:55:54 +01:00
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*
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2007-03-07 09:32:30 +01:00
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* Copyright (c) 2003-2007 Jocelyn Mayer
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2003-11-23 15:55:54 +01:00
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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2004-04-12 22:39:29 +02:00
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//#define DEBUG_OP
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2003-11-23 15:55:54 +01:00
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#include "config.h"
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#include "exec.h"
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2007-03-07 09:32:30 +01:00
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#include "op_helper.h"
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2003-11-23 15:55:54 +01:00
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2007-03-07 09:32:30 +01:00
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/* XXX: this is to be suppressed */
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2003-11-23 15:55:54 +01:00
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#define regs (env)
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#define Ts0 (int32_t)T0
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#define Ts1 (int32_t)T1
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#define Ts2 (int32_t)T2
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2003-11-23 17:58:08 +01:00
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#define FT0 (env->ft0)
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2004-01-04 15:57:11 +01:00
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#define FT1 (env->ft1)
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#define FT2 (env->ft2)
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2007-03-07 09:32:30 +01:00
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/* XXX: this is to be suppressed... */
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#define PPC_OP(name) void OPPROTO glue(op_, name)(void)
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2003-11-23 15:55:54 +01:00
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2003-11-23 17:58:08 +01:00
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#define REG 0
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#include "op_template.h"
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#define REG 1
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#include "op_template.h"
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#define REG 2
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#include "op_template.h"
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#define REG 3
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#include "op_template.h"
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#define REG 4
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#include "op_template.h"
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#define REG 5
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#include "op_template.h"
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#define REG 6
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#include "op_template.h"
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#define REG 7
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#include "op_template.h"
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#define REG 8
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#include "op_template.h"
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#define REG 9
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#include "op_template.h"
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#define REG 10
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#include "op_template.h"
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#define REG 11
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#include "op_template.h"
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#define REG 12
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#include "op_template.h"
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#define REG 13
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#include "op_template.h"
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#define REG 14
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#include "op_template.h"
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#define REG 15
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#include "op_template.h"
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#define REG 16
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#include "op_template.h"
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#define REG 17
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#include "op_template.h"
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#define REG 18
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#include "op_template.h"
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#define REG 19
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#include "op_template.h"
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#define REG 20
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#include "op_template.h"
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#define REG 21
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#include "op_template.h"
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#define REG 22
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#include "op_template.h"
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#define REG 23
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#include "op_template.h"
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#define REG 24
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#include "op_template.h"
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#define REG 25
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#include "op_template.h"
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#define REG 26
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#include "op_template.h"
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#define REG 27
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#include "op_template.h"
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#define REG 28
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#include "op_template.h"
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#define REG 29
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#include "op_template.h"
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#define REG 30
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#include "op_template.h"
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#define REG 31
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#include "op_template.h"
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2005-07-02 22:59:34 +02:00
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/* PowerPC state maintenance operations */
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2003-11-23 15:55:54 +01:00
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/* set_Rc0 */
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PPC_OP(set_Rc0)
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{
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2007-03-07 09:32:30 +01:00
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env->crf[0] = T0 | xer_ov;
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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2004-01-04 15:57:11 +01:00
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/* Set Rc1 (for floating point arithmetic) */
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PPC_OP(set_Rc1)
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{
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env->crf[1] = regs->fpscr[7];
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RETURN();
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}
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2004-01-04 23:58:38 +01:00
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/* Constants load */
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2007-03-07 09:32:30 +01:00
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void OPPROTO op_reset_T0 (void)
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{
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T0 = 0;
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RETURN();
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}
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2003-11-23 15:55:54 +01:00
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PPC_OP(set_T0)
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{
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T0 = PARAM(1);
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RETURN();
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}
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PPC_OP(set_T1)
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{
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T1 = PARAM(1);
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RETURN();
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}
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2007-03-07 09:32:30 +01:00
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#if 0 // unused
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2003-11-23 15:55:54 +01:00
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PPC_OP(set_T2)
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{
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T2 = PARAM(1);
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RETURN();
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}
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2007-03-07 09:32:30 +01:00
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#endif
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2003-11-23 15:55:54 +01:00
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2007-03-07 09:32:30 +01:00
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void OPPROTO op_move_T1_T0 (void)
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2003-11-23 15:55:54 +01:00
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{
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2007-03-07 09:32:30 +01:00
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T1 = T0;
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RETURN();
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2004-01-04 23:58:38 +01:00
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}
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2007-03-07 09:32:30 +01:00
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/* Generate exceptions */
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PPC_OP(raise_exception_err)
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2004-01-04 23:58:38 +01:00
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{
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2007-03-07 09:32:30 +01:00
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do_raise_exception_err(PARAM(1), PARAM(2));
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2004-01-04 23:58:38 +01:00
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}
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2004-05-21 14:59:32 +02:00
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PPC_OP(update_nip)
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2004-01-04 23:58:38 +01:00
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{
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2004-02-21 15:10:04 +01:00
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env->nip = PARAM(1);
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2007-03-07 09:32:30 +01:00
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RETURN();
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2004-01-04 23:58:38 +01:00
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}
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2006-05-22 23:50:20 +02:00
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PPC_OP(debug)
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{
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do_raise_exception(EXCP_DEBUG);
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}
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2004-01-04 23:58:38 +01:00
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2007-03-07 09:32:30 +01:00
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PPC_OP(exit_tb)
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2004-01-04 23:58:38 +01:00
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{
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2007-03-07 09:32:30 +01:00
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EXIT_TB();
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2004-01-04 23:58:38 +01:00
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}
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2007-03-07 09:32:30 +01:00
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/* Load/store special registers */
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PPC_OP(load_cr)
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2004-01-04 23:58:38 +01:00
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{
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2007-03-07 09:32:30 +01:00
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do_load_cr();
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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2007-03-07 09:32:30 +01:00
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PPC_OP(store_cr)
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2003-11-23 15:55:54 +01:00
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{
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2007-03-07 09:32:30 +01:00
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do_store_cr(PARAM(1));
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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2007-03-07 09:32:30 +01:00
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void OPPROTO op_load_cro (void)
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2003-11-23 15:55:54 +01:00
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{
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2007-03-07 09:32:30 +01:00
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T0 = env->crf[PARAM1];
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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2007-03-07 09:32:30 +01:00
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void OPPROTO op_store_cro (void)
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2003-11-23 15:55:54 +01:00
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{
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2007-03-07 09:32:30 +01:00
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env->crf[PARAM1] = T0;
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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PPC_OP(load_xer_cr)
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{
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T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1);
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RETURN();
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}
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PPC_OP(clear_xer_cr)
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{
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xer_so = 0;
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xer_ov = 0;
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xer_ca = 0;
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RETURN();
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}
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PPC_OP(load_xer_bc)
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{
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2004-01-04 23:58:38 +01:00
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T1 = xer_bc;
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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2007-03-07 09:32:30 +01:00
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void OPPROTO op_store_xer_bc (void)
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{
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xer_bc = T0;
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RETURN();
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}
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2003-11-23 15:55:54 +01:00
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PPC_OP(load_xer)
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{
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2007-03-07 09:32:30 +01:00
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do_load_xer();
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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PPC_OP(store_xer)
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{
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2007-03-07 09:32:30 +01:00
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do_store_xer();
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RETURN();
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}
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#if !defined(CONFIG_USER_ONLY)
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/* Segment registers load and store */
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PPC_OP(load_sr)
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{
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T0 = regs->sr[T1];
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RETURN();
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}
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PPC_OP(store_sr)
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{
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do_store_sr(env, T1, T0);
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RETURN();
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}
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PPC_OP(load_sdr1)
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{
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T0 = regs->sdr1;
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RETURN();
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}
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PPC_OP(store_sdr1)
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{
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do_store_sdr1(env, T0);
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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PPC_OP(load_msr)
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{
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2005-07-02 22:59:34 +02:00
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T0 = do_load_msr(env);
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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PPC_OP(store_msr)
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{
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2005-07-02 22:59:34 +02:00
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do_store_msr(env, T0);
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2004-01-04 23:58:38 +01:00
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RETURN();
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}
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2007-03-07 09:32:30 +01:00
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#endif
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2004-01-04 23:58:38 +01:00
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/* SPR */
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PPC_OP(load_spr)
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{
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T0 = regs->spr[PARAM(1)];
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RETURN();
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}
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PPC_OP(store_spr)
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{
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regs->spr[PARAM(1)] = T0;
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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PPC_OP(load_lr)
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{
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2004-01-04 23:58:38 +01:00
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T0 = regs->lr;
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RETURN();
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}
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PPC_OP(store_lr)
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{
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regs->lr = T0;
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RETURN();
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}
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PPC_OP(load_ctr)
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{
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T0 = regs->ctr;
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RETURN();
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}
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PPC_OP(store_ctr)
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{
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regs->ctr = T0;
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RETURN();
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}
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2004-05-21 14:59:32 +02:00
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PPC_OP(load_tbl)
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2004-01-04 23:58:38 +01:00
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{
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2004-05-21 14:59:32 +02:00
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T0 = cpu_ppc_load_tbl(regs);
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2004-01-04 23:58:38 +01:00
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RETURN();
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}
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2004-05-21 14:59:32 +02:00
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PPC_OP(load_tbu)
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2004-01-04 23:58:38 +01:00
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{
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2004-05-21 14:59:32 +02:00
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T0 = cpu_ppc_load_tbu(regs);
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2004-01-04 23:58:38 +01:00
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RETURN();
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}
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2007-03-07 09:32:30 +01:00
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#if !defined(CONFIG_USER_ONLY)
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2004-05-21 14:59:32 +02:00
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PPC_OP(store_tbl)
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2004-01-04 23:58:38 +01:00
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{
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2004-05-21 14:59:32 +02:00
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cpu_ppc_store_tbl(regs, T0);
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2003-11-23 15:55:54 +01:00
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RETURN();
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}
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2004-05-21 14:59:32 +02:00
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PPC_OP(store_tbu)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2004-05-21 14:59:32 +02:00
|
|
|
cpu_ppc_store_tbu(regs, T0);
|
2004-01-04 23:58:38 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2004-05-21 14:59:32 +02:00
|
|
|
PPC_OP(load_decr)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2004-05-21 14:59:32 +02:00
|
|
|
T0 = cpu_ppc_load_decr(regs);
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
2004-05-21 14:59:32 +02:00
|
|
|
|
|
|
|
PPC_OP(store_decr)
|
|
|
|
{
|
|
|
|
cpu_ppc_store_decr(regs, T0);
|
2004-01-04 23:58:38 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(load_ibat)
|
|
|
|
{
|
|
|
|
T0 = regs->IBAT[PARAM(1)][PARAM(2)];
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_store_ibatu (void)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2005-07-02 22:59:34 +02:00
|
|
|
do_store_ibatu(env, PARAM1, T0);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_store_ibatl (void)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
|
|
|
#if 1
|
|
|
|
env->IBAT[1][PARAM1] = T0;
|
|
|
|
#else
|
|
|
|
do_store_ibatl(env, PARAM1, T0);
|
|
|
|
#endif
|
|
|
|
RETURN();
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(load_dbat)
|
|
|
|
{
|
|
|
|
T0 = regs->DBAT[PARAM(1)][PARAM(2)];
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_store_dbatu (void)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
|
|
|
do_store_dbatu(env, PARAM1, T0);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_store_dbatl (void)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2005-07-02 22:59:34 +02:00
|
|
|
#if 1
|
|
|
|
env->DBAT[1][PARAM1] = T0;
|
|
|
|
#else
|
|
|
|
do_store_dbatl(env, PARAM1, T0);
|
|
|
|
#endif
|
|
|
|
RETURN();
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
2007-03-07 09:32:30 +01:00
|
|
|
#endif /* !defined(CONFIG_USER_ONLY) */
|
2004-01-04 23:58:38 +01:00
|
|
|
|
2004-01-04 15:57:11 +01:00
|
|
|
/* FPSCR */
|
|
|
|
PPC_OP(load_fpscr)
|
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
do_load_fpscr();
|
2004-01-04 15:57:11 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(store_fpscr)
|
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
do_store_fpscr(PARAM1);
|
2004-01-04 15:57:11 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(reset_scrfx)
|
|
|
|
{
|
|
|
|
regs->fpscr[7] &= ~0x8;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2003-11-23 15:55:54 +01:00
|
|
|
/* crf operations */
|
|
|
|
PPC_OP(getbit_T0)
|
|
|
|
{
|
|
|
|
T0 = (T0 >> PARAM(1)) & 1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(getbit_T1)
|
|
|
|
{
|
|
|
|
T1 = (T1 >> PARAM(1)) & 1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(setcrfbit)
|
|
|
|
{
|
|
|
|
T1 = (T1 & PARAM(1)) | (T0 << PARAM(2));
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Branch */
|
2004-01-04 23:58:38 +01:00
|
|
|
#define EIP regs->nip
|
|
|
|
|
2004-02-21 16:35:00 +01:00
|
|
|
PPC_OP(setlr)
|
|
|
|
{
|
|
|
|
regs->lr = PARAM1;
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
2005-10-30 22:39:19 +01:00
|
|
|
PPC_OP(goto_tb0)
|
2004-02-21 16:35:00 +01:00
|
|
|
{
|
2005-10-30 22:39:19 +01:00
|
|
|
GOTO_TB(op_goto_tb0, PARAM1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(goto_tb1)
|
|
|
|
{
|
|
|
|
GOTO_TB(op_goto_tb1, PARAM1, 1);
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(b_T1)
|
|
|
|
{
|
2005-06-05 00:19:02 +02:00
|
|
|
regs->nip = T1 & ~3;
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
2005-10-30 22:39:19 +01:00
|
|
|
PPC_OP(jz_T0)
|
2004-02-21 16:35:00 +01:00
|
|
|
{
|
2005-10-30 22:39:19 +01:00
|
|
|
if (!T0)
|
|
|
|
GOTO_LABEL_PARAM(1);
|
2004-02-21 16:35:00 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(btest_T1)
|
|
|
|
{
|
|
|
|
if (T0) {
|
|
|
|
regs->nip = T1 & ~3;
|
|
|
|
} else {
|
|
|
|
regs->nip = PARAM1;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(movl_T1_ctr)
|
|
|
|
{
|
|
|
|
T1 = regs->ctr;
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(movl_T1_lr)
|
|
|
|
{
|
|
|
|
T1 = regs->lr;
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* tests with result in T0 */
|
|
|
|
|
|
|
|
PPC_OP(test_ctr)
|
|
|
|
{
|
2004-02-22 14:41:47 +01:00
|
|
|
T0 = regs->ctr;
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(test_ctr_true)
|
|
|
|
{
|
|
|
|
T0 = (regs->ctr != 0 && (T0 & PARAM(1)) != 0);
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(test_ctr_false)
|
|
|
|
{
|
|
|
|
T0 = (regs->ctr != 0 && (T0 & PARAM(1)) == 0);
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(test_ctrz)
|
|
|
|
{
|
|
|
|
T0 = (regs->ctr == 0);
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(test_ctrz_true)
|
|
|
|
{
|
|
|
|
T0 = (regs->ctr == 0 && (T0 & PARAM(1)) != 0);
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(test_ctrz_false)
|
|
|
|
{
|
|
|
|
T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0);
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(test_true)
|
|
|
|
{
|
2004-02-22 14:41:47 +01:00
|
|
|
T0 = (T0 & PARAM(1));
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(test_false)
|
|
|
|
{
|
|
|
|
T0 = ((T0 & PARAM(1)) == 0);
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2004-02-21 16:35:00 +01:00
|
|
|
}
|
2003-11-23 15:55:54 +01:00
|
|
|
|
|
|
|
/* CTR maintenance */
|
|
|
|
PPC_OP(dec_ctr)
|
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
regs->ctr--;
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*** Integer arithmetic ***/
|
|
|
|
/* add */
|
|
|
|
PPC_OP(add)
|
|
|
|
{
|
|
|
|
T0 += T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_addo (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_addo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* add carrying */
|
|
|
|
PPC_OP(addc)
|
|
|
|
{
|
|
|
|
T2 = T0;
|
|
|
|
T0 += T1;
|
|
|
|
if (T0 < T2) {
|
|
|
|
xer_ca = 1;
|
|
|
|
} else {
|
|
|
|
xer_ca = 0;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_addco (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_addco();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* add extended */
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_adde (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_adde();
|
2007-03-07 09:32:30 +01:00
|
|
|
RETURN();
|
2003-11-23 15:55:54 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(addeo)
|
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_addeo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* add immediate */
|
|
|
|
PPC_OP(addi)
|
|
|
|
{
|
|
|
|
T0 += PARAM(1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* add immediate carrying */
|
|
|
|
PPC_OP(addic)
|
|
|
|
{
|
|
|
|
T1 = T0;
|
|
|
|
T0 += PARAM(1);
|
|
|
|
if (T0 < T1) {
|
|
|
|
xer_ca = 1;
|
|
|
|
} else {
|
|
|
|
xer_ca = 0;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* add to minus one extended */
|
|
|
|
PPC_OP(addme)
|
|
|
|
{
|
|
|
|
T1 = T0;
|
|
|
|
T0 += xer_ca + (-1);
|
|
|
|
if (T1 != 0)
|
|
|
|
xer_ca = 1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_addmeo (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_addmeo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* add to zero extended */
|
|
|
|
PPC_OP(addze)
|
|
|
|
{
|
|
|
|
T1 = T0;
|
|
|
|
T0 += xer_ca;
|
|
|
|
if (T0 < T1) {
|
|
|
|
xer_ca = 1;
|
|
|
|
} else {
|
|
|
|
xer_ca = 0;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_addzeo (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_addzeo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* divide word */
|
|
|
|
PPC_OP(divw)
|
|
|
|
{
|
|
|
|
if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) {
|
2005-02-16 00:06:19 +01:00
|
|
|
T0 = (int32_t)((-1) * (T0 >> 31));
|
2003-11-23 15:55:54 +01:00
|
|
|
} else {
|
2005-02-16 00:06:19 +01:00
|
|
|
T0 = (Ts0 / Ts1);
|
2003-11-23 15:55:54 +01:00
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_divwo (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_divwo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* divide word unsigned */
|
|
|
|
PPC_OP(divwu)
|
|
|
|
{
|
|
|
|
if (T1 == 0) {
|
|
|
|
T0 = 0;
|
|
|
|
} else {
|
|
|
|
T0 /= T1;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_divwuo (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_divwuo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* multiply high word */
|
|
|
|
PPC_OP(mulhw)
|
|
|
|
{
|
2005-02-16 00:06:19 +01:00
|
|
|
T0 = ((int64_t)Ts0 * (int64_t)Ts1) >> 32;
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* multiply high word unsigned */
|
|
|
|
PPC_OP(mulhwu)
|
|
|
|
{
|
|
|
|
T0 = ((uint64_t)T0 * (uint64_t)T1) >> 32;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* multiply low immediate */
|
|
|
|
PPC_OP(mulli)
|
|
|
|
{
|
2005-02-16 00:06:19 +01:00
|
|
|
T0 = (Ts0 * SPARAM(1));
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* multiply low word */
|
|
|
|
PPC_OP(mullw)
|
|
|
|
{
|
|
|
|
T0 *= T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_mullwo (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_mullwo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* negate */
|
|
|
|
PPC_OP(neg)
|
|
|
|
{
|
|
|
|
if (T0 != 0x80000000) {
|
2005-02-16 00:06:19 +01:00
|
|
|
T0 = -Ts0;
|
2003-11-23 15:55:54 +01:00
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_nego (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_nego();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* substract from */
|
|
|
|
PPC_OP(subf)
|
|
|
|
{
|
|
|
|
T0 = T1 - T0;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_subfo (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_subfo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* substract from carrying */
|
|
|
|
PPC_OP(subfc)
|
|
|
|
{
|
|
|
|
T0 = T1 - T0;
|
|
|
|
if (T0 <= T1) {
|
|
|
|
xer_ca = 1;
|
|
|
|
} else {
|
|
|
|
xer_ca = 0;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_subfco (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_subfco();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* substract from extended */
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_subfe (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_subfe();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
PPC_OP(subfeo)
|
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_subfeo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* substract from immediate carrying */
|
|
|
|
PPC_OP(subfic)
|
|
|
|
{
|
|
|
|
T0 = PARAM(1) + ~T0 + 1;
|
|
|
|
if (T0 <= PARAM(1)) {
|
|
|
|
xer_ca = 1;
|
|
|
|
} else {
|
|
|
|
xer_ca = 0;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* substract from minus one extended */
|
|
|
|
PPC_OP(subfme)
|
|
|
|
{
|
|
|
|
T0 = ~T0 + xer_ca - 1;
|
|
|
|
|
|
|
|
if (T0 != -1)
|
|
|
|
xer_ca = 1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_subfmeo (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_subfmeo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* substract from zero extended */
|
|
|
|
PPC_OP(subfze)
|
|
|
|
{
|
|
|
|
T1 = ~T0;
|
|
|
|
T0 = T1 + xer_ca;
|
|
|
|
if (T0 < T1) {
|
|
|
|
xer_ca = 1;
|
|
|
|
} else {
|
|
|
|
xer_ca = 0;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_subfzeo (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_subfzeo();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*** Integer comparison ***/
|
|
|
|
/* compare */
|
|
|
|
PPC_OP(cmp)
|
|
|
|
{
|
|
|
|
if (Ts0 < Ts1) {
|
|
|
|
T0 = 0x08;
|
|
|
|
} else if (Ts0 > Ts1) {
|
|
|
|
T0 = 0x04;
|
|
|
|
} else {
|
|
|
|
T0 = 0x02;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* compare immediate */
|
|
|
|
PPC_OP(cmpi)
|
|
|
|
{
|
|
|
|
if (Ts0 < SPARAM(1)) {
|
|
|
|
T0 = 0x08;
|
|
|
|
} else if (Ts0 > SPARAM(1)) {
|
|
|
|
T0 = 0x04;
|
|
|
|
} else {
|
|
|
|
T0 = 0x02;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* compare logical */
|
|
|
|
PPC_OP(cmpl)
|
|
|
|
{
|
|
|
|
if (T0 < T1) {
|
|
|
|
T0 = 0x08;
|
|
|
|
} else if (T0 > T1) {
|
|
|
|
T0 = 0x04;
|
|
|
|
} else {
|
|
|
|
T0 = 0x02;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* compare logical immediate */
|
|
|
|
PPC_OP(cmpli)
|
|
|
|
{
|
|
|
|
if (T0 < PARAM(1)) {
|
|
|
|
T0 = 0x08;
|
|
|
|
} else if (T0 > PARAM(1)) {
|
|
|
|
T0 = 0x04;
|
|
|
|
} else {
|
|
|
|
T0 = 0x02;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*** Integer logical ***/
|
|
|
|
/* and */
|
|
|
|
PPC_OP(and)
|
|
|
|
{
|
|
|
|
T0 &= T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* andc */
|
|
|
|
PPC_OP(andc)
|
|
|
|
{
|
|
|
|
T0 &= ~T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* andi. */
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_andi_T0 (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
|
|
|
T0 &= PARAM(1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_andi_T1 (void)
|
|
|
|
{
|
|
|
|
T1 &= PARAM1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2003-11-23 15:55:54 +01:00
|
|
|
/* count leading zero */
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_cntlzw (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
int cnt;
|
|
|
|
|
|
|
|
cnt = 0;
|
|
|
|
if (!(T0 & 0xFFFF0000UL)) {
|
|
|
|
cnt += 16;
|
|
|
|
T0 <<= 16;
|
|
|
|
}
|
|
|
|
if (!(T0 & 0xFF000000UL)) {
|
|
|
|
cnt += 8;
|
|
|
|
T0 <<= 8;
|
|
|
|
}
|
|
|
|
if (!(T0 & 0xF0000000UL)) {
|
|
|
|
cnt += 4;
|
|
|
|
T0 <<= 4;
|
|
|
|
}
|
|
|
|
if (!(T0 & 0xC0000000UL)) {
|
|
|
|
cnt += 2;
|
|
|
|
T0 <<= 2;
|
|
|
|
}
|
|
|
|
if (!(T0 & 0x80000000UL)) {
|
|
|
|
cnt++;
|
|
|
|
T0 <<= 1;
|
|
|
|
}
|
|
|
|
if (!(T0 & 0x80000000UL)) {
|
|
|
|
cnt++;
|
|
|
|
}
|
|
|
|
T0 = cnt;
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* eqv */
|
|
|
|
PPC_OP(eqv)
|
|
|
|
{
|
|
|
|
T0 = ~(T0 ^ T1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* extend sign byte */
|
|
|
|
PPC_OP(extsb)
|
|
|
|
{
|
2005-02-16 00:06:19 +01:00
|
|
|
T0 = (int32_t)((int8_t)(Ts0));
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* extend sign half word */
|
|
|
|
PPC_OP(extsh)
|
|
|
|
{
|
2005-02-16 00:06:19 +01:00
|
|
|
T0 = (int32_t)((int16_t)(Ts0));
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* nand */
|
|
|
|
PPC_OP(nand)
|
|
|
|
{
|
|
|
|
T0 = ~(T0 & T1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* nor */
|
|
|
|
PPC_OP(nor)
|
|
|
|
{
|
|
|
|
T0 = ~(T0 | T1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* or */
|
|
|
|
PPC_OP(or)
|
|
|
|
{
|
|
|
|
T0 |= T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* orc */
|
|
|
|
PPC_OP(orc)
|
|
|
|
{
|
|
|
|
T0 |= ~T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ori */
|
|
|
|
PPC_OP(ori)
|
|
|
|
{
|
|
|
|
T0 |= PARAM(1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* xor */
|
|
|
|
PPC_OP(xor)
|
|
|
|
{
|
|
|
|
T0 ^= T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* xori */
|
|
|
|
PPC_OP(xori)
|
|
|
|
{
|
|
|
|
T0 ^= PARAM(1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*** Integer rotate ***/
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_rotl32_T0_T1 (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
T0 = rotl32(T0, T1 & 0x1F);
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_rotli32_T0 (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
T0 = rotl32(T0, PARAM1);
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/*** Integer shift ***/
|
|
|
|
/* shift left word */
|
|
|
|
PPC_OP(slw)
|
|
|
|
{
|
|
|
|
if (T1 & 0x20) {
|
|
|
|
T0 = 0;
|
|
|
|
} else {
|
|
|
|
T0 = T0 << T1;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* shift right algebraic word */
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_sraw (void)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
do_sraw();
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* shift right algebraic word immediate */
|
|
|
|
PPC_OP(srawi)
|
|
|
|
{
|
2005-02-16 00:06:19 +01:00
|
|
|
T1 = T0;
|
|
|
|
T0 = (Ts0 >> PARAM(1));
|
2003-11-23 15:55:54 +01:00
|
|
|
if (Ts1 < 0 && (Ts1 & PARAM(2)) != 0) {
|
|
|
|
xer_ca = 1;
|
|
|
|
} else {
|
|
|
|
xer_ca = 0;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* shift right word */
|
|
|
|
PPC_OP(srw)
|
|
|
|
{
|
|
|
|
if (T1 & 0x20) {
|
|
|
|
T0 = 0;
|
|
|
|
} else {
|
|
|
|
T0 = T0 >> T1;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_sl_T0_T1 (void)
|
|
|
|
{
|
|
|
|
T0 = T0 << T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_sli_T0 (void)
|
|
|
|
{
|
|
|
|
T0 = T0 << PARAM1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_srl_T0_T1 (void)
|
|
|
|
{
|
|
|
|
T0 = T0 >> T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_srli_T0 (void)
|
|
|
|
{
|
|
|
|
T0 = T0 >> PARAM1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_srli_T1 (void)
|
|
|
|
{
|
|
|
|
T1 = T1 >> PARAM1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2003-11-23 15:55:54 +01:00
|
|
|
/*** Floating-Point arithmetic ***/
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fadd - fadd. */
|
|
|
|
PPC_OP(fadd)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
FT0 = float64_add(FT0, FT1, &env->fp_status);
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fsub - fsub. */
|
|
|
|
PPC_OP(fsub)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
FT0 = float64_sub(FT0, FT1, &env->fp_status);
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fmul - fmul. */
|
|
|
|
PPC_OP(fmul)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
FT0 = float64_mul(FT0, FT1, &env->fp_status);
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fdiv - fdiv. */
|
|
|
|
PPC_OP(fdiv)
|
2003-11-23 15:55:54 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
FT0 = float64_div(FT0, FT1, &env->fp_status);
|
2003-11-23 15:55:54 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
2003-11-23 17:58:08 +01:00
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fsqrt - fsqrt. */
|
|
|
|
PPC_OP(fsqrt)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
do_fsqrt();
|
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fres - fres. */
|
|
|
|
PPC_OP(fres)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
do_fres();
|
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* frsqrte - frsqrte. */
|
|
|
|
PPC_OP(frsqrte)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2005-03-13 18:01:22 +01:00
|
|
|
do_frsqrte();
|
2004-01-04 23:58:38 +01:00
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fsel - fsel. */
|
|
|
|
PPC_OP(fsel)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
do_fsel();
|
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/*** Floating-Point multiply-and-add ***/
|
|
|
|
/* fmadd - fmadd. */
|
|
|
|
PPC_OP(fmadd)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
FT0 = float64_mul(FT0, FT1, &env->fp_status);
|
|
|
|
FT0 = float64_add(FT0, FT2, &env->fp_status);
|
2004-01-04 23:58:38 +01:00
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fmsub - fmsub. */
|
|
|
|
PPC_OP(fmsub)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
FT0 = float64_mul(FT0, FT1, &env->fp_status);
|
|
|
|
FT0 = float64_sub(FT0, FT2, &env->fp_status);
|
2004-01-04 23:58:38 +01:00
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fnmadd - fnmadd. - fnmadds - fnmadds. */
|
|
|
|
PPC_OP(fnmadd)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2004-05-24 00:18:12 +02:00
|
|
|
do_fnmadd();
|
2004-01-04 23:58:38 +01:00
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fnmsub - fnmsub. */
|
|
|
|
PPC_OP(fnmsub)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2004-05-24 00:18:12 +02:00
|
|
|
do_fnmsub();
|
2004-01-04 23:58:38 +01:00
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/*** Floating-Point round & convert ***/
|
|
|
|
/* frsp - frsp. */
|
|
|
|
PPC_OP(frsp)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
FT0 = float64_to_float32(FT0, &env->fp_status);
|
2004-01-04 23:58:38 +01:00
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fctiw - fctiw. */
|
|
|
|
PPC_OP(fctiw)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
do_fctiw();
|
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fctiwz - fctiwz. */
|
|
|
|
PPC_OP(fctiwz)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
do_fctiwz();
|
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/*** Floating-Point compare ***/
|
|
|
|
/* fcmpu */
|
|
|
|
PPC_OP(fcmpu)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
do_fcmpu();
|
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fcmpo */
|
|
|
|
PPC_OP(fcmpo)
|
2004-01-04 15:57:11 +01:00
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
do_fcmpo();
|
|
|
|
RETURN();
|
2004-01-04 15:57:11 +01:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/*** Floating-point move ***/
|
|
|
|
/* fabs */
|
|
|
|
PPC_OP(fabs)
|
2004-01-04 15:57:11 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
FT0 = float64_abs(FT0);
|
2004-01-04 15:57:11 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fnabs */
|
|
|
|
PPC_OP(fnabs)
|
2004-01-04 15:57:11 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
FT0 = float64_abs(FT0);
|
|
|
|
FT0 = float64_chs(FT0);
|
2004-01-04 15:57:11 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* fneg */
|
|
|
|
PPC_OP(fneg)
|
2004-01-04 15:57:11 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
FT0 = float64_chs(FT0);
|
2004-01-04 15:57:11 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* Load and store */
|
|
|
|
#define MEMSUFFIX _raw
|
2007-03-07 09:32:30 +01:00
|
|
|
#include "op_helper.h"
|
2004-01-04 23:58:38 +01:00
|
|
|
#include "op_mem.h"
|
2004-04-12 22:39:29 +02:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2004-01-04 23:58:38 +01:00
|
|
|
#define MEMSUFFIX _user
|
2007-03-07 09:32:30 +01:00
|
|
|
#include "op_helper.h"
|
2004-01-04 23:58:38 +01:00
|
|
|
#include "op_mem.h"
|
|
|
|
#define MEMSUFFIX _kernel
|
2007-03-07 09:32:30 +01:00
|
|
|
#include "op_helper.h"
|
2004-01-04 23:58:38 +01:00
|
|
|
#include "op_mem.h"
|
|
|
|
#endif
|
|
|
|
|
2004-05-24 00:18:12 +02:00
|
|
|
/* Special op to check and maybe clear reservation */
|
|
|
|
PPC_OP(check_reservation)
|
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
if ((uint32_t)env->reserve == (uint32_t)(T0 & ~0x00000003))
|
|
|
|
env->reserve = -1;
|
2004-05-24 00:18:12 +02:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* Return from interrupt */
|
2007-03-07 09:32:30 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
void OPPROTO op_rfi (void)
|
2003-11-23 17:58:08 +01:00
|
|
|
{
|
2005-07-05 00:17:05 +02:00
|
|
|
do_rfi();
|
2004-01-04 15:57:11 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
2007-03-07 09:32:30 +01:00
|
|
|
#endif
|
2004-01-04 15:57:11 +01:00
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/* Trap word */
|
2007-03-07 09:32:30 +01:00
|
|
|
void OPPROTO op_tw (void)
|
2004-01-04 15:57:11 +01:00
|
|
|
{
|
2007-03-07 09:32:30 +01:00
|
|
|
do_tw(PARAM1);
|
2004-01-04 15:57:11 +01:00
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Instruction cache block invalidate */
|
2004-01-04 23:58:38 +01:00
|
|
|
PPC_OP(icbi)
|
2004-01-04 15:57:11 +01:00
|
|
|
{
|
|
|
|
do_icbi();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
2004-01-04 23:58:38 +01:00
|
|
|
/* tlbia */
|
|
|
|
PPC_OP(tlbia)
|
2004-01-04 15:57:11 +01:00
|
|
|
{
|
2004-01-04 23:58:38 +01:00
|
|
|
do_tlbia();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* tlbie */
|
|
|
|
PPC_OP(tlbie)
|
|
|
|
{
|
|
|
|
do_tlbie();
|
2004-01-04 15:57:11 +01:00
|
|
|
RETURN();
|
2003-11-23 17:58:08 +01:00
|
|
|
}
|
2007-03-07 09:32:30 +01:00
|
|
|
#endif
|
2005-07-02 22:59:34 +02:00
|
|
|
|
2007-03-07 09:32:30 +01:00
|
|
|
/* PowerPC 602/603/755 software TLB load instructions */
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
void OPPROTO op_6xx_tlbld (void)
|
|
|
|
{
|
|
|
|
do_load_6xx_tlb(0);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_6xx_tlbli (void)
|
|
|
|
{
|
|
|
|
do_load_6xx_tlb(1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* 601 specific */
|
|
|
|
uint32_t cpu_ppc601_load_rtcl (CPUState *env);
|
|
|
|
void OPPROTO op_load_601_rtcl (void)
|
|
|
|
{
|
|
|
|
T0 = cpu_ppc601_load_rtcl(env);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
uint32_t cpu_ppc601_load_rtcu (CPUState *env);
|
|
|
|
void OPPROTO op_load_601_rtcu (void)
|
|
|
|
{
|
|
|
|
T0 = cpu_ppc601_load_rtcu(env);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value);
|
|
|
|
void OPPROTO op_store_601_rtcl (void)
|
|
|
|
{
|
|
|
|
cpu_ppc601_store_rtcl(env, T0);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value);
|
|
|
|
void OPPROTO op_store_601_rtcu (void)
|
|
|
|
{
|
|
|
|
cpu_ppc601_store_rtcu(env, T0);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_load_601_bat (void)
|
|
|
|
{
|
|
|
|
T0 = env->IBAT[PARAM1][PARAM2];
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
#endif /* !defined(CONFIG_USER_ONLY) */
|
|
|
|
|
|
|
|
/* 601 unified BATs store.
|
|
|
|
* To avoid using specific MMU code for 601, we store BATs in
|
|
|
|
* IBAT and DBAT simultaneously, then emulate unified BATs.
|
|
|
|
*/
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
void OPPROTO op_store_601_batl (void)
|
|
|
|
{
|
|
|
|
int nr = PARAM1;
|
|
|
|
|
|
|
|
env->IBAT[1][nr] = T0;
|
|
|
|
env->DBAT[1][nr] = T0;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_store_601_batu (void)
|
|
|
|
{
|
|
|
|
do_store_601_batu(PARAM1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
#endif /* !defined(CONFIG_USER_ONLY) */
|
|
|
|
|
|
|
|
/* PowerPC 601 specific instructions (POWER bridge) */
|
|
|
|
/* XXX: those micro-ops need tests ! */
|
|
|
|
void OPPROTO op_POWER_abs (void)
|
|
|
|
{
|
|
|
|
if (T0 == INT32_MIN)
|
|
|
|
T0 = INT32_MAX;
|
|
|
|
else if (T0 < 0)
|
|
|
|
T0 = -T0;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_abso (void)
|
|
|
|
{
|
|
|
|
do_POWER_abso();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_clcs (void)
|
|
|
|
{
|
|
|
|
do_POWER_clcs();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_div (void)
|
|
|
|
{
|
|
|
|
do_POWER_div();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_divo (void)
|
|
|
|
{
|
|
|
|
do_POWER_divo();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_divs (void)
|
|
|
|
{
|
|
|
|
do_POWER_divs();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_divso (void)
|
|
|
|
{
|
|
|
|
do_POWER_divso();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_doz (void)
|
|
|
|
{
|
|
|
|
if (Ts1 > Ts0)
|
|
|
|
T0 = T1 - T0;
|
|
|
|
else
|
|
|
|
T0 = 0;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_dozo (void)
|
|
|
|
{
|
|
|
|
do_POWER_dozo();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_load_xer_cmp (void)
|
|
|
|
{
|
|
|
|
T2 = xer_cmp;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_maskg (void)
|
|
|
|
{
|
|
|
|
do_POWER_maskg();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_maskir (void)
|
|
|
|
{
|
|
|
|
T0 = (T0 & ~T2) | (T1 & T2);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_mul (void)
|
|
|
|
{
|
|
|
|
uint64_t tmp;
|
|
|
|
|
|
|
|
tmp = (uint64_t)T0 * (uint64_t)T1;
|
|
|
|
env->spr[SPR_MQ] = tmp >> 32;
|
|
|
|
T0 = tmp;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_mulo (void)
|
|
|
|
{
|
|
|
|
do_POWER_mulo();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_nabs (void)
|
|
|
|
{
|
|
|
|
if (T0 > 0)
|
|
|
|
T0 = -T0;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_nabso (void)
|
|
|
|
{
|
|
|
|
/* nabs never overflows */
|
|
|
|
if (T0 > 0)
|
|
|
|
T0 = -T0;
|
|
|
|
xer_ov = 0;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: factorise POWER rotates... */
|
|
|
|
void OPPROTO op_POWER_rlmi (void)
|
|
|
|
{
|
|
|
|
T0 = rotl32(T0, T2) & PARAM1;
|
|
|
|
T0 |= T1 & PARAM2;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_rrib (void)
|
|
|
|
{
|
|
|
|
T2 &= 0x1FUL;
|
|
|
|
T0 = rotl32(T0 & INT32_MIN, T2);
|
|
|
|
T0 |= T1 & ~rotl32(INT32_MIN, T2);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_sle (void)
|
|
|
|
{
|
|
|
|
T1 &= 0x1FUL;
|
|
|
|
env->spr[SPR_MQ] = rotl32(T0, T1);
|
|
|
|
T0 = T0 << T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_sleq (void)
|
|
|
|
{
|
|
|
|
uint32_t tmp = env->spr[SPR_MQ];
|
|
|
|
|
|
|
|
T1 &= 0x1FUL;
|
|
|
|
env->spr[SPR_MQ] = rotl32(T0, T1);
|
|
|
|
T0 = T0 << T1;
|
|
|
|
T0 |= tmp >> (32 - T1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_sllq (void)
|
|
|
|
{
|
|
|
|
uint32_t msk = -1;
|
|
|
|
|
|
|
|
msk = msk << (T1 & 0x1FUL);
|
|
|
|
if (T1 & 0x20UL)
|
|
|
|
msk = ~msk;
|
|
|
|
T1 &= 0x1FUL;
|
|
|
|
T0 = (T0 << T1) & msk;
|
|
|
|
T0 |= env->spr[SPR_MQ] & ~msk;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_slq (void)
|
|
|
|
{
|
|
|
|
uint32_t msk = -1, tmp;
|
|
|
|
|
|
|
|
msk = msk << (T1 & 0x1FUL);
|
|
|
|
if (T1 & 0x20UL)
|
|
|
|
msk = ~msk;
|
|
|
|
T1 &= 0x1FUL;
|
|
|
|
tmp = rotl32(T0, T1);
|
|
|
|
T0 = tmp & msk;
|
|
|
|
env->spr[SPR_MQ] = tmp;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_sraq (void)
|
|
|
|
{
|
|
|
|
env->spr[SPR_MQ] = rotl32(T0, 32 - (T1 & 0x1FUL));
|
|
|
|
if (T1 & 0x20UL)
|
|
|
|
T0 = -1L;
|
|
|
|
else
|
|
|
|
T0 = Ts0 >> T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_sre (void)
|
|
|
|
{
|
|
|
|
T1 &= 0x1FUL;
|
|
|
|
env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
|
|
|
|
T0 = Ts0 >> T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_srea (void)
|
|
|
|
{
|
|
|
|
T1 &= 0x1FUL;
|
|
|
|
env->spr[SPR_MQ] = T0 >> T1;
|
|
|
|
T0 = Ts0 >> T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_sreq (void)
|
|
|
|
{
|
|
|
|
uint32_t tmp;
|
|
|
|
int32_t msk;
|
|
|
|
|
|
|
|
T1 &= 0x1FUL;
|
|
|
|
msk = INT32_MIN >> T1;
|
|
|
|
tmp = env->spr[SPR_MQ];
|
|
|
|
env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
|
|
|
|
T0 = T0 >> T1;
|
|
|
|
T0 |= tmp & msk;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_srlq (void)
|
|
|
|
{
|
|
|
|
uint32_t tmp;
|
|
|
|
int32_t msk;
|
|
|
|
|
|
|
|
msk = INT32_MIN >> (T1 & 0x1FUL);
|
|
|
|
if (T1 & 0x20UL)
|
|
|
|
msk = ~msk;
|
|
|
|
T1 &= 0x1FUL;
|
|
|
|
tmp = env->spr[SPR_MQ];
|
|
|
|
env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
|
|
|
|
T0 = T0 >> T1;
|
|
|
|
T0 &= msk;
|
|
|
|
T0 |= tmp & ~msk;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_srq (void)
|
|
|
|
{
|
|
|
|
T1 &= 0x1FUL;
|
|
|
|
env->spr[SPR_MQ] = rotl32(T0, 32 - T1);
|
|
|
|
T0 = T0 >> T1;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* POWER instructions not implemented in PowerPC 601 */
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
void OPPROTO op_POWER_mfsri (void)
|
|
|
|
{
|
|
|
|
T1 = T0 >> 28;
|
|
|
|
T0 = env->sr[T1];
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_rac (void)
|
|
|
|
{
|
|
|
|
do_POWER_rac();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_POWER_rfsvc (void)
|
|
|
|
{
|
|
|
|
do_POWER_rfsvc();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* PowerPC 602 specific instruction */
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
void OPPROTO op_602_mfrom (void)
|
|
|
|
{
|
|
|
|
do_op_602_mfrom();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* PowerPC 4xx specific micro-ops */
|
|
|
|
void OPPROTO op_405_add_T0_T2 (void)
|
|
|
|
{
|
|
|
|
T0 = (int32_t)T0 + (int32_t)T2;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_mulchw (void)
|
|
|
|
{
|
|
|
|
T0 = ((int16_t)T0) * ((int16_t)(T1 >> 16));
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_mulchwu (void)
|
|
|
|
{
|
|
|
|
T0 = ((uint16_t)T0) * ((uint16_t)(T1 >> 16));
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_mulhhw (void)
|
|
|
|
{
|
|
|
|
T0 = ((int16_t)(T0 >> 16)) * ((int16_t)(T1 >> 16));
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_mulhhwu (void)
|
|
|
|
{
|
|
|
|
T0 = ((uint16_t)(T0 >> 16)) * ((uint16_t)(T1 >> 16));
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_mullhw (void)
|
|
|
|
{
|
|
|
|
T0 = ((int16_t)T0) * ((int16_t)T1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_mullhwu (void)
|
|
|
|
{
|
|
|
|
T0 = ((uint16_t)T0) * ((uint16_t)T1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_check_ov (void)
|
|
|
|
{
|
|
|
|
do_405_check_ov();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_check_sat (void)
|
|
|
|
{
|
|
|
|
do_405_check_sat();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_check_ovu (void)
|
|
|
|
{
|
|
|
|
if (likely(T0 >= T2)) {
|
|
|
|
xer_ov = 0;
|
|
|
|
} else {
|
|
|
|
xer_ov = 1;
|
|
|
|
xer_so = 1;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_405_check_satu (void)
|
|
|
|
{
|
|
|
|
if (unlikely(T0 < T2)) {
|
|
|
|
/* Saturate result */
|
|
|
|
T0 = -1;
|
|
|
|
}
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
void OPPROTO op_4xx_load_dcr (void)
|
|
|
|
{
|
|
|
|
do_4xx_load_dcr(PARAM1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_4xx_store_dcr (void)
|
|
|
|
{
|
|
|
|
do_4xx_store_dcr(PARAM1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Return from critical interrupt :
|
|
|
|
* same as rfi, except nip & MSR are loaded from SRR2/3 instead of SRR0/1
|
|
|
|
*/
|
|
|
|
void OPPROTO op_4xx_rfci (void)
|
|
|
|
{
|
|
|
|
do_4xx_rfci();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_4xx_wrte (void)
|
|
|
|
{
|
|
|
|
msr_ee = T0 >> 16;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_4xx_tlbre_lo (void)
|
|
|
|
{
|
|
|
|
do_4xx_tlbre_lo();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_4xx_tlbre_hi (void)
|
|
|
|
{
|
|
|
|
do_4xx_tlbre_hi();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_4xx_tlbsx (void)
|
|
|
|
{
|
|
|
|
do_4xx_tlbsx();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_4xx_tlbsx_ (void)
|
|
|
|
{
|
|
|
|
do_4xx_tlbsx_();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_4xx_tlbwe_lo (void)
|
|
|
|
{
|
|
|
|
do_4xx_tlbwe_lo();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_4xx_tlbwe_hi (void)
|
|
|
|
{
|
|
|
|
do_4xx_tlbwe_hi();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/* SPR micro-ops */
|
|
|
|
/* 440 specific */
|
|
|
|
void OPPROTO op_440_dlmzb (void)
|
|
|
|
{
|
|
|
|
do_440_dlmzb();
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_440_dlmzb_update_Rc (void)
|
|
|
|
{
|
|
|
|
if (T0 == 8)
|
|
|
|
T0 = 0x2;
|
|
|
|
else if (T0 < 4)
|
|
|
|
T0 = 0x4;
|
|
|
|
else
|
|
|
|
T0 = 0x8;
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
|
|
void OPPROTO op_store_pir (void)
|
2005-07-02 22:59:34 +02:00
|
|
|
{
|
|
|
|
env->spr[SPR_PIR] = T0 & 0x0000000FUL;
|
|
|
|
RETURN();
|
|
|
|
}
|
2007-03-07 09:32:30 +01:00
|
|
|
|
|
|
|
void OPPROTO op_load_403_pb (void)
|
|
|
|
{
|
|
|
|
do_load_403_pb(PARAM1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
void OPPROTO op_store_403_pb (void)
|
|
|
|
{
|
|
|
|
do_store_403_pb(PARAM1);
|
|
|
|
RETURN();
|
|
|
|
}
|
|
|
|
|
|
|
|
target_ulong load_40x_pit (CPUState *env);
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void OPPROTO op_load_40x_pit (void)
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{
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T0 = load_40x_pit(env);
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RETURN();
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}
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void store_40x_pit (CPUState *env, target_ulong val);
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void OPPROTO op_store_40x_pit (void)
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{
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store_40x_pit(env, T0);
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|
RETURN();
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}
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void store_booke_tcr (CPUState *env, target_ulong val);
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void OPPROTO op_store_booke_tcr (void)
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|
{
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|
store_booke_tcr(env, T0);
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|
RETURN();
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}
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void store_booke_tsr (CPUState *env, target_ulong val);
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void OPPROTO op_store_booke_tsr (void)
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|
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|
{
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|
store_booke_tsr(env, T0);
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RETURN();
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}
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#endif /* !defined(CONFIG_USER_ONLY) */
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