2018-04-13 18:08:26 +02:00
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# -*- Mode: makefile -*-
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#
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# AArch64 specific tweaks
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2019-08-07 16:35:22 +02:00
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ARM_SRC=$(SRC_PATH)/tests/tcg/arm
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VPATH += $(ARM_SRC)
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2018-04-13 18:08:26 +02:00
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AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64
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VPATH += $(AARCH64_SRC)
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2021-11-03 05:03:52 +01:00
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# Base architecture tests
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AARCH64_TESTS=fcvt pcalign-a64
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2018-04-13 18:08:26 +02:00
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fcvt: LDFLAGS+=-lm
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run-fcvt: fcvt
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2018-05-21 11:38:37 +02:00
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$(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)")
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$(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref)
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2019-02-05 17:52:39 +01:00
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2022-09-29 13:42:04 +02:00
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config-cc.mak: Makefile
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$(quiet-@)( \
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$(call cc-option,-march=armv8.1-a+sve, CROSS_CC_HAS_SVE); \
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$(call cc-option,-march=armv8.1-a+sve2, CROSS_CC_HAS_SVE2); \
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2023-06-06 11:19:40 +02:00
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$(call cc-option,-march=armv8.2-a, CROSS_CC_HAS_ARMV8_2); \
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2022-09-29 13:42:04 +02:00
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$(call cc-option,-march=armv8.3-a, CROSS_CC_HAS_ARMV8_3); \
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2023-06-06 11:19:40 +02:00
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$(call cc-option,-march=armv8.5-a, CROSS_CC_HAS_ARMV8_5); \
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2022-09-29 13:42:04 +02:00
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$(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \
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2022-12-17 02:01:26 +01:00
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$(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \
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$(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak
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2022-09-29 13:42:04 +02:00
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-include config-cc.mak
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2023-06-06 11:19:40 +02:00
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ifneq ($(CROSS_CC_HAS_ARMV8_2),)
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AARCH64_TESTS += dcpop
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dcpop: CFLAGS += -march=armv8.2-a
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endif
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ifneq ($(CROSS_CC_HAS_ARMV8_5),)
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AARCH64_TESTS += dcpodp
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dcpodp: CFLAGS += -march=armv8.5-a
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endif
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2019-09-19 15:18:40 +02:00
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# Pauth Tests
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2022-04-19 11:10:07 +02:00
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ifneq ($(CROSS_CC_HAS_ARMV8_3),)
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2020-08-03 18:55:03 +02:00
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AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5
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2020-01-23 16:22:38 +01:00
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pauth-%: CFLAGS += -march=armv8.3-a
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2020-06-15 16:19:22 +02:00
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run-pauth-%: QEMU_OPTS += -cpu max
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2020-02-03 10:09:28 +01:00
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endif
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2019-02-05 17:52:39 +01:00
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2020-10-21 19:37:49 +02:00
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# BTI Tests
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# bti-1 tests the elf notes, so we require special compiler support.
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2022-04-19 11:10:07 +02:00
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ifneq ($(CROSS_CC_HAS_ARMV8_BTI),)
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2022-04-27 06:23:12 +02:00
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AARCH64_TESTS += bti-1 bti-3
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bti-1 bti-3: CFLAGS += -mbranch-protection=standard
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bti-1 bti-3: LDFLAGS += -nostdlib
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2020-10-21 19:37:49 +02:00
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endif
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# bti-2 tests PROT_BTI, so no special compiler support required.
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AARCH64_TESTS += bti-2
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2021-02-12 19:49:02 +01:00
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# MTE Tests
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2022-04-19 11:10:07 +02:00
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ifneq ($(CROSS_CC_HAS_ARMV8_MTE),)
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2021-06-12 21:57:07 +02:00
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AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7
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2021-02-12 19:49:02 +01:00
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mte-%: CFLAGS += -march=armv8.5-a+memtag
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endif
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2022-04-19 11:10:07 +02:00
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ifneq ($(CROSS_CC_HAS_SVE),)
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2020-03-16 18:21:47 +01:00
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# System Registers Tests
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AARCH64_TESTS += sysregs
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2022-12-17 02:01:26 +01:00
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ifneq ($(CROSS_CC_HAS_ARMV9_SME),)
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sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME
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else
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2020-03-16 18:21:47 +01:00
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sysregs: CFLAGS+=-march=armv8.1-a+sve
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2022-12-17 02:01:26 +01:00
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endif
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2020-03-16 18:21:50 +01:00
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2020-03-16 18:21:51 +01:00
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# SVE ioctl test
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AARCH64_TESTS += sve-ioctls
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sve-ioctls: CFLAGS+=-march=armv8.1-a+sve
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2022-02-25 18:20:14 +01:00
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# Vector SHA1
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sha1-vector: CFLAGS=-O3
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sha1-vector: sha1.c
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$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
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run-sha1-vector: sha1-vector run-sha1
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2022-09-29 13:42:03 +02:00
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$(call run-test, $<, $(QEMU) $(QEMU_OPTS) $<)
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2022-02-25 18:20:14 +01:00
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$(call diff-out, sha1-vector, sha1.out)
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TESTS += sha1-vector
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2022-02-25 18:20:16 +01:00
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# Vector versions of sha512 (-O3 triggers vectorisation)
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sha512-vector: CFLAGS=-O3
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sha512-vector: sha512.c
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$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
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TESTS += sha512-vector
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plugins: force slow path when plugins instrument memory ops
The lack of SVE memory instrumentation has been an omission in plugin
handling since it was introduced. Fortunately we can utilise the
probe_* functions to force all all memory access to follow the slow
path. We do this by checking the access type and presence of plugin
memory callbacks and if set return the TLB_MMIO flag.
We have to jump through a few hoops in user mode to re-use the flag
but it was the desired effect:
./qemu-system-aarch64 -display none -serial mon:stdio \
-M virt -cpu max -semihosting-config enable=on \
-kernel ./tests/tcg/aarch64-softmmu/memory-sve \
-plugin ./contrib/plugins/libexeclog.so,ifilter=st1w,afilter=0x40001808 -d plugin
gives (disas doesn't currently understand st1w):
0, 0x40001808, 0xe54342a0, ".byte 0xa0, 0x42, 0x43, 0xe5", store, 0x40213010, RAM, store, 0x40213014, RAM, store, 0x40213018, RAM
And for user-mode:
./qemu-aarch64 \
-plugin contrib/plugins/libexeclog.so,afilter=0x4007c0 \
-d plugin \
./tests/tcg/aarch64-linux-user/sha512-sve
gives:
1..10
ok 1 - do_test(&tests[i])
0, 0x4007c0, 0xa4004b80, ".byte 0x80, 0x4b, 0x00, 0xa4", load, 0x5500800370, load, 0x5500800371, load, 0x5500800372, load, 0x5500800373, load, 0x5500800374, load, 0x5500800375, load, 0x5500800376, load, 0x5500800377, load, 0x5500800378, load, 0x5500800379, load, 0x550080037a, load, 0x550080037b, load, 0x550080037c, load, 0x550080037d, load, 0x550080037e, load, 0x550080037f, load, 0x5500800380, load, 0x5500800381, load, 0x5500800382, load, 0x5500800383, load, 0x5500800384, load, 0x5500800385, load, 0x5500800386, lo
ad, 0x5500800387, load, 0x5500800388, load, 0x5500800389, load, 0x550080038a, load, 0x550080038b, load, 0x550080038c, load, 0x550080038d, load, 0x550080038e, load, 0x550080038f, load, 0x5500800390, load, 0x5500800391, load, 0x5500800392, load, 0x5500800393, load, 0x5500800394, load, 0x5500800395, load, 0x5500800396, load, 0x5500800397, load, 0x5500800398, load, 0x5500800399, load, 0x550080039a, load, 0x550080039b, load, 0x550080039c, load, 0x550080039d, load, 0x550080039e, load, 0x550080039f, load, 0x55008003a0, load, 0x55008003a1, load, 0x55008003a2, load, 0x55008003a3, load, 0x55008003a4, load, 0x55008003a5, load, 0x55008003a6, load, 0x55008003a7, load, 0x55008003a8, load, 0x55008003a9, load, 0x55008003aa, load, 0x55008003ab, load, 0x55008003ac, load, 0x55008003ad, load, 0x55008003ae, load, 0x55008003af
(4007c0 is the ld1b in the sha512-sve)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: Robert Henry <robhenry@microsoft.com>
Cc: Aaron Lindsay <aaron@os.amperecomputing.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20230630180423.558337-20-alex.bennee@linaro.org>
2023-06-30 20:04:04 +02:00
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ifneq ($(CROSS_CC_HAS_SVE),)
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sha512-sve: CFLAGS=-O3 -march=armv8.1-a+sve
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sha512-sve: sha512.c
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$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
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TESTS += sha512-sve
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endif
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2023-03-03 03:57:59 +01:00
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ifeq ($(HOST_GDB_SUPPORTS_ARCH),y)
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2020-03-16 18:21:50 +01:00
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GDB_SCRIPT=$(SRC_PATH)/tests/guest-debug/run-test.py
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run-gdbstub-sysregs: sysregs
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$(call run-test, $@, $(GDB_SCRIPT) \
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--gdb $(HAVE_GDB_BIN) \
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--qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
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--bin $< --test $(AARCH64_SRC)/gdbstub/test-sve.py, \
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2022-09-29 13:42:03 +02:00
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basic gdbstub SVE support)
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2020-03-16 18:21:52 +01:00
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run-gdbstub-sve-ioctls: sve-ioctls
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$(call run-test, $@, $(GDB_SCRIPT) \
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--gdb $(HAVE_GDB_BIN) \
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--qemu $(QEMU) --qargs "$(QEMU_OPTS)" \
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--bin $< --test $(AARCH64_SRC)/gdbstub/test-sve-ioctl.py, \
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2022-09-29 13:42:03 +02:00
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basic gdbstub SVE ZLEN support)
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2020-04-30 21:01:21 +02:00
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EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls
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2020-03-16 18:21:50 +01:00
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endif
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2022-03-08 04:16:55 +01:00
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endif
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2020-03-16 18:21:50 +01:00
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2022-04-19 11:10:07 +02:00
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ifneq ($(CROSS_CC_HAS_SVE2),)
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2022-03-08 04:16:55 +01:00
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AARCH64_TESTS += test-826
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test-826: CFLAGS+=-march=armv8.1-a+sve2
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2020-03-16 18:21:47 +01:00
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endif
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2019-08-07 16:35:22 +02:00
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TESTS += $(AARCH64_TESTS)
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