541 lines
17 KiB
C
541 lines
17 KiB
C
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/*
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* Nuvoton NPCM7xx MFT Module
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*
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* Copyright 2021 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "hw/misc/npcm7xx_mft.h"
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#include "hw/misc/npcm7xx_pwm.h"
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#include "hw/registerfields.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "qemu/bitops.h"
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#include "qemu/error-report.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/timer.h"
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#include "qemu/units.h"
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#include "trace.h"
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/*
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* Some of the registers can only accessed via 16-bit ops and some can only
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* be accessed via 8-bit ops. However we mark all of them using REG16 to
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* simplify implementation. npcm7xx_mft_check_mem_op checks the access length
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* of memory operations.
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*/
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REG16(NPCM7XX_MFT_CNT1, 0x00);
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REG16(NPCM7XX_MFT_CRA, 0x02);
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REG16(NPCM7XX_MFT_CRB, 0x04);
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REG16(NPCM7XX_MFT_CNT2, 0x06);
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REG16(NPCM7XX_MFT_PRSC, 0x08);
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REG16(NPCM7XX_MFT_CKC, 0x0a);
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REG16(NPCM7XX_MFT_MCTRL, 0x0c);
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REG16(NPCM7XX_MFT_ICTRL, 0x0e);
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REG16(NPCM7XX_MFT_ICLR, 0x10);
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REG16(NPCM7XX_MFT_IEN, 0x12);
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REG16(NPCM7XX_MFT_CPA, 0x14);
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REG16(NPCM7XX_MFT_CPB, 0x16);
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REG16(NPCM7XX_MFT_CPCFG, 0x18);
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REG16(NPCM7XX_MFT_INASEL, 0x1a);
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REG16(NPCM7XX_MFT_INBSEL, 0x1c);
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/* Register Fields */
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#define NPCM7XX_MFT_CKC_C2CSEL BIT(3)
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#define NPCM7XX_MFT_CKC_C1CSEL BIT(0)
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#define NPCM7XX_MFT_MCTRL_TBEN BIT(6)
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#define NPCM7XX_MFT_MCTRL_TAEN BIT(5)
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#define NPCM7XX_MFT_MCTRL_TBEDG BIT(4)
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#define NPCM7XX_MFT_MCTRL_TAEDG BIT(3)
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#define NPCM7XX_MFT_MCTRL_MODE5 BIT(2)
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#define NPCM7XX_MFT_ICTRL_TFPND BIT(5)
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#define NPCM7XX_MFT_ICTRL_TEPND BIT(4)
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#define NPCM7XX_MFT_ICTRL_TDPND BIT(3)
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#define NPCM7XX_MFT_ICTRL_TCPND BIT(2)
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#define NPCM7XX_MFT_ICTRL_TBPND BIT(1)
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#define NPCM7XX_MFT_ICTRL_TAPND BIT(0)
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#define NPCM7XX_MFT_ICLR_TFCLR BIT(5)
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#define NPCM7XX_MFT_ICLR_TECLR BIT(4)
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#define NPCM7XX_MFT_ICLR_TDCLR BIT(3)
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#define NPCM7XX_MFT_ICLR_TCCLR BIT(2)
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#define NPCM7XX_MFT_ICLR_TBCLR BIT(1)
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#define NPCM7XX_MFT_ICLR_TACLR BIT(0)
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#define NPCM7XX_MFT_IEN_TFIEN BIT(5)
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#define NPCM7XX_MFT_IEN_TEIEN BIT(4)
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#define NPCM7XX_MFT_IEN_TDIEN BIT(3)
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#define NPCM7XX_MFT_IEN_TCIEN BIT(2)
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#define NPCM7XX_MFT_IEN_TBIEN BIT(1)
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#define NPCM7XX_MFT_IEN_TAIEN BIT(0)
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#define NPCM7XX_MFT_CPCFG_GET_B(rv) extract8((rv), 4, 4)
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#define NPCM7XX_MFT_CPCFG_GET_A(rv) extract8((rv), 0, 4)
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#define NPCM7XX_MFT_CPCFG_HIEN BIT(3)
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#define NPCM7XX_MFT_CPCFG_EQEN BIT(2)
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#define NPCM7XX_MFT_CPCFG_LOEN BIT(1)
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#define NPCM7XX_MFT_CPCFG_CPSEL BIT(0)
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#define NPCM7XX_MFT_INASEL_SELA BIT(0)
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#define NPCM7XX_MFT_INBSEL_SELB BIT(0)
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/* Max CNT values of the module. The CNT value is a countdown from it. */
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#define NPCM7XX_MFT_MAX_CNT 0xFFFF
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/* Each fan revolution should generated 2 pulses */
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#define NPCM7XX_MFT_PULSE_PER_REVOLUTION 2
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typedef enum NPCM7xxMFTCaptureState {
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/* capture succeeded with a valid CNT value. */
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NPCM7XX_CAPTURE_SUCCEED,
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/* capture stopped prematurely due to reaching CPCFG condition. */
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NPCM7XX_CAPTURE_COMPARE_HIT,
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/* capture fails since it reaches underflow condition for CNT. */
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NPCM7XX_CAPTURE_UNDERFLOW,
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} NPCM7xxMFTCaptureState;
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static void npcm7xx_mft_reset(NPCM7xxMFTState *s)
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{
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int i;
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/* Only registers PRSC ~ INBSEL need to be reset. */
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for (i = R_NPCM7XX_MFT_PRSC; i <= R_NPCM7XX_MFT_INBSEL; ++i) {
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s->regs[i] = 0;
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}
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}
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static void npcm7xx_mft_clear_interrupt(NPCM7xxMFTState *s, uint8_t iclr)
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{
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/*
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* Clear bits in ICTRL where corresponding bits in iclr is 1.
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* Both iclr and ictrl are 8-bit regs. (See npcm7xx_mft_check_mem_op)
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*/
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s->regs[R_NPCM7XX_MFT_ICTRL] &= ~iclr;
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}
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/*
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* If the CPCFG's condition should be triggered during count down from
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* NPCM7XX_MFT_MAX_CNT to src if compared to tgt, return the count when
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* the condition is triggered.
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* Otherwise return -1.
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* Since tgt is uint16_t it must always <= NPCM7XX_MFT_MAX_CNT.
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*/
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static int npcm7xx_mft_compare(int32_t src, uint16_t tgt, uint8_t cpcfg)
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{
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if (cpcfg & NPCM7XX_MFT_CPCFG_HIEN) {
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return NPCM7XX_MFT_MAX_CNT;
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}
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if ((cpcfg & NPCM7XX_MFT_CPCFG_EQEN) && (src <= tgt)) {
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return tgt;
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}
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if ((cpcfg & NPCM7XX_MFT_CPCFG_LOEN) && (tgt > 0) && (src < tgt)) {
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return tgt - 1;
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}
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return -1;
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}
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/* Compute CNT according to corresponding fan's RPM. */
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static NPCM7xxMFTCaptureState npcm7xx_mft_compute_cnt(
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Clock *clock, uint32_t max_rpm, uint32_t duty, uint16_t tgt,
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uint8_t cpcfg, uint16_t *cnt)
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{
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uint32_t rpm = (uint64_t)max_rpm * (uint64_t)duty / NPCM7XX_PWM_MAX_DUTY;
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int32_t count;
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int stopped;
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NPCM7xxMFTCaptureState state;
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if (rpm == 0) {
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/*
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* If RPM = 0, capture won't happen. CNT will continue count down.
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* So it's effective equivalent to have a cnt > NPCM7XX_MFT_MAX_CNT
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*/
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count = NPCM7XX_MFT_MAX_CNT + 1;
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} else {
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/*
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* RPM = revolution/min. The time for one revlution (in ns) is
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* MINUTE_TO_NANOSECOND / RPM.
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*/
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count = clock_ns_to_ticks(clock, (60 * NANOSECONDS_PER_SECOND) /
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(rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION));
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}
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if (count > NPCM7XX_MFT_MAX_CNT) {
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count = -1;
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} else {
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/* The CNT is a countdown value from NPCM7XX_MFT_MAX_CNT. */
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count = NPCM7XX_MFT_MAX_CNT - count;
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}
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stopped = npcm7xx_mft_compare(count, tgt, cpcfg);
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if (stopped == -1) {
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if (count == -1) {
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/* Underflow */
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state = NPCM7XX_CAPTURE_UNDERFLOW;
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} else {
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state = NPCM7XX_CAPTURE_SUCCEED;
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}
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} else {
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count = stopped;
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state = NPCM7XX_CAPTURE_COMPARE_HIT;
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}
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if (count != -1) {
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*cnt = count;
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}
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trace_npcm7xx_mft_rpm(clock->canonical_path, clock_get_hz(clock),
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state, count, rpm, duty);
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return state;
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}
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/*
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* Capture Fan RPM and update CNT and CR registers accordingly.
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* Raise IRQ if certain contidions are met in IEN.
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*/
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static void npcm7xx_mft_capture(NPCM7xxMFTState *s)
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{
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int irq_level = 0;
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NPCM7xxMFTCaptureState state;
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int sel;
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uint8_t cpcfg;
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/*
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* If not mode 5, the behavior is undefined. We just do nothing in this
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* case.
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*/
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if (!(s->regs[R_NPCM7XX_MFT_MCTRL] & NPCM7XX_MFT_MCTRL_MODE5)) {
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return;
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}
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/* Capture input A. */
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if (s->regs[R_NPCM7XX_MFT_MCTRL] & NPCM7XX_MFT_MCTRL_TAEN &&
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s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C1CSEL) {
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sel = s->regs[R_NPCM7XX_MFT_INASEL] & NPCM7XX_MFT_INASEL_SELA;
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cpcfg = NPCM7XX_MFT_CPCFG_GET_A(s->regs[R_NPCM7XX_MFT_CPCFG]);
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state = npcm7xx_mft_compute_cnt(s->clock_1,
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sel ? s->max_rpm[2] : s->max_rpm[0],
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sel ? s->duty[2] : s->duty[0],
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s->regs[R_NPCM7XX_MFT_CPA],
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cpcfg,
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&s->regs[R_NPCM7XX_MFT_CNT1]);
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switch (state) {
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case NPCM7XX_CAPTURE_SUCCEED:
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/* Interrupt on input capture on TAn transition - TAPND */
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s->regs[R_NPCM7XX_MFT_CRA] = s->regs[R_NPCM7XX_MFT_CNT1];
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s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TAPND;
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if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TAIEN) {
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irq_level = 1;
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}
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break;
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case NPCM7XX_CAPTURE_COMPARE_HIT:
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/* Compare Hit - TEPND */
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s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TEPND;
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if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TEIEN) {
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irq_level = 1;
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}
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break;
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case NPCM7XX_CAPTURE_UNDERFLOW:
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/* Underflow - TCPND */
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s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TCPND;
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if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TCIEN) {
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irq_level = 1;
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}
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break;
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default:
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g_assert_not_reached();
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}
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}
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/* Capture input B. */
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if (s->regs[R_NPCM7XX_MFT_MCTRL] & NPCM7XX_MFT_MCTRL_TBEN &&
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s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C2CSEL) {
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sel = s->regs[R_NPCM7XX_MFT_INBSEL] & NPCM7XX_MFT_INBSEL_SELB;
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cpcfg = NPCM7XX_MFT_CPCFG_GET_B(s->regs[R_NPCM7XX_MFT_CPCFG]);
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state = npcm7xx_mft_compute_cnt(s->clock_2,
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sel ? s->max_rpm[3] : s->max_rpm[1],
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sel ? s->duty[3] : s->duty[1],
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s->regs[R_NPCM7XX_MFT_CPB],
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cpcfg,
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&s->regs[R_NPCM7XX_MFT_CNT2]);
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switch (state) {
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case NPCM7XX_CAPTURE_SUCCEED:
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/* Interrupt on input capture on TBn transition - TBPND */
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s->regs[R_NPCM7XX_MFT_CRB] = s->regs[R_NPCM7XX_MFT_CNT2];
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s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TBPND;
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if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TBIEN) {
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irq_level = 1;
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}
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break;
|
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case NPCM7XX_CAPTURE_COMPARE_HIT:
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/* Compare Hit - TFPND */
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s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TFPND;
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if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TFIEN) {
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irq_level = 1;
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}
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break;
|
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case NPCM7XX_CAPTURE_UNDERFLOW:
|
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/* Underflow - TDPND */
|
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s->regs[R_NPCM7XX_MFT_ICTRL] |= NPCM7XX_MFT_ICTRL_TDPND;
|
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|
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if (s->regs[R_NPCM7XX_MFT_IEN] & NPCM7XX_MFT_IEN_TDIEN) {
|
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irq_level = 1;
|
||
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}
|
||
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break;
|
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|
||
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default:
|
||
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g_assert_not_reached();
|
||
|
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}
|
||
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}
|
||
|
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|
||
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trace_npcm7xx_mft_capture(DEVICE(s)->canonical_path, irq_level);
|
||
|
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qemu_set_irq(s->irq, irq_level);
|
||
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}
|
||
|
|
|
||
|
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/* Update clock for counters. */
|
||
|
|
static void npcm7xx_mft_update_clock(void *opaque, ClockEvent event)
|
||
|
|
{
|
||
|
|
NPCM7xxMFTState *s = NPCM7XX_MFT(opaque);
|
||
|
|
uint64_t prescaled_clock_period;
|
||
|
|
|
||
|
|
prescaled_clock_period = clock_get(s->clock_in) *
|
||
|
|
(s->regs[R_NPCM7XX_MFT_PRSC] + 1ULL);
|
||
|
|
trace_npcm7xx_mft_update_clock(s->clock_in->canonical_path,
|
||
|
|
s->regs[R_NPCM7XX_MFT_CKC],
|
||
|
|
clock_get(s->clock_in),
|
||
|
|
prescaled_clock_period);
|
||
|
|
/* Update clock 1 */
|
||
|
|
if (s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C1CSEL) {
|
||
|
|
/* Clock is prescaled. */
|
||
|
|
clock_update(s->clock_1, prescaled_clock_period);
|
||
|
|
} else {
|
||
|
|
/* Clock stopped. */
|
||
|
|
clock_update(s->clock_1, 0);
|
||
|
|
}
|
||
|
|
/* Update clock 2 */
|
||
|
|
if (s->regs[R_NPCM7XX_MFT_CKC] & NPCM7XX_MFT_CKC_C2CSEL) {
|
||
|
|
/* Clock is prescaled. */
|
||
|
|
clock_update(s->clock_2, prescaled_clock_period);
|
||
|
|
} else {
|
||
|
|
/* Clock stopped. */
|
||
|
|
clock_update(s->clock_2, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
npcm7xx_mft_capture(s);
|
||
|
|
}
|
||
|
|
|
||
|
|
static uint64_t npcm7xx_mft_read(void *opaque, hwaddr offset, unsigned size)
|
||
|
|
{
|
||
|
|
NPCM7xxMFTState *s = NPCM7XX_MFT(opaque);
|
||
|
|
uint16_t value = 0;
|
||
|
|
|
||
|
|
switch (offset) {
|
||
|
|
case A_NPCM7XX_MFT_ICLR:
|
||
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
||
|
|
"%s: register @ 0x%04" HWADDR_PRIx " is write-only\n",
|
||
|
|
__func__, offset);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
value = s->regs[offset / 2];
|
||
|
|
}
|
||
|
|
|
||
|
|
trace_npcm7xx_mft_read(DEVICE(s)->canonical_path, offset, value);
|
||
|
|
return value;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void npcm7xx_mft_write(void *opaque, hwaddr offset,
|
||
|
|
uint64_t v, unsigned size)
|
||
|
|
{
|
||
|
|
NPCM7xxMFTState *s = NPCM7XX_MFT(opaque);
|
||
|
|
|
||
|
|
trace_npcm7xx_mft_write(DEVICE(s)->canonical_path, offset, v);
|
||
|
|
switch (offset) {
|
||
|
|
case A_NPCM7XX_MFT_ICLR:
|
||
|
|
npcm7xx_mft_clear_interrupt(s, v);
|
||
|
|
break;
|
||
|
|
|
||
|
|
case A_NPCM7XX_MFT_CKC:
|
||
|
|
case A_NPCM7XX_MFT_PRSC:
|
||
|
|
s->regs[offset / 2] = v;
|
||
|
|
npcm7xx_mft_update_clock(s, ClockUpdate);
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
s->regs[offset / 2] = v;
|
||
|
|
npcm7xx_mft_capture(s);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool npcm7xx_mft_check_mem_op(void *opaque, hwaddr offset,
|
||
|
|
unsigned size, bool is_write,
|
||
|
|
MemTxAttrs attrs)
|
||
|
|
{
|
||
|
|
switch (offset) {
|
||
|
|
/* 16-bit registers. Must be accessed with 16-bit read/write.*/
|
||
|
|
case A_NPCM7XX_MFT_CNT1:
|
||
|
|
case A_NPCM7XX_MFT_CRA:
|
||
|
|
case A_NPCM7XX_MFT_CRB:
|
||
|
|
case A_NPCM7XX_MFT_CNT2:
|
||
|
|
case A_NPCM7XX_MFT_CPA:
|
||
|
|
case A_NPCM7XX_MFT_CPB:
|
||
|
|
return size == 2;
|
||
|
|
|
||
|
|
/* 8-bit registers. Must be accessed with 8-bit read/write.*/
|
||
|
|
case A_NPCM7XX_MFT_PRSC:
|
||
|
|
case A_NPCM7XX_MFT_CKC:
|
||
|
|
case A_NPCM7XX_MFT_MCTRL:
|
||
|
|
case A_NPCM7XX_MFT_ICTRL:
|
||
|
|
case A_NPCM7XX_MFT_ICLR:
|
||
|
|
case A_NPCM7XX_MFT_IEN:
|
||
|
|
case A_NPCM7XX_MFT_CPCFG:
|
||
|
|
case A_NPCM7XX_MFT_INASEL:
|
||
|
|
case A_NPCM7XX_MFT_INBSEL:
|
||
|
|
return size == 1;
|
||
|
|
|
||
|
|
default:
|
||
|
|
/* Invalid registers. */
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
static void npcm7xx_mft_get_max_rpm(Object *obj, Visitor *v, const char *name,
|
||
|
|
void *opaque, Error **errp)
|
||
|
|
{
|
||
|
|
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void npcm7xx_mft_set_max_rpm(Object *obj, Visitor *v, const char *name,
|
||
|
|
void *opaque, Error **errp)
|
||
|
|
{
|
||
|
|
NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
|
||
|
|
uint32_t *max_rpm = opaque;
|
||
|
|
uint32_t value;
|
||
|
|
|
||
|
|
if (!visit_type_uint32(v, name, &value, errp)) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
*max_rpm = value;
|
||
|
|
npcm7xx_mft_capture(s);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void npcm7xx_mft_duty_handler(void *opaque, int n, int value)
|
||
|
|
{
|
||
|
|
NPCM7xxMFTState *s = NPCM7XX_MFT(opaque);
|
||
|
|
|
||
|
|
trace_npcm7xx_mft_set_duty(DEVICE(s)->canonical_path, n, value);
|
||
|
|
s->duty[n] = value;
|
||
|
|
npcm7xx_mft_capture(s);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct MemoryRegionOps npcm7xx_mft_ops = {
|
||
|
|
.read = npcm7xx_mft_read,
|
||
|
|
.write = npcm7xx_mft_write,
|
||
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||
|
|
.valid = {
|
||
|
|
.min_access_size = 1,
|
||
|
|
.max_access_size = 2,
|
||
|
|
.unaligned = false,
|
||
|
|
.accepts = npcm7xx_mft_check_mem_op,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static void npcm7xx_mft_enter_reset(Object *obj, ResetType type)
|
||
|
|
{
|
||
|
|
NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
|
||
|
|
|
||
|
|
npcm7xx_mft_reset(s);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void npcm7xx_mft_hold_reset(Object *obj)
|
||
|
|
{
|
||
|
|
NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
|
||
|
|
|
||
|
|
qemu_irq_lower(s->irq);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void npcm7xx_mft_init(Object *obj)
|
||
|
|
{
|
||
|
|
NPCM7xxMFTState *s = NPCM7XX_MFT(obj);
|
||
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
||
|
|
DeviceState *dev = DEVICE(obj);
|
||
|
|
|
||
|
|
memory_region_init_io(&s->iomem, obj, &npcm7xx_mft_ops, s,
|
||
|
|
TYPE_NPCM7XX_MFT, 4 * KiB);
|
||
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
||
|
|
sysbus_init_irq(sbd, &s->irq);
|
||
|
|
s->clock_in = qdev_init_clock_in(dev, "clock-in", npcm7xx_mft_update_clock,
|
||
|
|
s, ClockUpdate);
|
||
|
|
s->clock_1 = qdev_init_clock_out(dev, "clock1");
|
||
|
|
s->clock_2 = qdev_init_clock_out(dev, "clock2");
|
||
|
|
|
||
|
|
for (int i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
|
||
|
|
object_property_add(obj, "max_rpm[*]", "uint32",
|
||
|
|
npcm7xx_mft_get_max_rpm,
|
||
|
|
npcm7xx_mft_set_max_rpm,
|
||
|
|
NULL, &s->max_rpm[i]);
|
||
|
|
}
|
||
|
|
qdev_init_gpio_in_named(dev, npcm7xx_mft_duty_handler, "duty",
|
||
|
|
NPCM7XX_MFT_FANIN_COUNT);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const VMStateDescription vmstate_npcm7xx_mft = {
|
||
|
|
.name = "npcm7xx-mft-module",
|
||
|
|
.version_id = 0,
|
||
|
|
.minimum_version_id = 0,
|
||
|
|
.fields = (VMStateField[]) {
|
||
|
|
VMSTATE_CLOCK(clock_in, NPCM7xxMFTState),
|
||
|
|
VMSTATE_CLOCK(clock_1, NPCM7xxMFTState),
|
||
|
|
VMSTATE_CLOCK(clock_2, NPCM7xxMFTState),
|
||
|
|
VMSTATE_UINT16_ARRAY(regs, NPCM7xxMFTState, NPCM7XX_MFT_NR_REGS),
|
||
|
|
VMSTATE_UINT32_ARRAY(max_rpm, NPCM7xxMFTState, NPCM7XX_MFT_FANIN_COUNT),
|
||
|
|
VMSTATE_UINT32_ARRAY(duty, NPCM7xxMFTState, NPCM7XX_MFT_FANIN_COUNT),
|
||
|
|
VMSTATE_END_OF_LIST(),
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static void npcm7xx_mft_class_init(ObjectClass *klass, void *data)
|
||
|
|
{
|
||
|
|
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
||
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||
|
|
|
||
|
|
dc->desc = "NPCM7xx MFT Controller";
|
||
|
|
dc->vmsd = &vmstate_npcm7xx_mft;
|
||
|
|
rc->phases.enter = npcm7xx_mft_enter_reset;
|
||
|
|
rc->phases.hold = npcm7xx_mft_hold_reset;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const TypeInfo npcm7xx_mft_info = {
|
||
|
|
.name = TYPE_NPCM7XX_MFT,
|
||
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
||
|
|
.instance_size = sizeof(NPCM7xxMFTState),
|
||
|
|
.class_init = npcm7xx_mft_class_init,
|
||
|
|
.instance_init = npcm7xx_mft_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static void npcm7xx_mft_register_type(void)
|
||
|
|
{
|
||
|
|
type_register_static(&npcm7xx_mft_info);
|
||
|
|
}
|
||
|
|
type_init(npcm7xx_mft_register_type);
|