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qemu-e2k/target/arm/cpregs.h

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target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/*
* QEMU ARM CP Register access and descriptions
*
* Copyright (c) 2022 Linaro Ltd
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see
* <http://www.gnu.org/licenses/gpl-2.0.html>
*/
#ifndef TARGET_ARM_CPREGS_H
#define TARGET_ARM_CPREGS_H
/*
target/arm: Reorg ARMCPRegInfo type field bits Instead of defining ARM_CP_FLAG_MASK to remove flags, define ARM_CP_SPECIAL_MASK to isolate special cases. Sort the specials to the low bits. Use an enum. Split the large comment block so as to document each value separately. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:47 +02:00
* ARMCPRegInfo type field bits:
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
*/
target/arm: Reorg ARMCPRegInfo type field bits Instead of defining ARM_CP_FLAG_MASK to remove flags, define ARM_CP_SPECIAL_MASK to isolate special cases. Sort the specials to the low bits. Use an enum. Split the large comment block so as to document each value separately. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:47 +02:00
enum {
/*
* Register must be handled specially during translation.
* The method is one of the values below:
*/
ARM_CP_SPECIAL_MASK = 0x000f,
/* Special: no change to PE state: writes ignored, reads ignored. */
ARM_CP_NOP = 0x0001,
/* Special: sysreg is WFI, for v5 and v6. */
ARM_CP_WFI = 0x0002,
/* Special: sysreg is NZCV. */
ARM_CP_NZCV = 0x0003,
/* Special: sysreg is CURRENTEL. */
ARM_CP_CURRENTEL = 0x0004,
/* Special: sysreg is DC ZVA or similar. */
ARM_CP_DC_ZVA = 0x0005,
ARM_CP_DC_GVA = 0x0006,
ARM_CP_DC_GZVA = 0x0007,
/* Flag: reads produce resetvalue; writes ignored. */
ARM_CP_CONST = 1 << 4,
/* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */
ARM_CP_64BIT = 1 << 5,
/*
* Flag: TB should not be ended after a write to this register
* (the default is that the TB ends after cp writes).
*/
ARM_CP_SUPPRESS_TB_END = 1 << 6,
/*
* Flag: Permit a register definition to override a previous definition
* for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new
* or the old must have the ARM_CP_OVERRIDE bit set.
*/
ARM_CP_OVERRIDE = 1 << 7,
/*
* Flag: Register is an alias view of some underlying state which is also
* visible via another register, and that the other register is handling
* migration and reset; registers marked ARM_CP_ALIAS will not be migrated
* but may have their state set by syncing of register state from KVM.
*/
ARM_CP_ALIAS = 1 << 8,
/*
* Flag: Register does I/O and therefore its accesses need to be marked
* with gen_io_start() and also end the TB. In particular, registers which
* implement clocks or timers require this.
*/
ARM_CP_IO = 1 << 9,
/*
* Flag: Register has no underlying state and does not support raw access
* for state saving/loading; it will not be used for either migration or
* KVM state synchronization. Typically this is for "registers" which are
* actually used as instructions for cache maintenance and so on.
*/
ARM_CP_NO_RAW = 1 << 10,
/*
* Flag: The read or write hook might raise an exception; the generated
* code will synchronize the CPU state before calling the hook so that it
* is safe for the hook to call raise_exception().
*/
ARM_CP_RAISES_EXC = 1 << 11,
/*
* Flag: Writes to the sysreg might change the exception level - typically
* on older ARM chips. For those cases we need to re-read the new el when
* recomputing the translation flags.
*/
ARM_CP_NEWEL = 1 << 12,
/*
* Flag: Access check for this sysreg is identical to accessing FPU state
* from an instruction: use translation fp_access_check().
*/
ARM_CP_FPU = 1 << 13,
/*
* Flag: Access check for this sysreg is identical to accessing SVE state
* from an instruction: use translation sve_access_check().
*/
ARM_CP_SVE = 1 << 14,
/* Flag: Do not expose in gdb sysreg xml. */
ARM_CP_NO_GDB = 1 << 15,
target/arm: Handle cpreg registration for missing EL More gracefully handle cpregs when EL2 and/or EL3 are missing. If the reg is entirely inaccessible, do not register it at all. If the reg is for EL2, and EL3 is present but EL2 is not, either discard, squash to res0, const, or keep unchanged. Per rule RJFFP, mark the 4 aarch32 hypervisor access registers with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF. Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ. This will simplify cpreg registration for conditional arm features. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-06 20:02:19 +02:00
/*
* Flags: If EL3 but not EL2...
* - UNDEF: discard the cpreg,
* - KEEP: retain the cpreg as is,
* - C_NZ: set const on the cpreg, but retain resetvalue,
* - else: set const on the cpreg, zero resetvalue, aka RES0.
* See rule RJFFP in section D1.1.3 of DDI0487H.a.
*/
ARM_CP_EL3_NO_EL2_UNDEF = 1 << 16,
ARM_CP_EL3_NO_EL2_KEEP = 1 << 17,
ARM_CP_EL3_NO_EL2_C_NZ = 1 << 18,
target/arm: Add ARM_CP_SME This will be used for controlling access to SME cpregs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-20 19:51:48 +02:00
/*
* Flag: Access check for this sysreg is constrained by the
* ARM pseudocode function CheckSMEAccess().
*/
ARM_CP_SME = 1 << 19,
target/arm: Reorg ARMCPRegInfo type field bits Instead of defining ARM_CP_FLAG_MASK to remove flags, define ARM_CP_SPECIAL_MASK to isolate special cases. Sort the specials to the low bits. Use an enum. Split the large comment block so as to document each value separately. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:47 +02:00
};
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/*
* Valid values for ARMCPRegInfo state field, indicating which of
* the AArch32 and AArch64 execution states this register is visible in.
* If the reginfo doesn't explicitly specify then it is AArch32 only.
* If the reginfo is declared to be visible in both states then a second
* reginfo is synthesised for the AArch32 view of the AArch64 register,
* such that the AArch32 view is the lower 32 bits of the AArch64 one.
* Note that we rely on the values of these enums as we iterate through
* the various states in some places.
*/
target/arm: Name CPState type Give this enum a name and use in ARMCPRegInfo, add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:50 +02:00
typedef enum {
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
ARM_CP_STATE_AA32 = 0,
ARM_CP_STATE_AA64 = 1,
ARM_CP_STATE_BOTH = 2,
target/arm: Name CPState type Give this enum a name and use in ARMCPRegInfo, add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:50 +02:00
} CPState;
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/*
* ARM CP register secure state flags. These flags identify security state
* attributes for a given CP register entry.
* The existence of both or neither secure and non-secure flags indicates that
* the register has both a secure and non-secure hash entry. A single one of
* these flags causes the register to only be hashed for the specified
* security state.
* Although definitions may have any combination of the S/NS bits, each
* registered entry will only have one to identify whether the entry is secure
* or non-secure.
*/
target/arm: Name CPSecureState type Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 is handled in define_one_arm_cp_reg_with_opaque. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:51 +02:00
typedef enum {
ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
target/arm: Name CPSecureState type Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 is handled in define_one_arm_cp_reg_with_opaque. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:51 +02:00
} CPSecureState;
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/*
* Access rights:
* We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
* defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
* PL2 (hyp). The other level which has Read and Write bits is Secure PL1
* (ie any of the privileged modes in Secure state, or Monitor mode).
* If a register is accessible in one privilege level it's always accessible
* in higher privilege levels too. Since "Secure PL1" also follows this rule
* (ie anything visible in PL2 is visible in S-PL1, some things are only
* visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
* terminology a little and call this PL3.
* In AArch64 things are somewhat simpler as the PLx bits line up exactly
* with the ELx exception levels.
*
* If access permissions for a register are more complex than can be
* described with these bits, then use a laxer set of restrictions, and
* do the more restrictive/complex check inside a helper function.
*/
target/arm: Change cpreg access permissions to enum Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:49 +02:00
typedef enum {
PL3_R = 0x80,
PL3_W = 0x40,
PL2_R = 0x20 | PL3_R,
PL2_W = 0x10 | PL3_W,
PL1_R = 0x08 | PL2_R,
PL1_W = 0x04 | PL2_W,
PL0_R = 0x02 | PL1_R,
PL0_W = 0x01 | PL1_W,
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
target/arm: Change cpreg access permissions to enum Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:49 +02:00
/*
* For user-mode some registers are accessible to EL0 via a kernel
* trap-and-emulate ABI. In this case we define the read permissions
* as actually being PL0_R. However some bits of any given register
* may still be masked.
*/
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
#ifdef CONFIG_USER_ONLY
target/arm: Change cpreg access permissions to enum Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:49 +02:00
PL0U_R = PL0_R,
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
#else
target/arm: Change cpreg access permissions to enum Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:49 +02:00
PL0U_R = PL1_R,
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
#endif
target/arm: Change cpreg access permissions to enum Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:49 +02:00
PL3_RW = PL3_R | PL3_W,
PL2_RW = PL2_R | PL2_W,
PL1_RW = PL1_R | PL1_W,
PL0_RW = PL0_R | PL0_W,
} CPAccessRights;
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
typedef enum CPAccessResult {
/* Access is permitted */
CP_ACCESS_OK = 0,
target/arm: Reorg CPAccessResult and access_check_cp_reg Rearrange the values of the enumerators of CPAccessResult so that we may directly extract the target el. For the two special cases in access_check_cp_reg, use CPAccessResult. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:44 +02:00
/*
* Combined with one of the following, the low 2 bits indicate the
* target exception level. If 0, the exception is taken to the usual
* target EL (EL1 or PL1 if in EL0, otherwise to the current EL).
*/
CP_ACCESS_EL_MASK = 3,
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/*
* Access fails due to a configurable trap or enable which would
* result in a categorized exception syndrome giving information about
* the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
target/arm: Reorg CPAccessResult and access_check_cp_reg Rearrange the values of the enumerators of CPAccessResult so that we may directly extract the target el. For the two special cases in access_check_cp_reg, use CPAccessResult. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:44 +02:00
* 0xc or 0x18).
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
*/
target/arm: Reorg CPAccessResult and access_check_cp_reg Rearrange the values of the enumerators of CPAccessResult so that we may directly extract the target el. For the two special cases in access_check_cp_reg, use CPAccessResult. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:44 +02:00
CP_ACCESS_TRAP = (1 << 2),
CP_ACCESS_TRAP_EL2 = CP_ACCESS_TRAP | 2,
CP_ACCESS_TRAP_EL3 = CP_ACCESS_TRAP | 3,
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/*
* Access fails and results in an exception syndrome 0x0 ("uncategorized").
* Note that this is not a catch-all case -- the set of cases which may
* result in this failure is specifically defined by the architecture.
target/arm: Remove CP_ACCESS_TRAP_UNCATEGORIZED_{EL2, EL3} We added the CPAccessResult values CP_ACCESS_TRAP_UNCATEGORIZED_EL2 and CP_ACCESS_TRAP_UNCATEGORIZED_EL3 purely in order to use them in the ats_access() function, but doing so was incorrect (a bug fixed in a previous commit). There aren't any cases where we want an access function to be able to request a trap to EL2 or EL3 with a zero syndrome value, so remove these enum values. As well as cleaning up dead code, the motivation here is that we'd like to implement fine-grained-trap handling in helper_access_check_cp_reg(). Although the fine-grained traps to EL2 are always lower priority than trap-to-same-EL and higher priority than trap-to-EL3, they are in the middle of various other kinds of trap-to-EL2. Knowing that a trap-to-EL2 must always for us have the same syndrome (ie that an access function will return CP_ACCESS_TRAP_EL2 and there is no other kind of trap-to-EL2 enum value) means we don't have to try to choose which of the two syndrome values to report if the access would trap to EL2 both for the fine-grained-trap and because the access function requires it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-4-peter.maydell@linaro.org Message-id: 20230127175507.2895013-4-peter.maydell@linaro.org
2023-01-30 19:24:39 +01:00
* This trap is always to the usual target EL, never directly to a
* specified target EL.
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
*/
target/arm: Reorg CPAccessResult and access_check_cp_reg Rearrange the values of the enumerators of CPAccessResult so that we may directly extract the target el. For the two special cases in access_check_cp_reg, use CPAccessResult. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:44 +02:00
CP_ACCESS_TRAP_UNCATEGORIZED = (2 << 2),
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
} CPAccessResult;
target/arm: Define the FEAT_FGT registers Define the system registers which are provided by the FEAT_FGT fine-grained trap architectural feature: HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2 All these registers are a set of bit fields, where each bit is set for a trap and clear to not trap on a particular system register access. The R and W register pairs are for system registers, allowing trapping to be done separately for reads and writes; the I register is for system instructions where trapping is on instruction execution. The data storage in the CPU state struct is arranged as a set of arrays rather than separate fields so that when we're looking up the bits for a system register access we can just index into the array rather than having to use a switch to select a named struct member. The later FEAT_FGT2 will add extra elements to these arrays. The field definitions for the new registers are in cpregs.h because in practice the code that needs them is code that also needs the cpregs information; cpu.h is included in a lot more files. We're also going to add some FGT-specific definitions to cpregs.h in the next commit. We do not implement HAFGRTR_EL2, because we don't implement FEAT_AMUv1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-9-peter.maydell@linaro.org Message-id: 20230127175507.2895013-9-peter.maydell@linaro.org
2023-01-30 19:24:44 +01:00
/* Indexes into fgt_read[] */
#define FGTREG_HFGRTR 0
#define FGTREG_HDFGRTR 1
/* Indexes into fgt_write[] */
#define FGTREG_HFGWTR 0
#define FGTREG_HDFGWTR 1
/* Indexes into fgt_exec[] */
#define FGTREG_HFGITR 0
FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1)
FIELD(HFGRTR_EL2, AFSR1_EL1, 1, 1)
FIELD(HFGRTR_EL2, AIDR_EL1, 2, 1)
FIELD(HFGRTR_EL2, AMAIR_EL1, 3, 1)
FIELD(HFGRTR_EL2, APDAKEY, 4, 1)
FIELD(HFGRTR_EL2, APDBKEY, 5, 1)
FIELD(HFGRTR_EL2, APGAKEY, 6, 1)
FIELD(HFGRTR_EL2, APIAKEY, 7, 1)
FIELD(HFGRTR_EL2, APIBKEY, 8, 1)
FIELD(HFGRTR_EL2, CCSIDR_EL1, 9, 1)
FIELD(HFGRTR_EL2, CLIDR_EL1, 10, 1)
FIELD(HFGRTR_EL2, CONTEXTIDR_EL1, 11, 1)
FIELD(HFGRTR_EL2, CPACR_EL1, 12, 1)
FIELD(HFGRTR_EL2, CSSELR_EL1, 13, 1)
FIELD(HFGRTR_EL2, CTR_EL0, 14, 1)
FIELD(HFGRTR_EL2, DCZID_EL0, 15, 1)
FIELD(HFGRTR_EL2, ESR_EL1, 16, 1)
FIELD(HFGRTR_EL2, FAR_EL1, 17, 1)
FIELD(HFGRTR_EL2, ISR_EL1, 18, 1)
FIELD(HFGRTR_EL2, LORC_EL1, 19, 1)
FIELD(HFGRTR_EL2, LOREA_EL1, 20, 1)
FIELD(HFGRTR_EL2, LORID_EL1, 21, 1)
FIELD(HFGRTR_EL2, LORN_EL1, 22, 1)
FIELD(HFGRTR_EL2, LORSA_EL1, 23, 1)
FIELD(HFGRTR_EL2, MAIR_EL1, 24, 1)
FIELD(HFGRTR_EL2, MIDR_EL1, 25, 1)
FIELD(HFGRTR_EL2, MPIDR_EL1, 26, 1)
FIELD(HFGRTR_EL2, PAR_EL1, 27, 1)
FIELD(HFGRTR_EL2, REVIDR_EL1, 28, 1)
FIELD(HFGRTR_EL2, SCTLR_EL1, 29, 1)
FIELD(HFGRTR_EL2, SCXTNUM_EL1, 30, 1)
FIELD(HFGRTR_EL2, SCXTNUM_EL0, 31, 1)
FIELD(HFGRTR_EL2, TCR_EL1, 32, 1)
FIELD(HFGRTR_EL2, TPIDR_EL1, 33, 1)
FIELD(HFGRTR_EL2, TPIDRRO_EL0, 34, 1)
FIELD(HFGRTR_EL2, TPIDR_EL0, 35, 1)
FIELD(HFGRTR_EL2, TTBR0_EL1, 36, 1)
FIELD(HFGRTR_EL2, TTBR1_EL1, 37, 1)
FIELD(HFGRTR_EL2, VBAR_EL1, 38, 1)
FIELD(HFGRTR_EL2, ICC_IGRPENN_EL1, 39, 1)
FIELD(HFGRTR_EL2, ERRIDR_EL1, 40, 1)
FIELD(HFGRTR_EL2, ERRSELR_EL1, 41, 1)
FIELD(HFGRTR_EL2, ERXFR_EL1, 42, 1)
FIELD(HFGRTR_EL2, ERXCTLR_EL1, 43, 1)
FIELD(HFGRTR_EL2, ERXSTATUS_EL1, 44, 1)
FIELD(HFGRTR_EL2, ERXMISCN_EL1, 45, 1)
FIELD(HFGRTR_EL2, ERXPFGF_EL1, 46, 1)
FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1)
FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1)
FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1)
FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1)
/* 51-53: RES0 */
FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1)
FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1)
/* 56-63: RES0 */
/* These match HFGRTR but bits for RO registers are RES0 */
FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1)
FIELD(HFGWTR_EL2, AFSR1_EL1, 1, 1)
FIELD(HFGWTR_EL2, AMAIR_EL1, 3, 1)
FIELD(HFGWTR_EL2, APDAKEY, 4, 1)
FIELD(HFGWTR_EL2, APDBKEY, 5, 1)
FIELD(HFGWTR_EL2, APGAKEY, 6, 1)
FIELD(HFGWTR_EL2, APIAKEY, 7, 1)
FIELD(HFGWTR_EL2, APIBKEY, 8, 1)
FIELD(HFGWTR_EL2, CONTEXTIDR_EL1, 11, 1)
FIELD(HFGWTR_EL2, CPACR_EL1, 12, 1)
FIELD(HFGWTR_EL2, CSSELR_EL1, 13, 1)
FIELD(HFGWTR_EL2, ESR_EL1, 16, 1)
FIELD(HFGWTR_EL2, FAR_EL1, 17, 1)
FIELD(HFGWTR_EL2, LORC_EL1, 19, 1)
FIELD(HFGWTR_EL2, LOREA_EL1, 20, 1)
FIELD(HFGWTR_EL2, LORN_EL1, 22, 1)
FIELD(HFGWTR_EL2, LORSA_EL1, 23, 1)
FIELD(HFGWTR_EL2, MAIR_EL1, 24, 1)
FIELD(HFGWTR_EL2, PAR_EL1, 27, 1)
FIELD(HFGWTR_EL2, SCTLR_EL1, 29, 1)
FIELD(HFGWTR_EL2, SCXTNUM_EL1, 30, 1)
FIELD(HFGWTR_EL2, SCXTNUM_EL0, 31, 1)
FIELD(HFGWTR_EL2, TCR_EL1, 32, 1)
FIELD(HFGWTR_EL2, TPIDR_EL1, 33, 1)
FIELD(HFGWTR_EL2, TPIDRRO_EL0, 34, 1)
FIELD(HFGWTR_EL2, TPIDR_EL0, 35, 1)
FIELD(HFGWTR_EL2, TTBR0_EL1, 36, 1)
FIELD(HFGWTR_EL2, TTBR1_EL1, 37, 1)
FIELD(HFGWTR_EL2, VBAR_EL1, 38, 1)
FIELD(HFGWTR_EL2, ICC_IGRPENN_EL1, 39, 1)
FIELD(HFGWTR_EL2, ERRSELR_EL1, 41, 1)
FIELD(HFGWTR_EL2, ERXCTLR_EL1, 43, 1)
FIELD(HFGWTR_EL2, ERXSTATUS_EL1, 44, 1)
FIELD(HFGWTR_EL2, ERXMISCN_EL1, 45, 1)
FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1)
FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1)
FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1)
FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1)
FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1)
FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1)
FIELD(HFGITR_EL2, ICIALLUIS, 0, 1)
FIELD(HFGITR_EL2, ICIALLU, 1, 1)
FIELD(HFGITR_EL2, ICIVAU, 2, 1)
FIELD(HFGITR_EL2, DCIVAC, 3, 1)
FIELD(HFGITR_EL2, DCISW, 4, 1)
FIELD(HFGITR_EL2, DCCSW, 5, 1)
FIELD(HFGITR_EL2, DCCISW, 6, 1)
FIELD(HFGITR_EL2, DCCVAU, 7, 1)
FIELD(HFGITR_EL2, DCCVAP, 8, 1)
FIELD(HFGITR_EL2, DCCVADP, 9, 1)
FIELD(HFGITR_EL2, DCCIVAC, 10, 1)
FIELD(HFGITR_EL2, DCZVA, 11, 1)
FIELD(HFGITR_EL2, ATS1E1R, 12, 1)
FIELD(HFGITR_EL2, ATS1E1W, 13, 1)
FIELD(HFGITR_EL2, ATS1E0R, 14, 1)
FIELD(HFGITR_EL2, ATS1E0W, 15, 1)
FIELD(HFGITR_EL2, ATS1E1RP, 16, 1)
FIELD(HFGITR_EL2, ATS1E1WP, 17, 1)
FIELD(HFGITR_EL2, TLBIVMALLE1OS, 18, 1)
FIELD(HFGITR_EL2, TLBIVAE1OS, 19, 1)
FIELD(HFGITR_EL2, TLBIASIDE1OS, 20, 1)
FIELD(HFGITR_EL2, TLBIVAAE1OS, 21, 1)
FIELD(HFGITR_EL2, TLBIVALE1OS, 22, 1)
FIELD(HFGITR_EL2, TLBIVAALE1OS, 23, 1)
FIELD(HFGITR_EL2, TLBIRVAE1OS, 24, 1)
FIELD(HFGITR_EL2, TLBIRVAAE1OS, 25, 1)
FIELD(HFGITR_EL2, TLBIRVALE1OS, 26, 1)
FIELD(HFGITR_EL2, TLBIRVAALE1OS, 27, 1)
FIELD(HFGITR_EL2, TLBIVMALLE1IS, 28, 1)
FIELD(HFGITR_EL2, TLBIVAE1IS, 29, 1)
FIELD(HFGITR_EL2, TLBIASIDE1IS, 30, 1)
FIELD(HFGITR_EL2, TLBIVAAE1IS, 31, 1)
FIELD(HFGITR_EL2, TLBIVALE1IS, 32, 1)
FIELD(HFGITR_EL2, TLBIVAALE1IS, 33, 1)
FIELD(HFGITR_EL2, TLBIRVAE1IS, 34, 1)
FIELD(HFGITR_EL2, TLBIRVAAE1IS, 35, 1)
FIELD(HFGITR_EL2, TLBIRVALE1IS, 36, 1)
FIELD(HFGITR_EL2, TLBIRVAALE1IS, 37, 1)
FIELD(HFGITR_EL2, TLBIRVAE1, 38, 1)
FIELD(HFGITR_EL2, TLBIRVAAE1, 39, 1)
FIELD(HFGITR_EL2, TLBIRVALE1, 40, 1)
FIELD(HFGITR_EL2, TLBIRVAALE1, 41, 1)
FIELD(HFGITR_EL2, TLBIVMALLE1, 42, 1)
FIELD(HFGITR_EL2, TLBIVAE1, 43, 1)
FIELD(HFGITR_EL2, TLBIASIDE1, 44, 1)
FIELD(HFGITR_EL2, TLBIVAAE1, 45, 1)
FIELD(HFGITR_EL2, TLBIVALE1, 46, 1)
FIELD(HFGITR_EL2, TLBIVAALE1, 47, 1)
FIELD(HFGITR_EL2, CFPRCTX, 48, 1)
FIELD(HFGITR_EL2, DVPRCTX, 49, 1)
FIELD(HFGITR_EL2, CPPRCTX, 50, 1)
FIELD(HFGITR_EL2, ERET, 51, 1)
FIELD(HFGITR_EL2, SVC_EL0, 52, 1)
FIELD(HFGITR_EL2, SVC_EL1, 53, 1)
FIELD(HFGITR_EL2, DCCVAC, 54, 1)
FIELD(HFGITR_EL2, NBRBINJ, 55, 1)
FIELD(HFGITR_EL2, NBRBIALL, 56, 1)
FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1)
FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1)
FIELD(HDFGRTR_EL2, DBGWCRN_EL1, 2, 1)
FIELD(HDFGRTR_EL2, DBGWVRN_EL1, 3, 1)
FIELD(HDFGRTR_EL2, MDSCR_EL1, 4, 1)
FIELD(HDFGRTR_EL2, DBGCLAIM, 5, 1)
FIELD(HDFGRTR_EL2, DBGAUTHSTATUS_EL1, 6, 1)
FIELD(HDFGRTR_EL2, DBGPRCR_EL1, 7, 1)
/* 8: RES0: OSLAR_EL1 is WO */
FIELD(HDFGRTR_EL2, OSLSR_EL1, 9, 1)
FIELD(HDFGRTR_EL2, OSECCR_EL1, 10, 1)
FIELD(HDFGRTR_EL2, OSDLR_EL1, 11, 1)
FIELD(HDFGRTR_EL2, PMEVCNTRN_EL0, 12, 1)
FIELD(HDFGRTR_EL2, PMEVTYPERN_EL0, 13, 1)
FIELD(HDFGRTR_EL2, PMCCFILTR_EL0, 14, 1)
FIELD(HDFGRTR_EL2, PMCCNTR_EL0, 15, 1)
FIELD(HDFGRTR_EL2, PMCNTEN, 16, 1)
FIELD(HDFGRTR_EL2, PMINTEN, 17, 1)
FIELD(HDFGRTR_EL2, PMOVS, 18, 1)
FIELD(HDFGRTR_EL2, PMSELR_EL0, 19, 1)
/* 20: RES0: PMSWINC_EL0 is WO */
/* 21: RES0: PMCR_EL0 is WO */
FIELD(HDFGRTR_EL2, PMMIR_EL1, 22, 1)
FIELD(HDFGRTR_EL2, PMBLIMITR_EL1, 23, 1)
FIELD(HDFGRTR_EL2, PMBPTR_EL1, 24, 1)
FIELD(HDFGRTR_EL2, PMBSR_EL1, 25, 1)
FIELD(HDFGRTR_EL2, PMSCR_EL1, 26, 1)
FIELD(HDFGRTR_EL2, PMSEVFR_EL1, 27, 1)
FIELD(HDFGRTR_EL2, PMSFCR_EL1, 28, 1)
FIELD(HDFGRTR_EL2, PMSICR_EL1, 29, 1)
FIELD(HDFGRTR_EL2, PMSIDR_EL1, 30, 1)
FIELD(HDFGRTR_EL2, PMSIRR_EL1, 31, 1)
FIELD(HDFGRTR_EL2, PMSLATFR_EL1, 32, 1)
FIELD(HDFGRTR_EL2, TRC, 33, 1)
FIELD(HDFGRTR_EL2, TRCAUTHSTATUS, 34, 1)
FIELD(HDFGRTR_EL2, TRCAUXCTLR, 35, 1)
FIELD(HDFGRTR_EL2, TRCCLAIM, 36, 1)
FIELD(HDFGRTR_EL2, TRCCNTVRn, 37, 1)
/* 38, 39: RES0 */
FIELD(HDFGRTR_EL2, TRCID, 40, 1)
FIELD(HDFGRTR_EL2, TRCIMSPECN, 41, 1)
/* 42: RES0: TRCOSLAR is WO */
FIELD(HDFGRTR_EL2, TRCOSLSR, 43, 1)
FIELD(HDFGRTR_EL2, TRCPRGCTLR, 44, 1)
FIELD(HDFGRTR_EL2, TRCSEQSTR, 45, 1)
FIELD(HDFGRTR_EL2, TRCSSCSRN, 46, 1)
FIELD(HDFGRTR_EL2, TRCSTATR, 47, 1)
FIELD(HDFGRTR_EL2, TRCVICTLR, 48, 1)
/* 49: RES0: TRFCR_EL1 is WO */
FIELD(HDFGRTR_EL2, TRBBASER_EL1, 50, 1)
FIELD(HDFGRTR_EL2, TRBIDR_EL1, 51, 1)
FIELD(HDFGRTR_EL2, TRBLIMITR_EL1, 52, 1)
FIELD(HDFGRTR_EL2, TRBMAR_EL1, 53, 1)
FIELD(HDFGRTR_EL2, TRBPTR_EL1, 54, 1)
FIELD(HDFGRTR_EL2, TRBSR_EL1, 55, 1)
FIELD(HDFGRTR_EL2, TRBTRG_EL1, 56, 1)
FIELD(HDFGRTR_EL2, PMUSERENR_EL0, 57, 1)
FIELD(HDFGRTR_EL2, PMCEIDN_EL0, 58, 1)
FIELD(HDFGRTR_EL2, NBRBIDR, 59, 1)
FIELD(HDFGRTR_EL2, NBRBCTL, 60, 1)
FIELD(HDFGRTR_EL2, NBRBDATA, 61, 1)
FIELD(HDFGRTR_EL2, NPMSNEVFR_EL1, 62, 1)
FIELD(HDFGRTR_EL2, PMBIDR_EL1, 63, 1)
/*
* These match HDFGRTR_EL2, but bits for RO registers are RES0.
* A few bits are for WO registers, where the HDFGRTR_EL2 bit is RES0.
*/
FIELD(HDFGWTR_EL2, DBGBCRN_EL1, 0, 1)
FIELD(HDFGWTR_EL2, DBGBVRN_EL1, 1, 1)
FIELD(HDFGWTR_EL2, DBGWCRN_EL1, 2, 1)
FIELD(HDFGWTR_EL2, DBGWVRN_EL1, 3, 1)
FIELD(HDFGWTR_EL2, MDSCR_EL1, 4, 1)
FIELD(HDFGWTR_EL2, DBGCLAIM, 5, 1)
FIELD(HDFGWTR_EL2, DBGPRCR_EL1, 7, 1)
FIELD(HDFGWTR_EL2, OSLAR_EL1, 8, 1)
FIELD(HDFGWTR_EL2, OSLSR_EL1, 9, 1)
FIELD(HDFGWTR_EL2, OSECCR_EL1, 10, 1)
FIELD(HDFGWTR_EL2, OSDLR_EL1, 11, 1)
FIELD(HDFGWTR_EL2, PMEVCNTRN_EL0, 12, 1)
FIELD(HDFGWTR_EL2, PMEVTYPERN_EL0, 13, 1)
FIELD(HDFGWTR_EL2, PMCCFILTR_EL0, 14, 1)
FIELD(HDFGWTR_EL2, PMCCNTR_EL0, 15, 1)
FIELD(HDFGWTR_EL2, PMCNTEN, 16, 1)
FIELD(HDFGWTR_EL2, PMINTEN, 17, 1)
FIELD(HDFGWTR_EL2, PMOVS, 18, 1)
FIELD(HDFGWTR_EL2, PMSELR_EL0, 19, 1)
FIELD(HDFGWTR_EL2, PMSWINC_EL0, 20, 1)
FIELD(HDFGWTR_EL2, PMCR_EL0, 21, 1)
FIELD(HDFGWTR_EL2, PMBLIMITR_EL1, 23, 1)
FIELD(HDFGWTR_EL2, PMBPTR_EL1, 24, 1)
FIELD(HDFGWTR_EL2, PMBSR_EL1, 25, 1)
FIELD(HDFGWTR_EL2, PMSCR_EL1, 26, 1)
FIELD(HDFGWTR_EL2, PMSEVFR_EL1, 27, 1)
FIELD(HDFGWTR_EL2, PMSFCR_EL1, 28, 1)
FIELD(HDFGWTR_EL2, PMSICR_EL1, 29, 1)
FIELD(HDFGWTR_EL2, PMSIRR_EL1, 31, 1)
FIELD(HDFGWTR_EL2, PMSLATFR_EL1, 32, 1)
FIELD(HDFGWTR_EL2, TRC, 33, 1)
FIELD(HDFGWTR_EL2, TRCAUXCTLR, 35, 1)
FIELD(HDFGWTR_EL2, TRCCLAIM, 36, 1)
FIELD(HDFGWTR_EL2, TRCCNTVRn, 37, 1)
FIELD(HDFGWTR_EL2, TRCIMSPECN, 41, 1)
FIELD(HDFGWTR_EL2, TRCOSLAR, 42, 1)
FIELD(HDFGWTR_EL2, TRCPRGCTLR, 44, 1)
FIELD(HDFGWTR_EL2, TRCSEQSTR, 45, 1)
FIELD(HDFGWTR_EL2, TRCSSCSRN, 46, 1)
FIELD(HDFGWTR_EL2, TRCVICTLR, 48, 1)
FIELD(HDFGWTR_EL2, TRFCR_EL1, 49, 1)
FIELD(HDFGWTR_EL2, TRBBASER_EL1, 50, 1)
FIELD(HDFGWTR_EL2, TRBLIMITR_EL1, 52, 1)
FIELD(HDFGWTR_EL2, TRBMAR_EL1, 53, 1)
FIELD(HDFGWTR_EL2, TRBPTR_EL1, 54, 1)
FIELD(HDFGWTR_EL2, TRBSR_EL1, 55, 1)
FIELD(HDFGWTR_EL2, TRBTRG_EL1, 56, 1)
FIELD(HDFGWTR_EL2, PMUSERENR_EL0, 57, 1)
FIELD(HDFGWTR_EL2, NBRBCTL, 60, 1)
FIELD(HDFGWTR_EL2, NBRBDATA, 61, 1)
FIELD(HDFGWTR_EL2, NPMSNEVFR_EL1, 62, 1)
target/arm: Implement FGT trapping infrastructure Implement the machinery for fine-grained traps on normal sysregs. Any sysreg with a fine-grained trap will set the new field to indicate which FGT register bit it should trap on. FGT traps only happen when an AArch64 EL2 enables them for an AArch64 EL1. They therefore are only relevant for AArch32 cpregs when the cpreg can be accessed from EL0. The logic in access_check_cp_reg() will check this, so it is safe to add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo. The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname which can be used to specify the FGT bit, eg .fgt = FGT_AFSR0_EL1 (We assume that there is no bit name duplication across the FGT registers, for brevity's sake.) Subsequent commits will add the .fgt fields to the relevant register definitions and define the FGT_nnn values for them. Note that some of the FGT traps are for instructions that we don't handle via the cpregs mechanisms (mostly these are instruction traps). Those we will have to handle separately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
2023-01-30 19:24:45 +01:00
/* Which fine-grained trap bit register to check, if any */
FIELD(FGT, TYPE, 10, 3)
FIELD(FGT, REV, 9, 1) /* Is bit sense reversed? */
FIELD(FGT, IDX, 6, 3) /* Index within a uint64_t[] array */
FIELD(FGT, BITPOS, 0, 6) /* Bit position within the uint64_t */
/*
* Macros to define FGT_##bitname enum constants to use in ARMCPRegInfo::fgt
* fields. We assume for brevity's sake that there are no duplicated
* bit names across the various FGT registers.
*/
#define DO_BIT(REG, BITNAME) \
FGT_##BITNAME = FGT_##REG | R_##REG##_EL2_##BITNAME##_SHIFT
/* Some bits have reversed sense, so 0 means trap and 1 means not */
#define DO_REV_BIT(REG, BITNAME) \
FGT_##BITNAME = FGT_##REG | FGT_REV | R_##REG##_EL2_##BITNAME##_SHIFT
typedef enum FGTBit {
/*
* These bits tell us which register arrays to use:
* if FGT_R is set then reads are checked against fgt_read[];
* if FGT_W is set then writes are checked against fgt_write[];
* if FGT_EXEC is set then all accesses are checked against fgt_exec[].
*
* For almost all bits in the R/W register pairs, the bit exists in
* both registers for a RW register, in HFGRTR/HDFGRTR for a RO register
* with the corresponding HFGWTR/HDFGTWTR bit being RES0, and vice-versa
* for a WO register. There are unfortunately a couple of exceptions
* (PMCR_EL0, TRFCR_EL1) where the register being trapped is RW but
* the FGT system only allows trapping of writes, not reads.
*
* Note that we arrange these bits so that a 0 FGTBit means "no trap".
*/
FGT_R = 1 << R_FGT_TYPE_SHIFT,
FGT_W = 2 << R_FGT_TYPE_SHIFT,
FGT_EXEC = 4 << R_FGT_TYPE_SHIFT,
FGT_RW = FGT_R | FGT_W,
/* Bit to identify whether trap bit is reversed sense */
FGT_REV = R_FGT_REV_MASK,
/*
* If a bit exists in HFGRTR/HDFGRTR then either the register being
* trapped is RO or the bit also exists in HFGWTR/HDFGWTR, so we either
* want to trap for both reads and writes or else it's harmless to mark
* it as trap-on-writes.
* If a bit exists only in HFGWTR/HDFGWTR then either the register being
* trapped is WO, or else it is one of the two oddball special cases
* which are RW but have only a write trap. We mark these as only
* FGT_W so we get the right behaviour for those special cases.
* (If a bit was added in future that provided only a read trap for an
* RW register we'd need to do something special to get the FGT_R bit
* only. But this seems unlikely to happen.)
*
* So for the DO_BIT/DO_REV_BIT macros: use FGT_HFGRTR/FGT_HDFGRTR if
* the bit exists in that register. Otherwise use FGT_HFGWTR/FGT_HDFGWTR.
*/
FGT_HFGRTR = FGT_RW | (FGTREG_HFGRTR << R_FGT_IDX_SHIFT),
FGT_HFGWTR = FGT_W | (FGTREG_HFGWTR << R_FGT_IDX_SHIFT),
FGT_HDFGRTR = FGT_RW | (FGTREG_HDFGRTR << R_FGT_IDX_SHIFT),
FGT_HDFGWTR = FGT_W | (FGTREG_HDFGWTR << R_FGT_IDX_SHIFT),
FGT_HFGITR = FGT_EXEC | (FGTREG_HFGITR << R_FGT_IDX_SHIFT),
target/arm: Mark up sysregs for HFGRTR bits 0..11 Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 0..11. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-11-peter.maydell@linaro.org Message-id: 20230127175507.2895013-11-peter.maydell@linaro.org
2023-01-30 19:24:46 +01:00
/* Trap bits in HFGRTR_EL2 / HFGWTR_EL2, starting from bit 0. */
DO_BIT(HFGRTR, AFSR0_EL1),
DO_BIT(HFGRTR, AFSR1_EL1),
DO_BIT(HFGRTR, AIDR_EL1),
DO_BIT(HFGRTR, AMAIR_EL1),
DO_BIT(HFGRTR, APDAKEY),
DO_BIT(HFGRTR, APDBKEY),
DO_BIT(HFGRTR, APGAKEY),
DO_BIT(HFGRTR, APIAKEY),
DO_BIT(HFGRTR, APIBKEY),
DO_BIT(HFGRTR, CCSIDR_EL1),
DO_BIT(HFGRTR, CLIDR_EL1),
DO_BIT(HFGRTR, CONTEXTIDR_EL1),
target/arm: Mark up sysregs for HFGRTR bits 12..23 Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 12..23. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-12-peter.maydell@linaro.org Message-id: 20230127175507.2895013-12-peter.maydell@linaro.org
2023-01-30 19:24:47 +01:00
DO_BIT(HFGRTR, CPACR_EL1),
DO_BIT(HFGRTR, CSSELR_EL1),
DO_BIT(HFGRTR, CTR_EL0),
DO_BIT(HFGRTR, DCZID_EL0),
DO_BIT(HFGRTR, ESR_EL1),
DO_BIT(HFGRTR, FAR_EL1),
DO_BIT(HFGRTR, ISR_EL1),
DO_BIT(HFGRTR, LORC_EL1),
DO_BIT(HFGRTR, LOREA_EL1),
DO_BIT(HFGRTR, LORID_EL1),
DO_BIT(HFGRTR, LORN_EL1),
DO_BIT(HFGRTR, LORSA_EL1),
target/arm: Mark up sysregs for HFGRTR bits 24..35 Mark up the sysreg definitions for the registers trapped by HFGRTR/HFGWTR bits 24..35. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-13-peter.maydell@linaro.org Message-id: 20230127175507.2895013-13-peter.maydell@linaro.org
2023-01-30 19:24:48 +01:00
DO_BIT(HFGRTR, MAIR_EL1),
DO_BIT(HFGRTR, MIDR_EL1),
DO_BIT(HFGRTR, MPIDR_EL1),
DO_BIT(HFGRTR, PAR_EL1),
DO_BIT(HFGRTR, REVIDR_EL1),
DO_BIT(HFGRTR, SCTLR_EL1),
DO_BIT(HFGRTR, SCXTNUM_EL1),
DO_BIT(HFGRTR, SCXTNUM_EL0),
DO_BIT(HFGRTR, TCR_EL1),
DO_BIT(HFGRTR, TPIDR_EL1),
DO_BIT(HFGRTR, TPIDRRO_EL0),
DO_BIT(HFGRTR, TPIDR_EL0),
target/arm: Implement FGT trapping infrastructure Implement the machinery for fine-grained traps on normal sysregs. Any sysreg with a fine-grained trap will set the new field to indicate which FGT register bit it should trap on. FGT traps only happen when an AArch64 EL2 enables them for an AArch64 EL1. They therefore are only relevant for AArch32 cpregs when the cpreg can be accessed from EL0. The logic in access_check_cp_reg() will check this, so it is safe to add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo. The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname which can be used to specify the FGT bit, eg .fgt = FGT_AFSR0_EL1 (We assume that there is no bit name duplication across the FGT registers, for brevity's sake.) Subsequent commits will add the .fgt fields to the relevant register definitions and define the FGT_nnn values for them. Note that some of the FGT traps are for instructions that we don't handle via the cpregs mechanisms (mostly these are instruction traps). Those we will have to handle separately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
2023-01-30 19:24:45 +01:00
} FGTBit;
#undef DO_BIT
#undef DO_REV_BIT
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
typedef struct ARMCPRegInfo ARMCPRegInfo;
/*
* Access functions for coprocessor registers. These cannot fail and
* may not raise exceptions.
*/
typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
uint64_t value);
/* Access permission check functions for coprocessor registers. */
typedef CPAccessResult CPAccessFn(CPUARMState *env,
const ARMCPRegInfo *opaque,
bool isread);
/* Hook function for register reset */
typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
#define CP_ANY 0xff
/* Definition of an ARM coprocessor register */
struct ARMCPRegInfo {
/* Name of register (useful mainly for debugging, need not be unique) */
const char *name;
/*
* Location of register: coprocessor number and (crn,crm,opc1,opc2)
* tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
* 'wildcard' field -- any value of that field in the MRC/MCR insn
* will be decoded to this register. The register read and write
* callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
* used by the program, so it is possible to register a wildcard and
* then behave differently on read/write if necessary.
* For 64 bit registers, only crm and opc1 are relevant; crn and opc2
* must both be zero.
* For AArch64-visible registers, opc0 is also used.
* Since there are no "coprocessors" in AArch64, cp is purely used as a
* way to distinguish (for KVM's benefit) guest-visible system registers
* from demuxed ones provided to preserve the "no side effects on
* KVM register read/write from QEMU" semantics. cp==0x13 is guest
* visible (to match KVM's encoding); cp==0 will be converted to
* cp==0x13 when the ARMCPRegInfo is registered, for convenience.
*/
uint8_t cp;
uint8_t crn;
uint8_t crm;
uint8_t opc0;
uint8_t opc1;
uint8_t opc2;
/* Execution state in which this register is visible: ARM_CP_STATE_* */
target/arm: Name CPState type Give this enum a name and use in ARMCPRegInfo, add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:50 +02:00
CPState state;
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/* Register type: ARM_CP_* bits/values */
int type;
/* Access rights: PL*_[RW] */
target/arm: Change cpreg access permissions to enum Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:49 +02:00
CPAccessRights access;
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/* Security state: ARM_CP_SECSTATE_* bits/values */
target/arm: Name CPSecureState type Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 is handled in define_one_arm_cp_reg_with_opaque. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:51 +02:00
CPSecureState secure;
target/arm: Implement FGT trapping infrastructure Implement the machinery for fine-grained traps on normal sysregs. Any sysreg with a fine-grained trap will set the new field to indicate which FGT register bit it should trap on. FGT traps only happen when an AArch64 EL2 enables them for an AArch64 EL1. They therefore are only relevant for AArch32 cpregs when the cpreg can be accessed from EL0. The logic in access_check_cp_reg() will check this, so it is safe to add a .fgt marking to an ARM_CP_STATE_BOTH ARMCPRegInfo. The DO_BIT and DO_REV_BIT macros define enum constants FGT_##bitname which can be used to specify the FGT bit, eg .fgt = FGT_AFSR0_EL1 (We assume that there is no bit name duplication across the FGT registers, for brevity's sake.) Subsequent commits will add the .fgt fields to the relevant register definitions and define the FGT_nnn values for them. Note that some of the FGT traps are for instructions that we don't handle via the cpregs mechanisms (mostly these are instruction traps). Those we will have to handle separately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Fuad Tabba <tabba@google.com> Message-id: 20230130182459.3309057-10-peter.maydell@linaro.org Message-id: 20230127175507.2895013-10-peter.maydell@linaro.org
2023-01-30 19:24:45 +01:00
/*
* Which fine-grained trap register bit to check, if any. This
* value encodes both the trap register and bit within it.
*/
FGTBit fgt;
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/*
* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
* this register was defined: can be used to hand data through to the
* register read/write functions, since they are passed the ARMCPRegInfo*.
*/
void *opaque;
/*
* Value of this register, if it is ARM_CP_CONST. Otherwise, if
* fieldoffset is non-zero, the reset value of the register.
*/
uint64_t resetvalue;
/*
* Offset of the field in CPUARMState for this register.
* This is not needed if either:
* 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
* 2. both readfn and writefn are specified
*/
ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
/*
* Offsets of the secure and non-secure fields in CPUARMState for the
* register if it is banked. These fields are only used during the static
* registration of a register. During hashing the bank associated
* with a given security state is copied to fieldoffset which is used from
* there on out.
*
* It is expected that register definitions use either fieldoffset or
* bank_fieldoffsets in the definition but not both. It is also expected
* that both bank offsets are set when defining a banked register. This
* use indicates that a register is banked.
*/
ptrdiff_t bank_fieldoffsets[2];
/*
* Function for making any access checks for this register in addition to
* those specified by the 'access' permissions bits. If NULL, no extra
* checks required. The access check is performed at runtime, not at
* translate time.
*/
CPAccessFn *accessfn;
/*
* Function for handling reads of this register. If NULL, then reads
* will be done by loading from the offset into CPUARMState specified
* by fieldoffset.
*/
CPReadFn *readfn;
/*
* Function for handling writes of this register. If NULL, then writes
* will be done by writing to the offset into CPUARMState specified
* by fieldoffset.
*/
CPWriteFn *writefn;
/*
* Function for doing a "raw" read; used when we need to copy
* coprocessor state to the kernel for KVM or out for
* migration. This only needs to be provided if there is also a
* readfn and it has side effects (for instance clear-on-read bits).
*/
CPReadFn *raw_readfn;
/*
* Function for doing a "raw" write; used when we need to copy KVM
* kernel coprocessor state into userspace, or for inbound
* migration. This only needs to be provided if there is also a
* writefn and it masks out "unwritable" bits or has write-one-to-clear
* or similar behaviour.
*/
CPWriteFn *raw_writefn;
/*
* Function for resetting the register. If NULL, then reset will be done
* by writing resetvalue to the field specified in fieldoffset. If
* fieldoffset is 0 then no reset will be done.
*/
CPResetFn *resetfn;
/*
* "Original" writefn and readfn.
* For ARMv8.1-VHE register aliases, we overwrite the read/write
* accessor functions of various EL1/EL0 to perform the runtime
* check for which sysreg should actually be modified, and then
* forwards the operation. Before overwriting the accessors,
* the original function is copied here, so that accesses that
* really do go to the EL1/EL0 version proceed normally.
* (The corresponding EL2 register is linked via opaque.)
*/
CPReadFn *orig_readfn;
CPWriteFn *orig_writefn;
};
/*
* Macros which are lvalues for the field in CPUARMState for the
* ARMCPRegInfo *ri.
*/
#define CPREG_FIELD32(env, ri) \
(*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
#define CPREG_FIELD64(env, ri) \
(*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:45 +02:00
void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *reg,
void *opaque);
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
{
target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:45 +02:00
define_one_arm_cp_reg_with_opaque(cpu, regs, NULL);
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
}
target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:45 +02:00
void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *regs,
void *opaque, size_t len);
#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \
do { \
QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \
ARRAY_SIZE(REGS)); \
} while (0)
#define define_arm_cp_regs(CPU, REGS) \
define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
/*
* Definition of an ARM co-processor register as viewed from
* userspace. This is used for presenting sanitised versions of
* registers to userspace when emulating the Linux AArch64 CPU
* ID/feature ABI (advertised as HWCAP_CPUID).
*/
typedef struct ARMCPRegUserSpaceInfo {
/* Name of register */
const char *name;
/* Is the name actually a glob pattern */
bool is_glob;
/* Only some bits are exported to user space */
uint64_t exported_bits;
/* Fixed bits are applied after the mask */
uint64_t fixed_bits;
} ARMCPRegUserSpaceInfo;
target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:45 +02:00
void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len,
const ARMCPRegUserSpaceInfo *mods,
size_t mods_len);
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:45 +02:00
#define modify_arm_cp_regs(REGS, MODS) \
do { \
QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) == 0); \
modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \
MODS, ARRAY_SIZE(MODS)); \
} while (0)
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/* CPWriteFn that can be used to implement writes-ignored behaviour */
void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value);
/* CPReadFn that can be used for read-as-zero behaviour */
uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
target/arm: Move define_debug_regs() to debug_helper.c The target/arm/helper.c file is very long and is a grabbag of all kinds of functionality. We have already a debug_helper.c which has code for implementing architectural debug. Move the code which defines the debug-related system registers out to this file also. This affects the define_debug_regs() function and the various functions and arrays which are used only by it. The functions raw_write() and arm_mdcr_el2_eff() and define_debug_regs() now need to be global rather than local to helper.c; everything else is pure code movement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-3-peter.maydell@linaro.org
2022-06-30 21:41:13 +02:00
/* CPWriteFn that just writes the value to ri->fieldoffset */
void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value);
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
/*
* CPResetFn that does nothing, for use if no reset is required even
* if fieldoffset is non zero.
*/
void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
/*
* Return true if this reginfo struct's field in the cpu state struct
* is 64 bits wide.
*/
static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
{
return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
}
static inline bool cp_access_ok(int current_el,
const ARMCPRegInfo *ri, int isread)
{
return (ri->access >> ((current_el * 2) + isread)) & 1;
}
/* Raw read of a coprocessor register (as needed for migration, etc) */
uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
target/arm: Implement FEAT_IDST The Armv8.4 feature FEAT_IDST specifies that exceptions generated by read accesses to the feature ID space should report a syndrome code of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED). The feature ID space is defined to be: op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7}, op2 == {0-7} In our implementation we might return the EC_UNCATEGORIZED syndrome value for a system register access in four cases: * no reginfo struct in the hashtable * cp_access_ok() fails (ie ri->access doesn't permit the access) * ri->accessfn returns CP_ACCESS_TRAP_UNCATEGORIZED at runtime * ri->type includes ARM_CP_RAISES_EXC, and the readfn raises an UNDEF exception at runtime We have very few regdefs that set ARM_CP_RAISES_EXC, and none of them are in the feature ID space. (In the unlikely event that any are added in future they would need to take care of setting the correct syndrome themselves.) This patch deals with the other three cases, and enables FEAT_IDST for AArch64 -cpu max. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220509155457.3560724-1-peter.maydell@linaro.org
2022-05-09 17:54:57 +02:00
/*
* Return true if the cp register encoding is in the "feature ID space" as
* defined by FEAT_IDST (and thus should be reported with ER_ELx.EC
* as EC_SYSTEMREGISTERTRAP rather than EC_UNCATEGORIZED).
*/
static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1,
uint8_t opc2,
uint8_t crn, uint8_t crm)
{
return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) &&
crn == 0 && crm < 8;
}
/*
* As arm_cpreg_encoding_in_idspace(), but take the encoding from an
* ARMCPRegInfo.
*/
static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri)
{
return ri->state == ARM_CP_STATE_AA64 &&
arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2,
ri->crn, ri->crm);
}
target/arm: Split out cpregs.h Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-01 07:49:43 +02:00
#endif /* TARGET_ARM_CPREGS_H */
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