2021-03-09 23:24:14 +01:00
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/*
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* Internal declarations for Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef TCG_INTERNAL_H
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2022-05-06 15:49:10 +02:00
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#define TCG_INTERNAL_H
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2021-03-09 23:24:14 +01:00
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2022-11-22 19:08:04 +01:00
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#ifdef CONFIG_TCG_INTERPRETER
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#include <ffi.h>
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#endif
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2021-03-09 23:24:14 +01:00
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#define TCG_HIGHWATER 1024
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2022-10-16 04:47:00 +02:00
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/*
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* Describe the calling convention of a given argument type.
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*/
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typedef enum {
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TCG_CALL_RET_NORMAL, /* by registers */
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} TCGCallReturnKind;
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typedef enum {
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TCG_CALL_ARG_NORMAL, /* by registers (continuing onto stack) */
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TCG_CALL_ARG_EVEN, /* like normal, but skipping odd slots */
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TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */
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TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */
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TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */
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} TCGCallArgumentKind;
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2022-11-11 01:09:37 +01:00
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typedef struct TCGCallArgumentLoc {
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TCGCallArgumentKind kind : 8;
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unsigned arg_slot : 8;
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unsigned ref_slot : 8;
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unsigned arg_idx : 4;
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unsigned tmp_subindex : 2;
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} TCGCallArgumentLoc;
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/* Avoid "unsigned < 0 is always false" Werror, when iarg_regs is empty. */
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#define REG_P(L) \
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((int)(L)->arg_slot < (int)ARRAY_SIZE(tcg_target_call_iarg_regs))
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2021-03-18 18:29:50 +01:00
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typedef struct TCGHelperInfo {
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void *func;
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const char *name;
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2022-11-22 19:08:04 +01:00
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#ifdef CONFIG_TCG_INTERPRETER
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ffi_cif *cif;
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#endif
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2022-11-11 01:09:37 +01:00
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unsigned typemask : 32;
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unsigned flags : 8;
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unsigned nr_in : 8;
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unsigned nr_out : 8;
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TCGCallReturnKind out_kind : 8;
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/* Maximum physical arguments are constrained by TCG_TYPE_I128. */
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TCGCallArgumentLoc in[MAX_CALL_IARGS * (128 / TCG_TARGET_REG_BITS)];
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2021-03-18 18:29:50 +01:00
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} TCGHelperInfo;
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2021-03-13 20:36:51 +01:00
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extern TCGContext tcg_init_ctx;
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2021-03-09 23:24:14 +01:00
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extern TCGContext **tcg_ctxs;
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2021-03-10 06:06:32 +01:00
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extern unsigned int tcg_cur_ctxs;
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extern unsigned int tcg_max_ctxs;
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2021-03-09 23:24:14 +01:00
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2021-03-10 05:52:45 +01:00
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void tcg_region_init(size_t tb_size, int splitwx, unsigned max_cpus);
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2021-03-09 23:24:14 +01:00
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bool tcg_region_alloc(TCGContext *s);
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void tcg_region_initial_alloc(TCGContext *s);
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void tcg_region_prologue_set(TCGContext *s);
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2021-03-18 23:40:07 +01:00
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static inline void *tcg_call_func(TCGOp *op)
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{
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return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op)];
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}
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2021-03-18 18:29:50 +01:00
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static inline const TCGHelperInfo *tcg_call_info(TCGOp *op)
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{
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return (void *)(uintptr_t)op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1];
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}
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2021-03-18 17:21:45 +01:00
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static inline unsigned tcg_call_flags(TCGOp *op)
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{
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2021-03-18 18:29:50 +01:00
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return tcg_call_info(op)->flags;
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2021-03-18 17:21:45 +01:00
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}
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2022-10-17 03:07:39 +02:00
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#if TCG_TARGET_REG_BITS == 32
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static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
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{
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2022-10-19 03:53:27 +02:00
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return temp_tcgv_i32(tcgv_i64_temp(t) + HOST_BIG_ENDIAN);
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2022-10-17 03:07:39 +02:00
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}
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static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
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{
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2022-10-19 03:53:27 +02:00
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return temp_tcgv_i32(tcgv_i64_temp(t) + !HOST_BIG_ENDIAN);
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2022-10-17 03:07:39 +02:00
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}
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#else
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extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable");
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extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable");
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#endif
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2021-03-09 23:24:14 +01:00
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#endif /* TCG_INTERNAL_H */
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