2018-05-04 19:05:51 +02:00
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/*
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* ARM SMMUv3 support - Internal API
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*
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Copyright (c) 2017 Red Hat, Inc.
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_ARM_SMMU_V3_INTERNAL_H
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#define HW_ARM_SMMU_V3_INTERNAL_H
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#include "hw/arm/smmu-common.h"
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/* MMIO Registers */
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REG32(IDR0, 0x0)
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FIELD(IDR0, S1P, 1 , 1)
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FIELD(IDR0, TTF, 2 , 2)
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FIELD(IDR0, COHACC, 4 , 1)
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FIELD(IDR0, ASID16, 12, 1)
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FIELD(IDR0, TTENDIAN, 21, 2)
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FIELD(IDR0, STALL_MODEL, 24, 2)
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FIELD(IDR0, TERM_MODEL, 26, 1)
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FIELD(IDR0, STLEVEL, 27, 2)
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REG32(IDR1, 0x4)
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FIELD(IDR1, SIDSIZE, 0 , 6)
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FIELD(IDR1, EVENTQS, 16, 5)
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FIELD(IDR1, CMDQS, 21, 5)
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#define SMMU_IDR1_SIDSIZE 16
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#define SMMU_CMDQS 19
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#define SMMU_EVENTQS 19
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REG32(IDR2, 0x8)
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REG32(IDR3, 0xc)
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REG32(IDR4, 0x10)
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REG32(IDR5, 0x14)
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FIELD(IDR5, OAS, 0, 3);
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FIELD(IDR5, GRAN4K, 4, 1);
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FIELD(IDR5, GRAN16K, 5, 1);
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FIELD(IDR5, GRAN64K, 6, 1);
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#define SMMU_IDR5_OAS 4
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REG32(IIDR, 0x1c)
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REG32(CR0, 0x20)
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FIELD(CR0, SMMU_ENABLE, 0, 1)
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FIELD(CR0, EVENTQEN, 2, 1)
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FIELD(CR0, CMDQEN, 3, 1)
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REG32(CR0ACK, 0x24)
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REG32(CR1, 0x28)
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REG32(CR2, 0x2c)
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REG32(STATUSR, 0x40)
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REG32(IRQ_CTRL, 0x50)
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FIELD(IRQ_CTRL, GERROR_IRQEN, 0, 1)
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FIELD(IRQ_CTRL, PRI_IRQEN, 1, 1)
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FIELD(IRQ_CTRL, EVENTQ_IRQEN, 2, 1)
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REG32(IRQ_CTRL_ACK, 0x54)
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REG32(GERROR, 0x60)
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FIELD(GERROR, CMDQ_ERR, 0, 1)
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FIELD(GERROR, EVENTQ_ABT_ERR, 2, 1)
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FIELD(GERROR, PRIQ_ABT_ERR, 3, 1)
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FIELD(GERROR, MSI_CMDQ_ABT_ERR, 4, 1)
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FIELD(GERROR, MSI_EVENTQ_ABT_ERR, 5, 1)
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FIELD(GERROR, MSI_PRIQ_ABT_ERR, 6, 1)
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FIELD(GERROR, MSI_GERROR_ABT_ERR, 7, 1)
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FIELD(GERROR, MSI_SFM_ERR, 8, 1)
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REG32(GERRORN, 0x64)
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#define A_GERROR_IRQ_CFG0 0x68 /* 64b */
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REG32(GERROR_IRQ_CFG1, 0x70)
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REG32(GERROR_IRQ_CFG2, 0x74)
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#define A_STRTAB_BASE 0x80 /* 64b */
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#define SMMU_BASE_ADDR_MASK 0xffffffffffe0
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REG32(STRTAB_BASE_CFG, 0x88)
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FIELD(STRTAB_BASE_CFG, FMT, 16, 2)
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FIELD(STRTAB_BASE_CFG, SPLIT, 6 , 5)
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FIELD(STRTAB_BASE_CFG, LOG2SIZE, 0 , 6)
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#define A_CMDQ_BASE 0x90 /* 64b */
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REG32(CMDQ_PROD, 0x98)
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REG32(CMDQ_CONS, 0x9c)
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FIELD(CMDQ_CONS, ERR, 24, 7)
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#define A_EVENTQ_BASE 0xa0 /* 64b */
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REG32(EVENTQ_PROD, 0xa8)
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REG32(EVENTQ_CONS, 0xac)
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#define A_EVENTQ_IRQ_CFG0 0xb0 /* 64b */
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REG32(EVENTQ_IRQ_CFG1, 0xb8)
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REG32(EVENTQ_IRQ_CFG2, 0xbc)
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#define A_IDREGS 0xfd0
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static inline int smmu_enabled(SMMUv3State *s)
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{
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return FIELD_EX32(s->cr[0], CR0, SMMU_ENABLE);
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}
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/* Command Queue Entry */
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typedef struct Cmd {
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uint32_t word[4];
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} Cmd;
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/* Event Queue Entry */
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typedef struct Evt {
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uint32_t word[8];
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} Evt;
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static inline uint32_t smmuv3_idreg(int regoffset)
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{
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/*
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* Return the value of the Primecell/Corelink ID registers at the
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* specified offset from the first ID register.
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* These value indicate an ARM implementation of MMU600 p1
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*/
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static const uint8_t smmuv3_ids[] = {
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0x04, 0, 0, 0, 0x84, 0xB4, 0xF0, 0x10, 0x0D, 0xF0, 0x05, 0xB1
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};
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return smmuv3_ids[regoffset / 4];
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}
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2018-05-04 19:05:51 +02:00
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static inline bool smmuv3_eventq_irq_enabled(SMMUv3State *s)
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{
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return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN);
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}
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static inline bool smmuv3_gerror_irq_enabled(SMMUv3State *s)
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{
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return FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN);
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}
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/* public until callers get introduced */
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void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask);
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void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t gerrorn);
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2018-05-04 19:05:51 +02:00
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#endif
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