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qemu-e2k/target/arm/t32.decode

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target/arm: Add stubs for aa32 decodetree Add the infrastructure that will become the new decoder. No instructions adjusted so far. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:52 +02:00
# Thumb2 instructions
#
# Copyright (c) 2019 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:53 +02:00
target/arm: Convert MSR (immediate) and hints Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:30:02 +02:00
&empty !extern
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:53 +02:00
&s_rrr_shi !extern s rd rn rm shim shty
target/arm: Convert Data Processing (reg-shifted-reg) Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:54 +02:00
&s_rrr_shr !extern s rn rd rm rs shty
target/arm: Convert Data Processing (immediate) Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:55 +02:00
&s_rri_rot !extern s rn rd imm rot
target/arm: Convert multiply and multiply accumulate Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:56 +02:00
&s_rrrr !extern s rd rn rm ra
&rrrr !extern rd rn rm ra
target/arm: Convert Saturating addition and subtraction Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:58 +02:00
&rrr !extern rd rn rm
target/arm: Convert MRS/MSR (banked, register) The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:30:03 +02:00
&msr_reg !extern rn r mask
&mrs_reg !extern rd r
&msr_bank !extern rn r sysm
&mrs_bank !extern rd r sysm
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:53 +02:00
# Data-processing (register)
%imm5_12_6 12:3 6:2
@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
&s_rrr_shi shim=%imm5_12_6
@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
&s_rrr_shi shim=%imm5_12_6 rn=0
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
{
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
}
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
{
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
}
{
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi
}
{
TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi
EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi
}
# PKHBT, PKHTB at opc1 = 0110
{
CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi
ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi
}
ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi
SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
{
CMP_xrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi
SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi
}
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
target/arm: Convert Data Processing (reg-shifted-reg) Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:54 +02:00
# Data-processing (register-shifted register)
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
&s_rrr_shr rn=0
target/arm: Convert Data Processing (immediate) Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:55 +02:00
# Data-processing (immediate)
%t32extrot 26:1 12:3 0:8 !function=t32_expandimm_rot
%t32extimm 26:1 12:3 0:8 !function=t32_expandimm_imm
@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \
&s_rri_rot imm=%t32extimm rot=%t32extrot
@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \
&s_rri_rot imm=%t32extimm rot=%t32extrot rn=0
@S_xri_rot ....... .... . rn:4 . ... .... ........ \
&s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0
{
TST_xri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot
AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot
}
BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot
{
MOV_rxi 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot
ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot
}
{
MVN_rxi 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot
ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot
}
{
TEQ_xri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot
EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot
}
{
CMN_xri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot
ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot
}
ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot
SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot
{
CMP_xri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot
SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot
}
RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
target/arm: Convert multiply and multiply accumulate Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:56 +02:00
# Multiply and multiply accumulate
@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0
@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0
@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr
target/arm: Convert Halfword multiply and multiply accumulate Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:59 +02:00
@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0
target/arm: Convert Saturating addition and subtraction Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:58 +02:00
@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr
target/arm: Convert multiply and multiply accumulate Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:56 +02:00
{
MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm
MLA 1111 1011 0000 .... .... .... 0000 .... @s0_rnadm
}
MLS 1111 1011 0000 .... .... .... 0001 .... @rnadm
SMULL 1111 1011 1000 .... .... .... 0000 .... @s0_rnadm
UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm
SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm
UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm
UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm
target/arm: Convert Halfword multiply and multiply accumulate Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:59 +02:00
{
SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm
SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm
}
{
SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm
SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm
}
{
SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm
SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm
}
{
SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm
SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm
}
{
SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm
SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm
}
{
SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm
SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm
}
SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm
SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm
SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm
SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm
target/arm: Convert Saturating addition and subtraction Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:29:58 +02:00
# Data-processing (two source registers)
QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm
QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm
QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm
QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm
target/arm: Convert MSR (immediate) and hints Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:30:02 +02:00
target/arm: Convert Cyclic Redundancy Check Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:30:04 +02:00
CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm
CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm
CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm
CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm
CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm
CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm
target/arm: Convert MSR (immediate) and hints Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:30:02 +02:00
# Branches and miscellaneous control
target/arm: Convert MRS/MSR (banked, register) The m-profile and a-profile decodings overlap. Only return false for the case of wrong profile; handle UNDEFINED for permission failure directly. This ensures that we don't accidentally pass an insn that applies to the wrong profile. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:30:03 +02:00
%msr_sysm 4:1 8:4
%mrs_sysm 4:1 16:4
{
{
YIELD 1111 0011 1010 1111 1000 0000 0000 0001
WFE 1111 0011 1010 1111 1000 0000 0000 0010
WFI 1111 0011 1010 1111 1000 0000 0000 0011
# TODO: Implement SEV, SEVL; may help SMP performance.
# SEV 1111 0011 1010 1111 1000 0000 0000 0100
# SEVL 1111 0011 1010 1111 1000 0000 0000 0101
# The canonical nop ends in 0000 0000, but the whole rest
# of the space is "reserved hint, behaves as nop".
NOP 1111 0011 1010 1111 1000 0000 ---- ----
}
# Note that the v7m insn overlaps both the normal and banked insn.
{
MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \
&mrs_bank sysm=%mrs_sysm
MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg
MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8
}
{
MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \
&msr_bank sysm=%msr_sysm
MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg
MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8
}
target/arm: Convert MSR (immediate) and hints Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 21:30:02 +02:00
}