2021-01-29 17:46:11 +01:00
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/*
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* Copyright © 2020, 2021 Oracle and/or its affiliates.
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*
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* This work is licensed under the terms of the GNU GPL-v2, version 2 or later.
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*
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/remote/machine.h"
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#include "io/channel.h"
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#include "hw/remote/mpqemu-link.h"
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#include "qapi/error.h"
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#include "sysemu/runstate.h"
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2021-01-29 17:46:16 +01:00
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#include "hw/pci/pci.h"
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2021-01-29 17:46:17 +01:00
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#include "exec/memattrs.h"
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2021-01-29 17:46:18 +01:00
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#include "hw/remote/memory.h"
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2021-01-29 17:46:19 +01:00
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#include "hw/remote/iohub.h"
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2021-01-29 17:46:21 +01:00
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#include "sysemu/reset.h"
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2021-01-29 17:46:16 +01:00
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static void process_config_write(QIOChannel *ioc, PCIDevice *dev,
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MPQemuMsg *msg, Error **errp);
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static void process_config_read(QIOChannel *ioc, PCIDevice *dev,
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MPQemuMsg *msg, Error **errp);
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2021-01-29 17:46:17 +01:00
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static void process_bar_write(QIOChannel *ioc, MPQemuMsg *msg, Error **errp);
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static void process_bar_read(QIOChannel *ioc, MPQemuMsg *msg, Error **errp);
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2021-01-29 17:46:21 +01:00
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static void process_device_reset_msg(QIOChannel *ioc, PCIDevice *dev,
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Error **errp);
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2021-01-29 17:46:11 +01:00
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void coroutine_fn mpqemu_remote_msg_loop_co(void *data)
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{
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g_autofree RemoteCommDev *com = (RemoteCommDev *)data;
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PCIDevice *pci_dev = NULL;
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Error *local_err = NULL;
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assert(com->ioc);
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pci_dev = com->dev;
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for (; !local_err;) {
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MPQemuMsg msg = {0};
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if (!mpqemu_msg_recv(&msg, com->ioc, &local_err)) {
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break;
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}
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if (!mpqemu_msg_valid(&msg)) {
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error_setg(&local_err, "Received invalid message from proxy"
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"in remote process pid="FMT_pid"",
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getpid());
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break;
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}
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switch (msg.cmd) {
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2021-01-29 17:46:16 +01:00
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case MPQEMU_CMD_PCI_CFGWRITE:
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process_config_write(com->ioc, pci_dev, &msg, &local_err);
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break;
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case MPQEMU_CMD_PCI_CFGREAD:
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process_config_read(com->ioc, pci_dev, &msg, &local_err);
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break;
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2021-01-29 17:46:17 +01:00
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case MPQEMU_CMD_BAR_WRITE:
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process_bar_write(com->ioc, &msg, &local_err);
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break;
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case MPQEMU_CMD_BAR_READ:
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process_bar_read(com->ioc, &msg, &local_err);
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break;
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2021-01-29 17:46:18 +01:00
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case MPQEMU_CMD_SYNC_SYSMEM:
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remote_sysmem_reconfig(&msg, &local_err);
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break;
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2021-01-29 17:46:19 +01:00
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case MPQEMU_CMD_SET_IRQFD:
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process_set_irqfd_msg(pci_dev, &msg);
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break;
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2021-01-29 17:46:21 +01:00
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case MPQEMU_CMD_DEVICE_RESET:
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process_device_reset_msg(com->ioc, pci_dev, &local_err);
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break;
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2021-01-29 17:46:11 +01:00
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default:
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error_setg(&local_err,
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"Unknown command (%d) received for device %s"
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" (pid="FMT_pid")",
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msg.cmd, DEVICE(pci_dev)->id, getpid());
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}
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}
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if (local_err) {
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error_report_err(local_err);
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_HOST_ERROR);
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} else {
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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}
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}
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2021-01-29 17:46:16 +01:00
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static void process_config_write(QIOChannel *ioc, PCIDevice *dev,
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MPQemuMsg *msg, Error **errp)
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{
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ERRP_GUARD();
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PciConfDataMsg *conf = (PciConfDataMsg *)&msg->data.pci_conf_data;
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MPQemuMsg ret = { 0 };
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if ((conf->addr + sizeof(conf->val)) > pci_config_size(dev)) {
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error_setg(errp, "Bad address for PCI config write, pid "FMT_pid".",
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getpid());
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ret.data.u64 = UINT64_MAX;
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} else {
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pci_default_write_config(dev, conf->addr, conf->val, conf->len);
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}
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ret.cmd = MPQEMU_CMD_RET;
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ret.size = sizeof(ret.data.u64);
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if (!mpqemu_msg_send(&ret, ioc, NULL)) {
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error_prepend(errp, "Error returning code to proxy, pid "FMT_pid": ",
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getpid());
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}
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}
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static void process_config_read(QIOChannel *ioc, PCIDevice *dev,
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MPQemuMsg *msg, Error **errp)
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{
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ERRP_GUARD();
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PciConfDataMsg *conf = (PciConfDataMsg *)&msg->data.pci_conf_data;
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MPQemuMsg ret = { 0 };
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if ((conf->addr + sizeof(conf->val)) > pci_config_size(dev)) {
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error_setg(errp, "Bad address for PCI config read, pid "FMT_pid".",
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getpid());
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ret.data.u64 = UINT64_MAX;
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} else {
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ret.data.u64 = pci_default_read_config(dev, conf->addr, conf->len);
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}
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ret.cmd = MPQEMU_CMD_RET;
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ret.size = sizeof(ret.data.u64);
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if (!mpqemu_msg_send(&ret, ioc, NULL)) {
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error_prepend(errp, "Error returning code to proxy, pid "FMT_pid": ",
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getpid());
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}
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}
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2021-01-29 17:46:17 +01:00
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static void process_bar_write(QIOChannel *ioc, MPQemuMsg *msg, Error **errp)
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{
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ERRP_GUARD();
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BarAccessMsg *bar_access = &msg->data.bar_access;
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AddressSpace *as =
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bar_access->memory ? &address_space_memory : &address_space_io;
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MPQemuMsg ret = { 0 };
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MemTxResult res;
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uint64_t val;
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if (!is_power_of_2(bar_access->size) ||
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(bar_access->size > sizeof(uint64_t))) {
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ret.data.u64 = UINT64_MAX;
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goto fail;
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}
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val = cpu_to_le64(bar_access->val);
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res = address_space_rw(as, bar_access->addr, MEMTXATTRS_UNSPECIFIED,
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(void *)&val, bar_access->size, true);
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if (res != MEMTX_OK) {
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error_setg(errp, "Bad address %"PRIx64" for mem write, pid "FMT_pid".",
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bar_access->addr, getpid());
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ret.data.u64 = -1;
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}
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fail:
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ret.cmd = MPQEMU_CMD_RET;
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ret.size = sizeof(ret.data.u64);
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if (!mpqemu_msg_send(&ret, ioc, NULL)) {
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error_prepend(errp, "Error returning code to proxy, pid "FMT_pid": ",
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getpid());
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}
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}
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static void process_bar_read(QIOChannel *ioc, MPQemuMsg *msg, Error **errp)
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{
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ERRP_GUARD();
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BarAccessMsg *bar_access = &msg->data.bar_access;
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MPQemuMsg ret = { 0 };
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AddressSpace *as;
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MemTxResult res;
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uint64_t val = 0;
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as = bar_access->memory ? &address_space_memory : &address_space_io;
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if (!is_power_of_2(bar_access->size) ||
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(bar_access->size > sizeof(uint64_t))) {
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val = UINT64_MAX;
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goto fail;
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}
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res = address_space_rw(as, bar_access->addr, MEMTXATTRS_UNSPECIFIED,
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(void *)&val, bar_access->size, false);
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if (res != MEMTX_OK) {
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error_setg(errp, "Bad address %"PRIx64" for mem read, pid "FMT_pid".",
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bar_access->addr, getpid());
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val = UINT64_MAX;
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}
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fail:
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ret.cmd = MPQEMU_CMD_RET;
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ret.data.u64 = le64_to_cpu(val);
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ret.size = sizeof(ret.data.u64);
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if (!mpqemu_msg_send(&ret, ioc, NULL)) {
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error_prepend(errp, "Error returning code to proxy, pid "FMT_pid": ",
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getpid());
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}
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}
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2021-01-29 17:46:21 +01:00
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static void process_device_reset_msg(QIOChannel *ioc, PCIDevice *dev,
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Error **errp)
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{
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DeviceClass *dc = DEVICE_GET_CLASS(dev);
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DeviceState *s = DEVICE(dev);
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MPQemuMsg ret = { 0 };
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if (dc->reset) {
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dc->reset(s);
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}
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ret.cmd = MPQEMU_CMD_RET;
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mpqemu_msg_send(&ret, ioc, errp);
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}
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