314 lines
9.9 KiB
C
314 lines
9.9 KiB
C
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/*
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* Altera Nios II helper routines.
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include <stdio.h>
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#include <string.h>
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#include <assert.h>
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#include "cpu.h"
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#include "qemu/osdep.h"
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#include "qemu/host-utils.h"
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#include "qapi/error.h"
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#include "exec/exec-all.h"
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#include "exec/log.h"
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#include "exec/helper-proto.h"
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#if defined(CONFIG_USER_ONLY)
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void nios2_cpu_do_interrupt(CPUState *cs)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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cs->exception_index = -1;
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env->regs[R_EA] = env->regs[R_PC] + 4;
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}
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int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx)
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{
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cs->exception_index = 0xaa;
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/* Page 0x1000 is kuser helper */
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if (address < 0x1000 || address >= 0x2000) {
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cpu_dump_state(cs, stderr, fprintf, 0);
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}
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return 1;
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}
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#else /* !CONFIG_USER_ONLY */
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void nios2_cpu_do_interrupt(CPUState *cs)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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switch (cs->exception_index) {
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case EXCP_IRQ:
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assert(env->regs[CR_STATUS] & CR_STATUS_PIE);
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qemu_log_mask(CPU_LOG_INT, "interrupt at pc=%x\n", env->regs[R_PC]);
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env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
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env->regs[CR_STATUS] |= CR_STATUS_IH;
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env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
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env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
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env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
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env->regs[R_EA] = env->regs[R_PC] + 4;
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env->regs[R_PC] = cpu->exception_addr;
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break;
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case EXCP_TLBD:
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if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
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qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=%x\n",
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env->regs[R_PC]);
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/* Fast TLB miss */
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/* Variation from the spec. Table 3-35 of the cpu reference shows
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* estatus not being changed for TLB miss but this appears to
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* be incorrect. */
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env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
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env->regs[CR_STATUS] |= CR_STATUS_EH;
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env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
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env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
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env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
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env->regs[CR_TLBMISC] &= ~CR_TLBMISC_DBL;
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env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
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env->regs[R_EA] = env->regs[R_PC] + 4;
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env->regs[R_PC] = cpu->fast_tlb_miss_addr;
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} else {
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qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=%x\n",
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env->regs[R_PC]);
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/* Double TLB miss */
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env->regs[CR_STATUS] |= CR_STATUS_EH;
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env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
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env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
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env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
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env->regs[CR_TLBMISC] |= CR_TLBMISC_DBL;
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env->regs[R_PC] = cpu->exception_addr;
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}
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break;
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case EXCP_TLBR:
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case EXCP_TLBW:
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case EXCP_TLBX:
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qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=%x\n", env->regs[R_PC]);
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env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
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env->regs[CR_STATUS] |= CR_STATUS_EH;
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env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
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env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
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env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
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if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
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env->regs[CR_TLBMISC] |= CR_TLBMISC_WR;
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}
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env->regs[R_EA] = env->regs[R_PC] + 4;
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env->regs[R_PC] = cpu->exception_addr;
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break;
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case EXCP_SUPERA:
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case EXCP_SUPERI:
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case EXCP_SUPERD:
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qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=%x\n",
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env->regs[R_PC]);
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if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
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env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
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env->regs[R_EA] = env->regs[R_PC] + 4;
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}
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env->regs[CR_STATUS] |= CR_STATUS_EH;
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env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
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env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
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env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
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env->regs[R_PC] = cpu->exception_addr;
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break;
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case EXCP_ILLEGAL:
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case EXCP_TRAP:
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qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=%x\n",
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env->regs[R_PC]);
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if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
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env->regs[CR_ESTATUS] = env->regs[CR_STATUS];
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env->regs[R_EA] = env->regs[R_PC] + 4;
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}
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env->regs[CR_STATUS] |= CR_STATUS_EH;
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env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
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env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
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env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
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env->regs[R_PC] = cpu->exception_addr;
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break;
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case EXCP_BREAK:
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if ((env->regs[CR_STATUS] & CR_STATUS_EH) == 0) {
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env->regs[CR_BSTATUS] = env->regs[CR_STATUS];
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env->regs[R_BA] = env->regs[R_PC] + 4;
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}
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env->regs[CR_STATUS] |= CR_STATUS_EH;
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env->regs[CR_STATUS] &= ~(CR_STATUS_PIE | CR_STATUS_U);
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env->regs[CR_EXCEPTION] &= ~(0x1F << 2);
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env->regs[CR_EXCEPTION] |= (cs->exception_index & 0x1F) << 2;
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env->regs[R_PC] = cpu->exception_addr;
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break;
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default:
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cpu_abort(cs, "unhandled exception type=%d\n",
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cs->exception_index);
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break;
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}
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}
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static int cpu_nios2_handle_virtual_page(
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CPUState *cs, target_ulong address, int rw, int mmu_idx)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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target_ulong vaddr, paddr;
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Nios2MMULookup lu;
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unsigned int hit;
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hit = mmu_translate(env, &lu, address, rw, mmu_idx);
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if (hit) {
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vaddr = address & TARGET_PAGE_MASK;
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paddr = lu.paddr + vaddr - lu.vaddr;
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if (((rw == 0) && (lu.prot & PAGE_READ)) ||
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((rw == 1) && (lu.prot & PAGE_WRITE)) ||
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((rw == 2) && (lu.prot & PAGE_EXEC))) {
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tlb_set_page(cs, vaddr, paddr, lu.prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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} else {
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/* Permission violation */
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cs->exception_index = (rw == 0) ? EXCP_TLBR :
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((rw == 1) ? EXCP_TLBW :
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EXCP_TLBX);
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}
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} else {
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cs->exception_index = EXCP_TLBD;
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}
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if (rw == 2) {
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env->regs[CR_TLBMISC] &= ~CR_TLBMISC_D;
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} else {
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env->regs[CR_TLBMISC] |= CR_TLBMISC_D;
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}
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env->regs[CR_PTEADDR] &= CR_PTEADDR_PTBASE_MASK;
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env->regs[CR_PTEADDR] |= (address >> 10) & CR_PTEADDR_VPN_MASK;
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env->mmu.pteaddr_wr = env->regs[CR_PTEADDR];
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env->regs[CR_BADADDR] = address;
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return 1;
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}
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int nios2_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, int mmu_idx)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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if (cpu->mmu_present) {
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if (MMU_SUPERVISOR_IDX == mmu_idx) {
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if (address >= 0xC0000000) {
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/* Kernel physical page - TLB bypassed */
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address &= TARGET_PAGE_MASK;
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tlb_set_page(cs, address, address, PAGE_BITS,
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mmu_idx, TARGET_PAGE_SIZE);
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} else if (address >= 0x80000000) {
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/* Kernel virtual page */
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return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_idx);
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} else {
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/* User virtual page */
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return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_idx);
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}
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} else {
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if (address >= 0x80000000) {
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/* Illegal access from user mode */
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cs->exception_index = EXCP_SUPERA;
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env->regs[CR_BADADDR] = address;
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return 1;
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} else {
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/* User virtual page */
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return cpu_nios2_handle_virtual_page(cs, address, rw, mmu_idx);
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}
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}
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} else {
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/* No MMU */
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address &= TARGET_PAGE_MASK;
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tlb_set_page(cs, address, address, PAGE_BITS,
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mmu_idx, TARGET_PAGE_SIZE);
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}
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return 0;
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}
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hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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target_ulong vaddr, paddr = 0;
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Nios2MMULookup lu;
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unsigned int hit;
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if (cpu->mmu_present && (addr < 0xC0000000)) {
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hit = mmu_translate(env, &lu, addr, 0, 0);
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if (hit) {
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vaddr = addr & TARGET_PAGE_MASK;
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paddr = lu.paddr + vaddr - lu.vaddr;
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} else {
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paddr = -1;
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qemu_log("cpu_get_phys_page debug MISS: %#" PRIx64 "\n", addr);
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}
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} else {
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paddr = addr & TARGET_PAGE_MASK;
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}
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return paddr;
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}
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void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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env->regs[CR_BADADDR] = addr;
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env->regs[CR_EXCEPTION] = EXCP_UNALIGN << 2;
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helper_raise_exception(env, EXCP_UNALIGN);
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}
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#endif /* !CONFIG_USER_ONLY */
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