2014-09-01 13:59:51 +02:00
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/*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2019-01-23 15:08:55 +01:00
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* version 2.1 of the License, or (at your option) any later version.
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2014-09-01 13:59:51 +02:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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2014-09-01 13:59:52 +02:00
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/* Arithmetic */
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DEF_HELPER_3(add_ssov, i32, env, i32, i32)
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2015-01-29 16:35:56 +01:00
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DEF_HELPER_3(add64_ssov, i64, env, i64, i64)
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target-tricore: Add instructions of RC opcode format
Add instructions of RC opcode format.
Add helper for mul, sha, absdif with signed saturation on overflow.
Add helper for add, sub, mul with unsigned saturation on overflow.
Add microcode generator functions:
* gen_add_CC, which calculates the carry bit.
* gen_addc_CC, which adds the carry bit to the add and calculates the carry bit.
* gen_absdif, which calculates the absolute difference.
* gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
* gen_sh_hi, which shifts two 16bit words in one reg.
* gen_sha_hi, which does a arithmetic shift on two 16bit words.
* gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb.
* gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
with the lsb of the result.
* gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-26 22:49:41 +01:00
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DEF_HELPER_3(add_suov, i32, env, i32, i32)
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2014-11-27 15:30:33 +01:00
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DEF_HELPER_3(add_h_ssov, i32, env, i32, i32)
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DEF_HELPER_3(add_h_suov, i32, env, i32, i32)
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2015-01-29 16:35:56 +01:00
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DEF_HELPER_4(addr_h_ssov, i32, env, i64, i32, i32)
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2015-02-06 15:48:33 +01:00
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DEF_HELPER_4(addsur_h_ssov, i32, env, i64, i32, i32)
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2014-09-01 13:59:52 +02:00
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DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
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2015-02-25 12:34:55 +01:00
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DEF_HELPER_3(sub64_ssov, i64, env, i64, i64)
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target-tricore: Add instructions of RC opcode format
Add instructions of RC opcode format.
Add helper for mul, sha, absdif with signed saturation on overflow.
Add helper for add, sub, mul with unsigned saturation on overflow.
Add microcode generator functions:
* gen_add_CC, which calculates the carry bit.
* gen_addc_CC, which adds the carry bit to the add and calculates the carry bit.
* gen_absdif, which calculates the absolute difference.
* gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
* gen_sh_hi, which shifts two 16bit words in one reg.
* gen_sha_hi, which does a arithmetic shift on two 16bit words.
* gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb.
* gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
with the lsb of the result.
* gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-26 22:49:41 +01:00
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DEF_HELPER_3(sub_suov, i32, env, i32, i32)
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2014-11-27 15:30:33 +01:00
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DEF_HELPER_3(sub_h_ssov, i32, env, i32, i32)
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DEF_HELPER_3(sub_h_suov, i32, env, i32, i32)
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2015-02-25 12:34:55 +01:00
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DEF_HELPER_4(subr_h_ssov, i32, env, i64, i32, i32)
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2015-02-25 12:55:52 +01:00
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DEF_HELPER_4(subadr_h_ssov, i32, env, i64, i32, i32)
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target-tricore: Add instructions of RC opcode format
Add instructions of RC opcode format.
Add helper for mul, sha, absdif with signed saturation on overflow.
Add helper for add, sub, mul with unsigned saturation on overflow.
Add microcode generator functions:
* gen_add_CC, which calculates the carry bit.
* gen_addc_CC, which adds the carry bit to the add and calculates the carry bit.
* gen_absdif, which calculates the absolute difference.
* gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
* gen_sh_hi, which shifts two 16bit words in one reg.
* gen_sha_hi, which does a arithmetic shift on two 16bit words.
* gen_sh_cond, which shifts left a reg by one and writes the result of cond into the lsb.
* gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
with the lsb of the result.
* gen_eqany_bi/hi, which checks ever byte/hword on equality.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-10-26 22:49:41 +01:00
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DEF_HELPER_3(mul_ssov, i32, env, i32, i32)
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DEF_HELPER_3(mul_suov, i32, env, i32, i32)
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DEF_HELPER_3(sha_ssov, i32, env, i32, i32)
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DEF_HELPER_3(absdif_ssov, i32, env, i32, i32)
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2014-11-02 18:31:45 +01:00
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DEF_HELPER_4(madd32_ssov, i32, env, i32, i32, i32)
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DEF_HELPER_4(madd32_suov, i32, env, i32, i32, i32)
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DEF_HELPER_4(madd64_ssov, i64, env, i32, i64, i32)
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2015-02-03 19:36:53 +01:00
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DEF_HELPER_5(madd64_q_ssov, i64, env, i64, i32, i32, i32)
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DEF_HELPER_3(madd32_q_add_ssov, i32, env, i64, i64)
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DEF_HELPER_5(maddr_q_ssov, i32, env, i32, i32, i32, i32)
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2014-11-02 18:31:45 +01:00
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DEF_HELPER_4(madd64_suov, i64, env, i32, i64, i32)
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DEF_HELPER_4(msub32_ssov, i32, env, i32, i32, i32)
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DEF_HELPER_4(msub32_suov, i32, env, i32, i32, i32)
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DEF_HELPER_4(msub64_ssov, i64, env, i32, i64, i32)
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2015-02-25 12:46:55 +01:00
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DEF_HELPER_5(msub64_q_ssov, i64, env, i64, i32, i32, i32)
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DEF_HELPER_3(msub32_q_sub_ssov, i32, env, i64, i64)
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DEF_HELPER_5(msubr_q_ssov, i32, env, i32, i32, i32, i32)
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2014-11-02 18:31:45 +01:00
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DEF_HELPER_4(msub64_suov, i64, env, i32, i64, i32)
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2014-11-27 15:30:33 +01:00
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DEF_HELPER_3(absdif_h_ssov, i32, env, i32, i32)
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DEF_HELPER_2(abs_ssov, i32, env, i32)
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DEF_HELPER_2(abs_h_ssov, i32, env, i32)
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/* hword/byte arithmetic */
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DEF_HELPER_2(abs_b, i32, env, i32)
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DEF_HELPER_2(abs_h, i32, env, i32)
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DEF_HELPER_3(absdif_b, i32, env, i32, i32)
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DEF_HELPER_3(absdif_h, i32, env, i32, i32)
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2015-01-29 16:35:56 +01:00
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DEF_HELPER_4(addr_h, i32, env, i64, i32, i32)
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2015-02-06 15:48:33 +01:00
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DEF_HELPER_4(addsur_h, i32, env, i64, i32, i32)
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2015-02-03 19:36:53 +01:00
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DEF_HELPER_5(maddr_q, i32, env, i32, i32, i32, i32)
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2014-11-27 15:30:33 +01:00
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DEF_HELPER_3(add_b, i32, env, i32, i32)
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DEF_HELPER_3(add_h, i32, env, i32, i32)
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DEF_HELPER_3(sub_b, i32, env, i32, i32)
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DEF_HELPER_3(sub_h, i32, env, i32, i32)
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2015-02-25 12:34:55 +01:00
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DEF_HELPER_4(subr_h, i32, env, i64, i32, i32)
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2015-02-25 12:55:52 +01:00
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DEF_HELPER_4(subadr_h, i32, env, i64, i32, i32)
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2015-02-25 12:46:55 +01:00
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DEF_HELPER_5(msubr_q, i32, env, i32, i32, i32, i32)
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2014-11-27 15:30:33 +01:00
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DEF_HELPER_FLAGS_2(eq_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(eq_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(eqany_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(eqany_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(lt_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(lt_bu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(lt_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(lt_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(max_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(max_bu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(max_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(max_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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2015-01-19 16:43:07 +01:00
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DEF_HELPER_FLAGS_2(ixmax, TCG_CALL_NO_RWG_SE, i64, i64, i32)
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DEF_HELPER_FLAGS_2(ixmax_u, TCG_CALL_NO_RWG_SE, i64, i64, i32)
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2014-11-27 15:30:33 +01:00
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DEF_HELPER_FLAGS_2(min_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(min_bu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(min_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(min_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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2015-01-19 16:43:07 +01:00
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DEF_HELPER_FLAGS_2(ixmin, TCG_CALL_NO_RWG_SE, i64, i64, i32)
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DEF_HELPER_FLAGS_2(ixmin_u, TCG_CALL_NO_RWG_SE, i64, i64, i32)
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2014-11-28 18:07:26 +01:00
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/* count leading ... */
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DEF_HELPER_FLAGS_1(clo_h, TCG_CALL_NO_RWG_SE, i32, i32)
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DEF_HELPER_FLAGS_1(clz_h, TCG_CALL_NO_RWG_SE, i32, i32)
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DEF_HELPER_FLAGS_1(cls_h, TCG_CALL_NO_RWG_SE, i32, i32)
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/* sh */
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DEF_HELPER_FLAGS_2(sh, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(sh_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_3(sha, i32, env, i32, i32)
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DEF_HELPER_2(sha_h, i32, i32, i32)
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2014-12-02 18:22:27 +01:00
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/* merge/split/parity */
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DEF_HELPER_FLAGS_2(bmerge, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_1(bsplit, TCG_CALL_NO_RWG_SE, i64, i32)
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DEF_HELPER_FLAGS_1(parity, TCG_CALL_NO_RWG_SE, i32, i32)
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/* float */
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2015-01-19 16:43:07 +01:00
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DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32)
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2014-12-02 18:22:27 +01:00
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DEF_HELPER_1(unpack, i64, i32)
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2016-03-11 16:03:13 +01:00
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DEF_HELPER_3(fadd, i32, env, i32, i32)
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DEF_HELPER_3(fsub, i32, env, i32, i32)
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2016-03-11 16:03:14 +01:00
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DEF_HELPER_3(fmul, i32, env, i32, i32)
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2016-03-11 16:03:15 +01:00
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DEF_HELPER_3(fdiv, i32, env, i32, i32)
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2016-10-06 16:50:53 +02:00
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DEF_HELPER_4(fmadd, i32, env, i32, i32, i32)
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DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
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2016-03-11 16:03:16 +01:00
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DEF_HELPER_3(fcmp, i32, env, i32, i32)
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2019-06-24 09:03:39 +02:00
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DEF_HELPER_2(qseed, i32, env, i32)
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2016-03-11 16:03:17 +01:00
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DEF_HELPER_2(ftoi, i32, env, i32)
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DEF_HELPER_2(itof, i32, env, i32)
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2019-06-24 09:03:36 +02:00
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DEF_HELPER_2(utof, i32, env, i32)
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2019-06-24 09:03:35 +02:00
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DEF_HELPER_2(ftoiz, i32, env, i32)
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2016-10-06 16:46:36 +02:00
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DEF_HELPER_2(ftouz, i32, env, i32)
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2016-10-06 17:52:04 +02:00
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DEF_HELPER_2(updfl, void, env, i32)
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2014-12-02 18:22:27 +01:00
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/* dvinit */
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DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
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DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
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DEF_HELPER_3(dvinit_h_13, i64, env, i32, i32)
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DEF_HELPER_3(dvinit_h_131, i64, env, i32, i32)
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2015-01-19 16:43:07 +01:00
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DEF_HELPER_FLAGS_2(dvadj, TCG_CALL_NO_RWG_SE, i64, i64, i32)
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DEF_HELPER_FLAGS_2(dvstep, TCG_CALL_NO_RWG_SE, i64, i64, i32)
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DEF_HELPER_FLAGS_2(dvstep_u, TCG_CALL_NO_RWG_SE, i64, i64, i32)
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2015-05-11 14:59:55 +02:00
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DEF_HELPER_3(divide, i64, env, i32, i32)
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DEF_HELPER_3(divide_u, i64, env, i32, i32)
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2014-12-12 17:55:34 +01:00
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/* mulh */
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DEF_HELPER_FLAGS_5(mul_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32)
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DEF_HELPER_FLAGS_5(mulm_h, TCG_CALL_NO_RWG_SE, i64, i32, i32, i32, i32, i32)
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DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32, i32)
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2015-05-07 19:55:37 +02:00
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/* crc32 */
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DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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2014-09-01 13:59:55 +02:00
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/* CSA */
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DEF_HELPER_2(call, void, env, i32)
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DEF_HELPER_1(ret, void, env)
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2014-09-01 13:59:58 +02:00
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DEF_HELPER_2(bisr, void, env, i32)
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2014-09-01 14:00:00 +02:00
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DEF_HELPER_1(rfe, void, env)
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2015-02-25 13:29:24 +01:00
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DEF_HELPER_1(rfm, void, env)
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2014-09-26 21:26:31 +02:00
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DEF_HELPER_2(ldlcx, void, env, i32)
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DEF_HELPER_2(lducx, void, env, i32)
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DEF_HELPER_2(stlcx, void, env, i32)
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DEF_HELPER_2(stucx, void, env, i32)
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2015-02-25 13:29:24 +01:00
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DEF_HELPER_1(svlcx, void, env)
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2016-02-19 14:43:43 +01:00
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DEF_HELPER_1(svucx, void, env)
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2015-02-25 13:29:24 +01:00
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DEF_HELPER_1(rslcx, void, env)
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2014-09-26 21:36:09 +02:00
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/* Address mode helper */
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DEF_HELPER_1(br_update, i32, i32)
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DEF_HELPER_2(circ_update, i32, i32, i32)
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2014-10-30 13:06:53 +01:00
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/* PSW cache helper */
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DEF_HELPER_2(psw_write, void, env, i32)
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DEF_HELPER_1(psw_read, i32, env)
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2016-02-19 14:43:43 +01:00
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/* Exceptions */
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DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32)
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