2017-07-13 22:15:21 +02:00
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/*
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2018-09-21 10:20:37 +02:00
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* Definitions for Hyper-V guest/hypervisor interaction - x86-specific part
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2017-07-13 22:15:21 +02:00
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*
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2018-09-21 10:20:37 +02:00
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* Copyright (c) 2017-2018 Virtuozzo International GmbH.
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2017-07-13 22:15:21 +02:00
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef TARGET_I386_HYPERV_PROTO_H
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#define TARGET_I386_HYPERV_PROTO_H
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2018-09-21 10:20:37 +02:00
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#include "hw/hyperv/hyperv-proto.h"
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2017-07-13 22:15:21 +02:00
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#define HV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
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#define HV_CPUID_INTERFACE 0x40000001
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#define HV_CPUID_VERSION 0x40000002
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#define HV_CPUID_FEATURES 0x40000003
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#define HV_CPUID_ENLIGHTMENT_INFO 0x40000004
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#define HV_CPUID_IMPLEMENT_LIMITS 0x40000005
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2018-10-22 18:55:06 +02:00
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#define HV_CPUID_NESTED_FEATURES 0x4000000A
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2022-02-16 11:24:58 +01:00
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#define HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS 0x40000080
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#define HV_CPUID_SYNDBG_INTERFACE 0x40000081
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#define HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES 0x40000082
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2017-07-13 22:15:21 +02:00
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#define HV_CPUID_MIN 0x40000005
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#define HV_CPUID_MAX 0x4000ffff
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#define HV_HYPERVISOR_PRESENT_BIT 0x80000000
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/*
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* HV_CPUID_FEATURES.EAX bits
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*/
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#define HV_VP_RUNTIME_AVAILABLE (1u << 0)
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#define HV_TIME_REF_COUNT_AVAILABLE (1u << 1)
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#define HV_SYNIC_AVAILABLE (1u << 2)
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#define HV_SYNTIMERS_AVAILABLE (1u << 3)
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#define HV_APIC_ACCESS_AVAILABLE (1u << 4)
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#define HV_HYPERCALL_AVAILABLE (1u << 5)
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#define HV_VP_INDEX_AVAILABLE (1u << 6)
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#define HV_RESET_AVAILABLE (1u << 7)
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#define HV_REFERENCE_TSC_AVAILABLE (1u << 9)
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#define HV_ACCESS_FREQUENCY_MSRS (1u << 11)
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2018-04-11 13:50:36 +02:00
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#define HV_ACCESS_REENLIGHTENMENTS_CONTROL (1u << 13)
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2017-07-13 22:15:21 +02:00
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2021-06-08 14:08:16 +02:00
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/*
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* HV_CPUID_FEATURES.EBX bits
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*/
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#define HV_POST_MESSAGES (1u << 4)
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#define HV_SIGNAL_EVENTS (1u << 5)
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2017-07-13 22:15:21 +02:00
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/*
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* HV_CPUID_FEATURES.EDX bits
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*/
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#define HV_MWAIT_AVAILABLE (1u << 0)
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#define HV_GUEST_DEBUGGING_AVAILABLE (1u << 1)
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#define HV_PERF_MONITOR_AVAILABLE (1u << 2)
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#define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1u << 3)
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2022-05-25 13:59:46 +02:00
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#define HV_HYPERCALL_XMM_INPUT_AVAILABLE (1u << 4)
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2017-07-13 22:15:21 +02:00
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#define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5)
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#define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8)
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#define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10)
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2022-02-16 11:24:58 +01:00
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#define HV_FEATURE_DEBUG_MSRS_AVAILABLE (1u << 11)
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2022-05-25 13:59:47 +02:00
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#define HV_EXT_GVA_RANGES_FLUSH_AVAILABLE (1u << 14)
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2019-05-17 16:19:24 +02:00
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#define HV_STIMER_DIRECT_MODE_AVAILABLE (1u << 19)
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2017-07-13 22:15:21 +02:00
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2022-02-16 11:24:58 +01:00
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/*
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* HV_CPUID_FEATURES.EBX bits
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*/
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#define HV_PARTITION_DEBUGGING_ALLOWED (1u << 12)
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2017-07-13 22:15:21 +02:00
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/*
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* HV_CPUID_ENLIGHTMENT_INFO.EAX bits
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*/
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#define HV_AS_SWITCH_RECOMMENDED (1u << 0)
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#define HV_LOCAL_TLB_FLUSH_RECOMMENDED (1u << 1)
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#define HV_REMOTE_TLB_FLUSH_RECOMMENDED (1u << 2)
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#define HV_APIC_ACCESS_RECOMMENDED (1u << 3)
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#define HV_SYSTEM_RESET_RECOMMENDED (1u << 4)
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#define HV_RELAXED_TIMING_RECOMMENDED (1u << 5)
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2021-09-02 11:35:28 +02:00
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#define HV_DEPRECATING_AEOI_RECOMMENDED (1u << 9)
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2018-10-09 15:08:53 +02:00
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#define HV_CLUSTER_IPI_RECOMMENDED (1u << 10)
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2018-06-10 20:49:27 +02:00
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#define HV_EX_PROCESSOR_MASKS_RECOMMENDED (1u << 11)
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2018-10-22 18:55:06 +02:00
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#define HV_ENLIGHTENED_VMCS_RECOMMENDED (1u << 14)
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2019-10-18 18:39:08 +02:00
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#define HV_NO_NONARCH_CORESHARING (1u << 18)
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2017-07-13 22:15:21 +02:00
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2022-02-16 11:24:58 +01:00
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/*
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* HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX bits
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*/
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#define HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING (1u << 1)
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2022-05-25 13:59:45 +02:00
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/*
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* HV_CPUID_NESTED_FEATURES.EAX bits
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*/
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2022-05-25 13:59:48 +02:00
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#define HV_NESTED_DIRECT_FLUSH (1u << 17)
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2022-05-25 13:59:45 +02:00
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#define HV_NESTED_MSR_BITMAP (1u << 19)
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2017-07-13 22:15:21 +02:00
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/*
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* Basic virtualized MSRs
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*/
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#define HV_X64_MSR_GUEST_OS_ID 0x40000000
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#define HV_X64_MSR_HYPERCALL 0x40000001
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#define HV_X64_MSR_VP_INDEX 0x40000002
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#define HV_X64_MSR_RESET 0x40000003
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#define HV_X64_MSR_VP_RUNTIME 0x40000010
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#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
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#define HV_X64_MSR_REFERENCE_TSC 0x40000021
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#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
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#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
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/*
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* Virtual APIC MSRs
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*/
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#define HV_X64_MSR_EOI 0x40000070
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#define HV_X64_MSR_ICR 0x40000071
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#define HV_X64_MSR_TPR 0x40000072
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#define HV_X64_MSR_APIC_ASSIST_PAGE 0x40000073
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/*
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* Synthetic interrupt controller MSRs
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*/
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#define HV_X64_MSR_SCONTROL 0x40000080
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#define HV_X64_MSR_SVERSION 0x40000081
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#define HV_X64_MSR_SIEFP 0x40000082
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#define HV_X64_MSR_SIMP 0x40000083
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#define HV_X64_MSR_EOM 0x40000084
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#define HV_X64_MSR_SINT0 0x40000090
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#define HV_X64_MSR_SINT1 0x40000091
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#define HV_X64_MSR_SINT2 0x40000092
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#define HV_X64_MSR_SINT3 0x40000093
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#define HV_X64_MSR_SINT4 0x40000094
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#define HV_X64_MSR_SINT5 0x40000095
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#define HV_X64_MSR_SINT6 0x40000096
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#define HV_X64_MSR_SINT7 0x40000097
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#define HV_X64_MSR_SINT8 0x40000098
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#define HV_X64_MSR_SINT9 0x40000099
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#define HV_X64_MSR_SINT10 0x4000009A
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#define HV_X64_MSR_SINT11 0x4000009B
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#define HV_X64_MSR_SINT12 0x4000009C
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#define HV_X64_MSR_SINT13 0x4000009D
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#define HV_X64_MSR_SINT14 0x4000009E
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#define HV_X64_MSR_SINT15 0x4000009F
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/*
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* Synthetic timer MSRs
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*/
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#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
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#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
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#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
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#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
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#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
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#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
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#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
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#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
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2022-02-16 11:24:58 +01:00
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/*
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* Hyper-V Synthetic debug options MSR
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*/
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#define HV_X64_MSR_SYNDBG_CONTROL 0x400000F1
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#define HV_X64_MSR_SYNDBG_STATUS 0x400000F2
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#define HV_X64_MSR_SYNDBG_SEND_BUFFER 0x400000F3
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#define HV_X64_MSR_SYNDBG_RECV_BUFFER 0x400000F4
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#define HV_X64_MSR_SYNDBG_PENDING_BUFFER 0x400000F5
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#define HV_X64_MSR_SYNDBG_OPTIONS 0x400000FF
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#define HV_X64_SYNDBG_OPTION_USE_HCALLS BIT(2)
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2017-07-13 22:15:21 +02:00
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/*
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* Guest crash notification MSRs
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*/
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#define HV_X64_MSR_CRASH_P0 0x40000100
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#define HV_X64_MSR_CRASH_P1 0x40000101
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#define HV_X64_MSR_CRASH_P2 0x40000102
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#define HV_X64_MSR_CRASH_P3 0x40000103
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#define HV_X64_MSR_CRASH_P4 0x40000104
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#define HV_CRASH_PARAMS (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0 + 1)
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#define HV_X64_MSR_CRASH_CTL 0x40000105
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#define HV_CRASH_CTL_NOTIFY (1ull << 63)
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2018-04-11 13:50:36 +02:00
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/*
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* Reenlightenment notification MSRs
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*/
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#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
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2021-03-19 13:38:01 +01:00
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#define HV_REENLIGHTENMENT_ENABLE_BIT (1u << 16)
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2018-04-11 13:50:36 +02:00
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#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
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#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
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2017-07-13 22:15:21 +02:00
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/*
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* Hypercall MSR bits
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*/
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#define HV_HYPERCALL_ENABLE (1u << 0)
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/*
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* Synthetic interrupt controller definitions
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*/
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#define HV_SYNIC_VERSION 1
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#define HV_SYNIC_ENABLE (1u << 0)
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#define HV_SIMP_ENABLE (1u << 0)
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#define HV_SIEFP_ENABLE (1u << 0)
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#define HV_SINT_MASKED (1u << 16)
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#define HV_SINT_AUTO_EOI (1u << 17)
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#define HV_SINT_VECTOR_MASK 0xff
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#define HV_STIMER_COUNT 4
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2022-02-16 11:24:58 +01:00
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/*
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* Synthetic debugger control definitions
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*/
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#define HV_SYNDBG_CONTROL_SEND (1u << 0)
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#define HV_SYNDBG_CONTROL_RECV (1u << 1)
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#define HV_SYNDBG_CONTROL_SEND_SIZE(ctl) ((ctl >> 16) & 0xffff)
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#define HV_SYNDBG_STATUS_INVALID (0)
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#define HV_SYNDBG_STATUS_SEND_SUCCESS (1u << 0)
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#define HV_SYNDBG_STATUS_RECV_SUCCESS (1u << 2)
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#define HV_SYNDBG_STATUS_RESET (1u << 3)
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#define HV_SYNDBG_STATUS_SET_SIZE(st, sz) (st | (sz << 16))
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2017-07-13 22:15:21 +02:00
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#endif
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