2018-07-30 16:11:32 +02:00
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/*
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* QEMU PowerPC sPAPR IRQ interface
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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2019-08-12 07:23:42 +02:00
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#include "hw/irq.h"
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2018-07-30 16:11:32 +02:00
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#include "hw/ppc/spapr.h"
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2019-01-17 08:53:26 +01:00
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#include "hw/ppc/spapr_cpu_core.h"
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2018-12-11 23:38:12 +01:00
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#include "hw/ppc/spapr_xive.h"
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2018-07-30 16:11:32 +02:00
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#include "hw/ppc/xics.h"
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2019-01-10 09:18:47 +01:00
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#include "hw/ppc/xics_spapr.h"
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2019-08-12 07:23:51 +02:00
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#include "hw/qdev-properties.h"
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2019-03-28 11:00:44 +01:00
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#include "cpu-models.h"
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2018-07-30 16:11:33 +02:00
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#include "sysemu/kvm.h"
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#include "trace.h"
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2018-07-30 16:11:32 +02:00
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2019-09-24 08:25:08 +02:00
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static const TypeInfo spapr_intc_info = {
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.name = TYPE_SPAPR_INTC,
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.parent = TYPE_INTERFACE,
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.class_size = sizeof(SpaprInterruptControllerClass),
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};
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2019-09-27 05:44:58 +02:00
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static void spapr_irq_msi_init(SpaprMachineState *spapr)
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2018-07-30 16:11:32 +02:00
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{
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2019-09-27 05:44:58 +02:00
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if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
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/* Legacy mode doesn't use this allocator */
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return;
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}
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spapr->irq_map_nr = spapr_irq_nr_msis(spapr);
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2018-07-30 16:11:32 +02:00
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spapr->irq_map = bitmap_new(spapr->irq_map_nr);
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}
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
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2018-07-30 16:11:32 +02:00
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Error **errp)
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{
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int irq;
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/*
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* The 'align_mask' parameter of bitmap_find_next_zero_area()
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* should be one less than a power of 2; 0 means no
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* alignment. Adapt the 'align' value of the former allocator
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* to fit the requirements of bitmap_find_next_zero_area()
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*/
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align -= 1;
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irq = bitmap_find_next_zero_area(spapr->irq_map, spapr->irq_map_nr, 0, num,
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align);
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if (irq == spapr->irq_map_nr) {
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error_setg(errp, "can't find a free %d-IRQ block", num);
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return -1;
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}
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bitmap_set(spapr->irq_map, irq, num);
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return irq + SPAPR_IRQ_MSI;
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}
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num)
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2018-07-30 16:11:32 +02:00
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{
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bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num);
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}
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2019-11-26 17:46:23 +01:00
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int spapr_irq_init_kvm(SpaprInterruptControllerInitKvm fn,
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2019-09-26 15:58:36 +02:00
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SpaprInterruptController *intc,
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2019-11-26 17:46:23 +01:00
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uint32_t nr_servers,
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2019-09-26 15:58:36 +02:00
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Error **errp)
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2018-07-30 16:11:33 +02:00
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{
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Error *local_err = NULL;
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2019-11-13 11:17:12 +01:00
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if (kvm_enabled() && kvm_kernel_irqchip_allowed()) {
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2019-11-26 17:46:23 +01:00
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if (fn(intc, nr_servers, &local_err) < 0) {
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2019-11-13 11:17:12 +01:00
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if (kvm_kernel_irqchip_required()) {
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2019-09-26 15:02:41 +02:00
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error_prepend(&local_err,
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"kernel_irqchip requested but unavailable: ");
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error_propagate(errp, local_err);
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return -1;
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}
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2019-05-13 10:42:42 +02:00
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2019-09-26 15:02:41 +02:00
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/*
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* We failed to initialize the KVM device, fallback to
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* emulated mode
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*/
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error_prepend(&local_err,
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"kernel_irqchip allowed but unavailable: ");
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error_append_hint(&local_err,
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"Falling back to kernel-irqchip=off\n");
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warn_report_err(local_err);
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2019-05-13 10:42:42 +02:00
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}
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2018-07-30 16:11:33 +02:00
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}
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2019-09-26 15:02:41 +02:00
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return 0;
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2019-05-13 10:42:42 +02:00
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}
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/*
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* XICS IRQ backend.
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*/
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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SpaprIrq spapr_irq_xics = {
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2019-09-25 07:12:07 +02:00
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.xics = true,
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.xive = false,
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2018-07-30 16:11:33 +02:00
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};
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2018-12-11 23:38:12 +01:00
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/*
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* XIVE IRQ backend.
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*/
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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SpaprIrq spapr_irq_xive = {
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2019-09-25 07:12:07 +02:00
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.xics = false,
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.xive = true,
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2018-12-11 23:38:12 +01:00
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};
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2019-01-02 06:57:42 +01:00
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/*
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* Dual XIVE and XICS IRQ backend.
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*
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* Both interrupt mode, XIVE and XICS, objects are created but the
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* machine starts in legacy interrupt mode (XICS). It can be changed
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* by the CAS negotiation process and, in that case, the new mode is
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* activated after an extra machine reset.
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*/
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/*
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* Define values in sync with the XIVE and XICS backend
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*/
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spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
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SpaprIrq spapr_irq_dual = {
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2019-09-25 07:12:07 +02:00
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.xics = true,
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.xive = true,
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2019-01-02 06:57:42 +01:00
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};
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2019-03-28 11:00:44 +01:00
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2019-09-30 04:20:47 +02:00
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static int spapr_irq_check(SpaprMachineState *spapr, Error **errp)
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2019-03-28 11:00:44 +01:00
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{
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2020-08-05 17:47:16 +02:00
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ERRP_GUARD();
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2019-03-28 11:00:44 +01:00
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MachineState *machine = MACHINE(spapr);
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/*
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* Sanity checks on non-P9 machines. On these, XIVE is not
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* advertised, see spapr_dt_ov5_platform_support()
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*/
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if (!ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00,
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0, spapr->max_compat_pvr)) {
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/*
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* If the 'dual' interrupt mode is selected, force XICS as CAS
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* negotiation is useless.
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*/
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if (spapr->irq == &spapr_irq_dual) {
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spapr->irq = &spapr_irq_xics;
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2019-09-30 04:20:47 +02:00
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return 0;
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2019-03-28 11:00:44 +01:00
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}
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/*
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* Non-P9 machines using only XIVE is a bogus setup. We have two
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* scenarios to take into account because of the compat mode:
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*
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* 1. POWER7/8 machines should fail to init later on when creating
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* the XIVE interrupt presenters because a POWER9 exception
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* model is required.
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* 2. POWER9 machines using the POWER8 compat mode won't fail and
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* will let the OS boot with a partial XIVE setup : DT
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* properties but no hcalls.
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*
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* To cover both and not confuse the OS, add an early failure in
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* QEMU.
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*/
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2020-08-20 16:01:06 +02:00
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if (!spapr->irq->xics) {
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2019-03-28 11:00:44 +01:00
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error_setg(errp, "XIVE-only machines require a POWER9 CPU");
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2019-09-30 04:20:47 +02:00
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return -1;
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2019-03-28 11:00:44 +01:00
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}
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}
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2019-06-13 18:45:05 +02:00
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/*
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* On a POWER9 host, some older KVM XICS devices cannot be destroyed and
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2020-08-05 17:47:16 +02:00
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* re-created. Same happens with KVM nested guests. Detect that early to
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* avoid QEMU to exit later when the guest reboots.
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2019-06-13 18:45:05 +02:00
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*/
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if (kvm_enabled() &&
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spapr->irq == &spapr_irq_dual &&
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2019-11-13 11:17:12 +01:00
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kvm_kernel_irqchip_required() &&
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2019-06-13 18:45:05 +02:00
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xics_kvm_has_broken_disconnect(spapr)) {
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2020-08-05 17:47:16 +02:00
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error_setg(errp,
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"KVM is incompatible with ic-mode=dual,kernel-irqchip=on");
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error_append_hint(errp,
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"This can happen with an old KVM or in a KVM nested guest.\n");
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error_append_hint(errp,
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"Try without kernel-irqchip or with kernel-irqchip=off.\n");
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2019-09-30 04:20:47 +02:00
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return -1;
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2019-06-13 18:45:05 +02:00
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}
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2019-09-30 04:20:47 +02:00
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return 0;
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2019-03-28 11:00:44 +01:00
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}
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2018-07-30 16:11:33 +02:00
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/*
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* sPAPR IRQ frontend routines for devices
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*/
|
2019-09-26 06:11:23 +02:00
|
|
|
#define ALL_INTCS(spapr_) \
|
|
|
|
|
{ SPAPR_INTC((spapr_)->ics), SPAPR_INTC((spapr_)->xive), }
|
|
|
|
|
|
|
|
|
|
int spapr_irq_cpu_intc_create(SpaprMachineState *spapr,
|
|
|
|
|
PowerPCCPU *cpu, Error **errp)
|
|
|
|
|
{
|
|
|
|
|
SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
|
|
|
|
|
int i;
|
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(intcs); i++) {
|
|
|
|
|
SpaprInterruptController *intc = intcs[i];
|
|
|
|
|
if (intc) {
|
|
|
|
|
SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc);
|
|
|
|
|
rc = sicc->cpu_intc_create(intc, cpu, errp);
|
|
|
|
|
if (rc < 0) {
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-22 18:38:10 +02:00
|
|
|
void spapr_irq_cpu_intc_reset(SpaprMachineState *spapr, PowerPCCPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(intcs); i++) {
|
|
|
|
|
SpaprInterruptController *intc = intcs[i];
|
|
|
|
|
if (intc) {
|
|
|
|
|
SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc);
|
|
|
|
|
sicc->cpu_intc_reset(intc, cpu);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-10-24 16:27:22 +02:00
|
|
|
void spapr_irq_cpu_intc_destroy(SpaprMachineState *spapr, PowerPCCPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(intcs); i++) {
|
|
|
|
|
SpaprInterruptController *intc = intcs[i];
|
|
|
|
|
if (intc) {
|
|
|
|
|
SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc);
|
|
|
|
|
sicc->cpu_intc_destroy(intc, cpu);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-26 08:09:46 +02:00
|
|
|
static void spapr_set_irq(void *opaque, int irq, int level)
|
|
|
|
|
{
|
|
|
|
|
SpaprMachineState *spapr = SPAPR_MACHINE(opaque);
|
|
|
|
|
SpaprInterruptControllerClass *sicc
|
|
|
|
|
= SPAPR_INTC_GET_CLASS(spapr->active_intc);
|
|
|
|
|
|
|
|
|
|
sicc->set_irq(spapr->active_intc, irq, level);
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-26 08:12:05 +02:00
|
|
|
void spapr_irq_print_info(SpaprMachineState *spapr, Monitor *mon)
|
|
|
|
|
{
|
|
|
|
|
SpaprInterruptControllerClass *sicc
|
|
|
|
|
= SPAPR_INTC_GET_CLASS(spapr->active_intc);
|
|
|
|
|
|
|
|
|
|
sicc->print_info(spapr->active_intc, mon);
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-30 04:35:06 +02:00
|
|
|
void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
|
|
|
|
|
void *fdt, uint32_t phandle)
|
|
|
|
|
{
|
|
|
|
|
SpaprInterruptControllerClass *sicc
|
|
|
|
|
= SPAPR_INTC_GET_CLASS(spapr->active_intc);
|
|
|
|
|
|
|
|
|
|
sicc->dt(spapr->active_intc, nr_servers, fdt, phandle);
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-27 05:44:58 +02:00
|
|
|
uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr)
|
|
|
|
|
{
|
2019-09-27 05:54:23 +02:00
|
|
|
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
|
|
|
|
|
|
|
|
|
|
if (smc->legacy_irq_allocation) {
|
|
|
|
|
return smc->nr_xirqs;
|
2019-09-27 05:44:58 +02:00
|
|
|
} else {
|
2019-09-27 05:54:23 +02:00
|
|
|
return SPAPR_XIRQ_BASE + smc->nr_xirqs - SPAPR_IRQ_MSI;
|
2019-09-27 05:44:58 +02:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
|
2018-12-06 00:22:27 +01:00
|
|
|
{
|
2019-09-27 05:54:23 +02:00
|
|
|
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
|
spapr: Disallow unsupported kernel-irqchip settings
Split mode doesn't make sense on pseries, neither with XICS nor XIVE. But
passing kernel-irqchip=split silently behaves like kernel-irqchip=on.
Other architectures that support kernel-irqchip do terminate QEMU when
split mode is requested but not available though. Do the same with pseries
for consistency.
Similarly, passing kernel-irqchip=on,accel=tcg starts the machine with the
emulated interrupt controller, ie, behaves like kernel-irqchip=off. However,
when passing kernel-irqchip=on,accel=kvm, if we can't initialize the KVM
XICS for some reason, ie, xics_kvm_init() fails, then QEMU is terminated.
This is inconsistent. Terminate QEMU all the same when requesting the
in-kernel interrupt controller without KVM.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <154964986747.291716.2679312373018476920.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-08 19:17:47 +01:00
|
|
|
|
2019-11-13 11:17:12 +01:00
|
|
|
if (kvm_enabled() && kvm_kernel_irqchip_split()) {
|
spapr: Disallow unsupported kernel-irqchip settings
Split mode doesn't make sense on pseries, neither with XICS nor XIVE. But
passing kernel-irqchip=split silently behaves like kernel-irqchip=on.
Other architectures that support kernel-irqchip do terminate QEMU when
split mode is requested but not available though. Do the same with pseries
for consistency.
Similarly, passing kernel-irqchip=on,accel=tcg starts the machine with the
emulated interrupt controller, ie, behaves like kernel-irqchip=off. However,
when passing kernel-irqchip=on,accel=kvm, if we can't initialize the KVM
XICS for some reason, ie, xics_kvm_init() fails, then QEMU is terminated.
This is inconsistent. Terminate QEMU all the same when requesting the
in-kernel interrupt controller without KVM.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <154964986747.291716.2679312373018476920.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-02-08 19:17:47 +01:00
|
|
|
error_setg(errp, "kernel_irqchip split mode not supported on pseries");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-30 04:20:47 +02:00
|
|
|
if (spapr_irq_check(spapr, errp) < 0) {
|
2019-03-28 11:00:44 +01:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-06 00:22:27 +01:00
|
|
|
/* Initialize the MSI IRQ allocator. */
|
2019-09-27 05:44:58 +02:00
|
|
|
spapr_irq_msi_init(spapr);
|
2018-12-06 00:22:27 +01:00
|
|
|
|
2019-09-30 04:24:43 +02:00
|
|
|
if (spapr->irq->xics) {
|
|
|
|
|
Object *obj;
|
|
|
|
|
|
|
|
|
|
obj = object_new(TYPE_ICS_SPAPR);
|
|
|
|
|
|
qom: Drop parameter @errp of object_property_add() & friends
The only way object_property_add() can fail is when a property with
the same name already exists. Since our property names are all
hardcoded, failure is a programming error, and the appropriate way to
handle it is passing &error_abort.
Same for its variants, except for object_property_add_child(), which
additionally fails when the child already has a parent. Parentage is
also under program control, so this is a programming error, too.
We have a bit over 500 callers. Almost half of them pass
&error_abort, slightly fewer ignore errors, one test case handles
errors, and the remaining few callers pass them to their own callers.
The previous few commits demonstrated once again that ignoring
programming errors is a bad idea.
Of the few ones that pass on errors, several violate the Error API.
The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL. Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call. ich9_pm_add_properties(), sparc32_ledma_realize(),
sparc32_dma_realize(), xilinx_axidma_realize(), xilinx_enet_realize()
are wrong that way.
When the one appropriate choice of argument is &error_abort, letting
users pick the argument is a bad idea.
Drop parameter @errp and assert the preconditions instead.
There's one exception to "duplicate property name is a programming
error": the way object_property_add() implements the magic (and
undocumented) "automatic arrayification". Don't drop @errp there.
Instead, rename object_property_add() to object_property_try_add(),
and add the obvious wrapper object_property_add().
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200505152926.18877-15-armbru@redhat.com>
[Two semantic rebase conflicts resolved]
2020-05-05 17:29:22 +02:00
|
|
|
object_property_add_child(OBJECT(spapr), "ics", obj);
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_link(obj, ICS_PROP_XICS, OBJECT(spapr),
|
2019-11-18 00:20:36 +01:00
|
|
|
&error_abort);
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_int(obj, "nr-irqs", smc->nr_xirqs, &error_abort);
|
error: Eliminate error_propagate() with Coccinelle, part 1
When all we do with an Error we receive into a local variable is
propagating to somewhere else, we can just as well receive it there
right away. Convert
if (!foo(..., &err)) {
...
error_propagate(errp, err);
...
return ...
}
to
if (!foo(..., errp)) {
...
...
return ...
}
where nothing else needs @err. Coccinelle script:
@rule1 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
binary operator op;
constant c1, c2;
symbol false;
@@
if (
(
- fun(args, &err, args2)
+ fun(args, errp, args2)
|
- !fun(args, &err, args2)
+ !fun(args, errp, args2)
|
- fun(args, &err, args2) op c1
+ fun(args, errp, args2) op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
)
}
@rule2 forall@
identifier fun, err, errp, lbl;
expression list args, args2;
expression var;
binary operator op;
constant c1, c2;
symbol false;
@@
- var = fun(args, &err, args2);
+ var = fun(args, errp, args2);
... when != err
if (
(
var
|
!var
|
var op c1
)
)
{
... when != err
when != lbl:
when strict
- error_propagate(errp, err);
... when != err
(
return;
|
return c2;
|
return false;
|
return var;
)
}
@depends on rule1 || rule2@
identifier err;
@@
- Error *err = NULL;
... when != err
Not exactly elegant, I'm afraid.
The "when != lbl:" is necessary to avoid transforming
if (fun(args, &err)) {
goto out
}
...
out:
error_propagate(errp, err);
even though other paths to label out still need the error_propagate().
For an actual example, see sclp_realize().
Without the "when strict", Coccinelle transforms vfio_msix_setup(),
incorrectly. I don't know what exactly "when strict" does, only that
it helps here.
The match of return is narrower than what I want, but I can't figure
out how to express "return where the operand doesn't use @err". For
an example where it's too narrow, see vfio_intx_enable().
Silently fails to convert hw/arm/armsse.c, because Coccinelle gets
confused by ARMSSE being used both as typedef and function-like macro
there. Converted manually.
Line breaks tidied up manually. One nested declaration of @local_err
deleted manually. Preexisting unwanted blank line dropped in
hw/riscv/sifive_e.c.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20200707160613.848843-35-armbru@redhat.com>
2020-07-07 18:06:02 +02:00
|
|
|
if (!qdev_realize(DEVICE(obj), NULL, errp)) {
|
2019-09-30 04:24:43 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spapr->ics = ICS_SPAPR(obj);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (spapr->irq->xive) {
|
|
|
|
|
uint32_t nr_servers = spapr_max_server_number(spapr);
|
|
|
|
|
DeviceState *dev;
|
|
|
|
|
int i;
|
|
|
|
|
|
qdev: Convert uses of qdev_create() with Coccinelle
This is the transformation explained in the commit before previous.
Takes care of just one pattern that needs conversion. More to come in
this series.
Coccinelle script:
@ depends on !(file in "hw/arm/highbank.c")@
expression bus, type_name, dev, expr;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr;
identifier DOWN;
@@
- dev = DOWN(qdev_create(bus, type_name));
+ dev = DOWN(qdev_new(type_name));
... when != dev = expr
- qdev_init_nofail(DEVICE(dev));
+ qdev_realize_and_unref(DEVICE(dev), bus, &error_fatal);
@@
expression bus, type_name, expr;
identifier dev;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- qdev_init_nofail(dev);
+ qdev_realize_and_unref(dev, bus, &error_fatal);
@@
expression bus, type_name, dev, expr, errp;
symbol true;
@@
- dev = qdev_create(bus, type_name);
+ dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
@@
expression bus, type_name, expr, errp;
identifier dev;
symbol true;
@@
- DeviceState *dev = qdev_create(bus, type_name);
+ DeviceState *dev = qdev_new(type_name);
... when != dev = expr
- object_property_set_bool(OBJECT(dev), true, "realized", errp);
+ qdev_realize_and_unref(dev, bus, errp);
The first rule exempts hw/arm/highbank.c, because it matches along two
control flow paths there, with different @type_name. Covered by the
next commit's manual conversions.
Missing #include "qapi/error.h" added manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-10-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:31:58 +02:00
|
|
|
dev = qdev_new(TYPE_SPAPR_XIVE);
|
2019-09-27 05:54:23 +02:00
|
|
|
qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_XIRQ_BASE);
|
2019-09-30 04:24:43 +02:00
|
|
|
/*
|
|
|
|
|
* 8 XIVE END structures per CPU. One for each available
|
|
|
|
|
* priority
|
|
|
|
|
*/
|
|
|
|
|
qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3);
|
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in
an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value,
const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and
object_property_parse().
Convert callers with this Coccinelle script:
@@
identifier fun = {
object_property_get, object_property_parse, object_property_set_str,
object_property_set_link, object_property_set_bool,
object_property_set_int, object_property_set_uint, object_property_set,
object_property_set_qobject
};
expression obj, v, name, errp;
@@
- fun(obj, v, name, errp)
+ fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error
message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by
ARMSSE being used both as typedef and function-like macro there.
Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused
by RXCPU being used both as typedef and function-like macro there.
Convert manually. The other files using RXCPU that way don't need
conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20200707160613.848843-27-armbru@redhat.com>
[Straightforwad conflict with commit 2336172d9b "audio: set default
value for pcspk.iobase property" resolved]
2020-07-07 18:05:54 +02:00
|
|
|
object_property_set_link(OBJECT(dev), "xive-fabric", OBJECT(spapr),
|
2020-01-06 15:56:37 +01:00
|
|
|
&error_abort);
|
sysbus: Convert to sysbus_realize() etc. with Coccinelle
Convert from qdev_realize(), qdev_realize_and_unref() with null @bus
argument to sysbus_realize(), sysbus_realize_and_unref().
Coccinelle script:
@@
expression dev, errp;
@@
- qdev_realize(DEVICE(dev), NULL, errp);
+ sysbus_realize(SYS_BUS_DEVICE(dev), errp);
@@
expression sysbus_dev, dev, errp;
@@
+ sysbus_dev = SYS_BUS_DEVICE(dev);
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
- sysbus_dev = SYS_BUS_DEVICE(dev);
@@
expression sysbus_dev, dev, errp;
expression expr;
@@
sysbus_dev = SYS_BUS_DEVICE(dev);
... when != dev = expr;
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(sysbus_dev, errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(DEVICE(dev), NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
@@
expression dev, errp;
@@
- qdev_realize_and_unref(dev, NULL, errp);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp);
Whitespace changes minimized manually.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200610053247.1583243-46-armbru@redhat.com>
[Conflicts in hw/misc/empty_slot.c and hw/sparc/leon3.c resolved]
2020-06-10 07:32:34 +02:00
|
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
2019-09-30 04:24:43 +02:00
|
|
|
|
|
|
|
|
spapr->xive = SPAPR_XIVE(dev);
|
|
|
|
|
|
|
|
|
|
/* Enable the CPU IPIs */
|
|
|
|
|
for (i = 0; i < nr_servers; ++i) {
|
2019-09-26 06:31:13 +02:00
|
|
|
SpaprInterruptControllerClass *sicc
|
|
|
|
|
= SPAPR_INTC_GET_CLASS(spapr->xive);
|
|
|
|
|
|
|
|
|
|
if (sicc->claim_irq(SPAPR_INTC(spapr->xive), SPAPR_IRQ_IPI + i,
|
|
|
|
|
false, errp) < 0) {
|
2019-09-30 04:24:43 +02:00
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spapr_xive_hcall_init(spapr);
|
|
|
|
|
}
|
2019-01-02 06:57:40 +01:00
|
|
|
|
2019-09-26 08:09:46 +02:00
|
|
|
spapr->qirqs = qemu_allocate_irqs(spapr_set_irq, spapr,
|
2019-09-27 05:54:23 +02:00
|
|
|
smc->nr_xirqs + SPAPR_XIRQ_BASE);
|
2019-10-02 03:53:57 +02:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Mostly we don't actually need this until reset, except that not
|
|
|
|
|
* having this set up can cause VFIO devices to issue a
|
|
|
|
|
* false-positive warning during realize(), because they don't yet
|
|
|
|
|
* have an in-kernel irq chip.
|
|
|
|
|
*/
|
|
|
|
|
spapr_irq_update_active_intc(spapr);
|
2018-12-06 00:22:27 +01:00
|
|
|
}
|
2018-07-30 16:11:33 +02:00
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp)
|
2018-07-30 16:11:33 +02:00
|
|
|
{
|
2019-09-26 06:31:13 +02:00
|
|
|
SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
|
|
|
|
|
int i;
|
2019-09-27 05:54:23 +02:00
|
|
|
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
|
2019-09-26 06:31:13 +02:00
|
|
|
int rc;
|
|
|
|
|
|
2019-09-25 05:49:59 +02:00
|
|
|
assert(irq >= SPAPR_XIRQ_BASE);
|
2019-09-27 05:54:23 +02:00
|
|
|
assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE));
|
2019-09-25 05:49:59 +02:00
|
|
|
|
2019-09-26 06:31:13 +02:00
|
|
|
for (i = 0; i < ARRAY_SIZE(intcs); i++) {
|
|
|
|
|
SpaprInterruptController *intc = intcs[i];
|
|
|
|
|
if (intc) {
|
|
|
|
|
SpaprInterruptControllerClass *sicc = SPAPR_INTC_GET_CLASS(intc);
|
|
|
|
|
rc = sicc->claim_irq(intc, irq, lsi, errp);
|
|
|
|
|
if (rc < 0) {
|
|
|
|
|
return rc;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
2018-07-30 16:11:33 +02:00
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
void spapr_irq_free(SpaprMachineState *spapr, int irq, int num)
|
2018-07-30 16:11:33 +02:00
|
|
|
{
|
2019-09-26 06:31:13 +02:00
|
|
|
SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
|
|
|
|
|
int i, j;
|
2019-09-27 05:54:23 +02:00
|
|
|
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
|
2019-09-24 16:12:21 +02:00
|
|
|
|
2019-09-25 05:49:59 +02:00
|
|
|
assert(irq >= SPAPR_XIRQ_BASE);
|
2019-09-27 05:54:23 +02:00
|
|
|
assert((irq + num) <= (smc->nr_xirqs + SPAPR_XIRQ_BASE));
|
2019-09-25 05:49:59 +02:00
|
|
|
|
2019-09-24 16:12:21 +02:00
|
|
|
for (i = irq; i < (irq + num); i++) {
|
2019-09-26 06:31:13 +02:00
|
|
|
for (j = 0; j < ARRAY_SIZE(intcs); j++) {
|
|
|
|
|
SpaprInterruptController *intc = intcs[j];
|
|
|
|
|
|
|
|
|
|
if (intc) {
|
|
|
|
|
SpaprInterruptControllerClass *sicc
|
|
|
|
|
= SPAPR_INTC_GET_CLASS(intc);
|
|
|
|
|
sicc->free_irq(intc, i);
|
|
|
|
|
}
|
|
|
|
|
}
|
2019-09-24 16:12:21 +02:00
|
|
|
}
|
2018-07-30 16:11:33 +02:00
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq)
|
2018-07-30 16:11:33 +02:00
|
|
|
{
|
2019-09-27 05:54:23 +02:00
|
|
|
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
|
|
|
|
|
|
2019-09-23 08:18:28 +02:00
|
|
|
/*
|
|
|
|
|
* This interface is basically for VIO and PHB devices to find the
|
|
|
|
|
* right qemu_irq to manipulate, so we only allow access to the
|
|
|
|
|
* external irqs for now. Currently anything which needs to
|
|
|
|
|
* access the IPIs most naturally gets there via the guest side
|
|
|
|
|
* interfaces, we can change this if we need to in future.
|
|
|
|
|
*/
|
|
|
|
|
assert(irq >= SPAPR_XIRQ_BASE);
|
2019-09-27 05:54:23 +02:00
|
|
|
assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE));
|
2019-09-23 08:18:28 +02:00
|
|
|
|
|
|
|
|
if (spapr->ics) {
|
|
|
|
|
assert(ics_valid_irq(spapr->ics, irq));
|
|
|
|
|
}
|
|
|
|
|
if (spapr->xive) {
|
|
|
|
|
assert(irq < spapr->xive->nr_irqs);
|
|
|
|
|
assert(xive_eas_is_valid(&spapr->xive->eat[irq]));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return spapr->qirqs[irq];
|
2018-07-30 16:11:33 +02:00
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
int spapr_irq_post_load(SpaprMachineState *spapr, int version_id)
|
2018-12-11 23:38:16 +01:00
|
|
|
{
|
2019-09-27 02:53:53 +02:00
|
|
|
SpaprInterruptControllerClass *sicc;
|
|
|
|
|
|
2019-09-26 07:41:39 +02:00
|
|
|
spapr_irq_update_active_intc(spapr);
|
2019-09-27 02:53:53 +02:00
|
|
|
sicc = SPAPR_INTC_GET_CLASS(spapr->active_intc);
|
|
|
|
|
return sicc->post_load(spapr->active_intc, version_id);
|
2018-12-11 23:38:16 +01:00
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
void spapr_irq_reset(SpaprMachineState *spapr, Error **errp)
|
2018-12-11 23:38:17 +01:00
|
|
|
{
|
2019-07-26 16:44:49 +02:00
|
|
|
assert(!spapr->irq_map || bitmap_empty(spapr->irq_map, spapr->irq_map_nr));
|
|
|
|
|
|
2019-09-26 07:41:39 +02:00
|
|
|
spapr_irq_update_active_intc(spapr);
|
2018-12-11 23:38:17 +01:00
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp)
|
2019-02-19 18:18:13 +01:00
|
|
|
{
|
2019-09-23 07:19:28 +02:00
|
|
|
const char *nodename = "interrupt-controller";
|
2019-02-19 18:18:13 +01:00
|
|
|
int offset, phandle;
|
|
|
|
|
|
|
|
|
|
offset = fdt_subnode_offset(fdt, 0, nodename);
|
|
|
|
|
if (offset < 0) {
|
2019-09-23 07:19:28 +02:00
|
|
|
error_setg(errp, "Can't find node \"%s\": %s",
|
|
|
|
|
nodename, fdt_strerror(offset));
|
2019-02-19 18:18:13 +01:00
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
phandle = fdt_get_phandle(fdt, offset);
|
|
|
|
|
if (!phandle) {
|
|
|
|
|
error_setg(errp, "Can't get phandle of node \"%s\"", nodename);
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return phandle;
|
|
|
|
|
}
|
|
|
|
|
|
2019-09-26 07:41:39 +02:00
|
|
|
static void set_active_intc(SpaprMachineState *spapr,
|
|
|
|
|
SpaprInterruptController *new_intc)
|
|
|
|
|
{
|
|
|
|
|
SpaprInterruptControllerClass *sicc;
|
2019-11-26 17:46:23 +01:00
|
|
|
uint32_t nr_servers = spapr_max_server_number(spapr);
|
2019-09-26 07:41:39 +02:00
|
|
|
|
|
|
|
|
assert(new_intc);
|
|
|
|
|
|
|
|
|
|
if (new_intc == spapr->active_intc) {
|
|
|
|
|
/* Nothing to do */
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (spapr->active_intc) {
|
|
|
|
|
sicc = SPAPR_INTC_GET_CLASS(spapr->active_intc);
|
|
|
|
|
if (sicc->deactivate) {
|
|
|
|
|
sicc->deactivate(spapr->active_intc);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
sicc = SPAPR_INTC_GET_CLASS(new_intc);
|
|
|
|
|
if (sicc->activate) {
|
2019-11-26 17:46:23 +01:00
|
|
|
sicc->activate(new_intc, nr_servers, &error_fatal);
|
2019-09-26 07:41:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
spapr->active_intc = new_intc;
|
2019-09-30 07:54:00 +02:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We've changed the kernel irqchip, let VFIO devices know they
|
|
|
|
|
* need to readjust.
|
|
|
|
|
*/
|
|
|
|
|
kvm_irqchip_change_notify();
|
2019-09-26 07:41:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void spapr_irq_update_active_intc(SpaprMachineState *spapr)
|
|
|
|
|
{
|
|
|
|
|
SpaprInterruptController *new_intc;
|
|
|
|
|
|
|
|
|
|
if (!spapr->ics) {
|
|
|
|
|
/*
|
|
|
|
|
* XXX before we run CAS, ov5_cas is initialized empty, which
|
|
|
|
|
* indicates XICS, even if we have ic-mode=xive. TODO: clean
|
|
|
|
|
* up the CAS path so that we have a clearer way of handling
|
|
|
|
|
* this.
|
|
|
|
|
*/
|
|
|
|
|
new_intc = SPAPR_INTC(spapr->xive);
|
2019-10-02 03:53:57 +02:00
|
|
|
} else if (spapr->ov5_cas
|
|
|
|
|
&& spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) {
|
2019-09-26 07:41:39 +02:00
|
|
|
new_intc = SPAPR_INTC(spapr->xive);
|
|
|
|
|
} else {
|
|
|
|
|
new_intc = SPAPR_INTC(spapr->ics);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
set_active_intc(spapr, new_intc);
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-30 16:11:33 +02:00
|
|
|
/*
|
|
|
|
|
* XICS legacy routines - to deprecate one day
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
static int ics_find_free_block(ICSState *ics, int num, int alignnum)
|
|
|
|
|
{
|
|
|
|
|
int first, i;
|
|
|
|
|
|
|
|
|
|
for (first = 0; first < ics->nr_irqs; first += alignnum) {
|
|
|
|
|
if (num > (ics->nr_irqs - first)) {
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
for (i = first; i < first + num; ++i) {
|
2019-09-11 15:39:36 +02:00
|
|
|
if (!ics_irq_free(ics, i)) {
|
2018-07-30 16:11:33 +02:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (i == (first + num)) {
|
|
|
|
|
return first;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp)
|
2018-07-30 16:11:33 +02:00
|
|
|
{
|
|
|
|
|
ICSState *ics = spapr->ics;
|
|
|
|
|
int first = -1;
|
|
|
|
|
|
|
|
|
|
assert(ics);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* MSIMesage::data is used for storing VIRQ so
|
|
|
|
|
* it has to be aligned to num to support multiple
|
|
|
|
|
* MSI vectors. MSI-X is not affected by this.
|
|
|
|
|
* The hint is used for the first IRQ, the rest should
|
|
|
|
|
* be allocated continuously.
|
|
|
|
|
*/
|
|
|
|
|
if (align) {
|
|
|
|
|
assert((num == 1) || (num == 2) || (num == 4) ||
|
|
|
|
|
(num == 8) || (num == 16) || (num == 32));
|
|
|
|
|
first = ics_find_free_block(ics, num, num);
|
|
|
|
|
} else {
|
|
|
|
|
first = ics_find_free_block(ics, num, 1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (first < 0) {
|
|
|
|
|
error_setg(errp, "can't find a free %d-IRQ block", num);
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return first + ics->offset;
|
|
|
|
|
}
|
2018-09-11 07:55:03 +02:00
|
|
|
|
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-03-06 05:35:37 +01:00
|
|
|
SpaprIrq spapr_irq_xics_legacy = {
|
2019-09-25 07:12:07 +02:00
|
|
|
.xics = true,
|
|
|
|
|
.xive = false,
|
2018-09-11 07:55:03 +02:00
|
|
|
};
|
2019-09-24 08:25:08 +02:00
|
|
|
|
|
|
|
|
static void spapr_irq_register_types(void)
|
|
|
|
|
{
|
|
|
|
|
type_register_static(&spapr_intc_info);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
type_init(spapr_irq_register_types)
|