2015-09-10 17:38:59 +02:00
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/*
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* QEMU monitor
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "cpu.h"
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#include "monitor/monitor.h"
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#include "monitor/hmp-target.h"
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#include "hmp.h"
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static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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unsigned int u;
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int i;
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u = 0;
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for (i = 0; i < 8; i++)
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u |= env->crf[i] << (32 - (4 * (i + 1)));
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return u;
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}
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static target_long monitor_get_decr (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return cpu_ppc_load_decr(env);
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}
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static target_long monitor_get_tbu (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return cpu_ppc_load_tbu(env);
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}
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static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
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{
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CPUArchState *env = mon_get_cpu_env();
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return cpu_ppc_load_tbl(env);
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}
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void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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{
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CPUArchState *env1 = mon_get_cpu_env();
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dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
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}
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const MonitorDef monitor_defs[] = {
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{ "fpscr", offsetof(CPUPPCState, fpscr) },
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/* Next instruction pointer */
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{ "nip|pc", offsetof(CPUPPCState, nip) },
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{ "lr", offsetof(CPUPPCState, lr) },
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{ "ctr", offsetof(CPUPPCState, ctr) },
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{ "decr", 0, &monitor_get_decr, },
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2015-11-12 04:44:23 +01:00
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{ "ccr|cr", 0, &monitor_get_ccr, },
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2015-09-10 17:38:59 +02:00
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/* Machine state register */
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2015-11-12 04:44:23 +01:00
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{ "xer", offsetof(CPUPPCState, xer) },
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{ "msr", offsetof(CPUPPCState, msr) },
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2015-09-10 17:38:59 +02:00
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{ "tbu", 0, &monitor_get_tbu, },
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{ "tbl", 0, &monitor_get_tbl, },
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{ NULL },
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};
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const MonitorDef *target_monitor_defs(void)
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{
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return monitor_defs;
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}
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2015-11-12 04:44:23 +01:00
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static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
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{
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int regnum;
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char *endptr = NULL;
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if (!*numstr) {
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return false;
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}
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regnum = strtoul(numstr, &endptr, 10);
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if (*endptr || (regnum >= maxnum)) {
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return false;
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}
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*pregnum = regnum;
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return true;
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}
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int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
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{
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int i, regnum;
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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/* General purpose registers */
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if ((tolower(name[0]) == 'r') &&
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ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), ®num)) {
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*pval = env->gpr[regnum];
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return 0;
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}
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/* Floating point registers */
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if ((tolower(name[0]) == 'f') &&
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ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->fpr), ®num)) {
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*pval = env->fpr[regnum];
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return 0;
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}
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/* Special purpose registers */
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for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
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ppc_spr_t *spr = &env->spr_cb[i];
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if (spr->name && (strcasecmp(name, spr->name) == 0)) {
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*pval = env->spr[i];
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return 0;
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}
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}
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/* Segment registers */
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#if !defined(CONFIG_USER_ONLY)
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if ((strncasecmp(name, "sr", 2) == 0) &&
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ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), ®num)) {
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*pval = env->sr[regnum];
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return 0;
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}
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#endif
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return -EINVAL;
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}
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