2017-02-07 19:29:59 +01:00
|
|
|
/*
|
|
|
|
* ASPEED Watchdog Controller
|
|
|
|
*
|
|
|
|
* Copyright (C) 2016-2017 IBM Corp.
|
|
|
|
*
|
|
|
|
* This code is licensed under the GPL version 2 or later. See the
|
|
|
|
* COPYING file in the top-level directory.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "qemu/osdep.h"
|
2017-09-04 16:21:54 +02:00
|
|
|
|
|
|
|
#include "qapi/error.h"
|
2017-02-07 19:29:59 +01:00
|
|
|
#include "qemu/log.h"
|
2019-05-23 16:35:07 +02:00
|
|
|
#include "qemu/module.h"
|
2017-09-04 16:21:54 +02:00
|
|
|
#include "qemu/timer.h"
|
2017-02-07 19:29:59 +01:00
|
|
|
#include "sysemu/watchdog.h"
|
2017-09-04 16:21:54 +02:00
|
|
|
#include "hw/misc/aspeed_scu.h"
|
2019-08-12 07:23:51 +02:00
|
|
|
#include "hw/qdev-properties.h"
|
2017-02-07 19:29:59 +01:00
|
|
|
#include "hw/sysbus.h"
|
|
|
|
#include "hw/watchdog/wdt_aspeed.h"
|
2019-08-12 07:23:45 +02:00
|
|
|
#include "migration/vmstate.h"
|
2021-10-12 08:20:08 +02:00
|
|
|
#include "trace.h"
|
2017-02-07 19:29:59 +01:00
|
|
|
|
2017-09-04 16:21:54 +02:00
|
|
|
#define WDT_STATUS (0x00 / 4)
|
|
|
|
#define WDT_RELOAD_VALUE (0x04 / 4)
|
|
|
|
#define WDT_RESTART (0x08 / 4)
|
|
|
|
#define WDT_CTRL (0x0C / 4)
|
2017-02-07 19:29:59 +01:00
|
|
|
#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
|
|
|
|
#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
|
|
|
|
#define WDT_CTRL_1MHZ_CLK BIT(4)
|
|
|
|
#define WDT_CTRL_WDT_EXT BIT(3)
|
|
|
|
#define WDT_CTRL_WDT_INTR BIT(2)
|
|
|
|
#define WDT_CTRL_RESET_SYSTEM BIT(1)
|
|
|
|
#define WDT_CTRL_ENABLE BIT(0)
|
2017-09-04 16:21:54 +02:00
|
|
|
#define WDT_RESET_WIDTH (0x18 / 4)
|
|
|
|
#define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
|
|
|
|
#define WDT_POLARITY_MASK (0xFF << 24)
|
|
|
|
#define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
|
|
|
|
#define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
|
|
|
|
#define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
|
|
|
|
#define WDT_DRIVE_TYPE_MASK (0xFF << 24)
|
|
|
|
#define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
|
|
|
|
#define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
|
2019-09-25 16:32:36 +02:00
|
|
|
#define WDT_RESET_MASK1 (0x1c / 4)
|
2017-02-07 19:29:59 +01:00
|
|
|
|
2017-09-04 16:21:54 +02:00
|
|
|
#define WDT_TIMEOUT_STATUS (0x10 / 4)
|
|
|
|
#define WDT_TIMEOUT_CLEAR (0x14 / 4)
|
2017-02-07 19:29:59 +01:00
|
|
|
|
2017-09-04 16:21:54 +02:00
|
|
|
#define WDT_RESTART_MAGIC 0x4755
|
2017-02-07 19:29:59 +01:00
|
|
|
|
2019-09-25 16:32:36 +02:00
|
|
|
#define AST2600_SCU_RESET_CONTROL1 (0x40 / 4)
|
2019-07-01 18:26:18 +02:00
|
|
|
#define SCU_RESET_CONTROL1 (0x04 / 4)
|
|
|
|
#define SCU_RESET_SDRAM BIT(0)
|
|
|
|
|
2017-02-07 19:29:59 +01:00
|
|
|
static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
|
|
|
|
{
|
|
|
|
return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
|
|
|
|
{
|
|
|
|
AspeedWDTState *s = ASPEED_WDT(opaque);
|
|
|
|
|
2021-10-12 08:20:08 +02:00
|
|
|
trace_aspeed_wdt_read(offset, size);
|
|
|
|
|
2017-02-07 19:29:59 +01:00
|
|
|
offset >>= 2;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case WDT_STATUS:
|
|
|
|
return s->regs[WDT_STATUS];
|
|
|
|
case WDT_RELOAD_VALUE:
|
|
|
|
return s->regs[WDT_RELOAD_VALUE];
|
|
|
|
case WDT_RESTART:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: read from write-only reg at offset 0x%"
|
|
|
|
HWADDR_PRIx "\n", __func__, offset);
|
|
|
|
return 0;
|
|
|
|
case WDT_CTRL:
|
|
|
|
return s->regs[WDT_CTRL];
|
2017-09-04 16:21:54 +02:00
|
|
|
case WDT_RESET_WIDTH:
|
|
|
|
return s->regs[WDT_RESET_WIDTH];
|
2019-09-25 16:32:36 +02:00
|
|
|
case WDT_RESET_MASK1:
|
|
|
|
return s->regs[WDT_RESET_MASK1];
|
2017-02-07 19:29:59 +01:00
|
|
|
case WDT_TIMEOUT_STATUS:
|
|
|
|
case WDT_TIMEOUT_CLEAR:
|
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
|
|
|
|
__func__, offset);
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
|
|
|
|
__func__, offset);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:03 +01:00
|
|
|
static void aspeed_wdt_reload(AspeedWDTState *s)
|
2017-02-07 19:29:59 +01:00
|
|
|
{
|
2017-10-12 14:20:06 +02:00
|
|
|
uint64_t reload;
|
2017-02-07 19:29:59 +01:00
|
|
|
|
2019-11-19 15:12:03 +01:00
|
|
|
if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) {
|
2017-02-07 19:29:59 +01:00
|
|
|
reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
|
|
|
|
s->pclk_freq);
|
|
|
|
} else {
|
2017-10-12 14:20:06 +02:00
|
|
|
reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
|
2017-02-07 19:29:59 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (aspeed_wdt_is_enabled(s)) {
|
|
|
|
timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:03 +01:00
|
|
|
static void aspeed_wdt_reload_1mhz(AspeedWDTState *s)
|
|
|
|
{
|
|
|
|
uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
|
|
|
|
|
|
|
|
if (aspeed_wdt_is_enabled(s)) {
|
|
|
|
timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-09-20 08:50:59 +02:00
|
|
|
static uint64_t aspeed_2400_sanitize_ctrl(uint64_t data)
|
|
|
|
{
|
|
|
|
return data & 0xffff;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t aspeed_2500_sanitize_ctrl(uint64_t data)
|
|
|
|
{
|
|
|
|
return (data & ~(0xfUL << 8)) | WDT_CTRL_1MHZ_CLK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t aspeed_2600_sanitize_ctrl(uint64_t data)
|
|
|
|
{
|
|
|
|
return data & ~(0x7UL << 7);
|
|
|
|
}
|
2019-11-19 15:12:03 +01:00
|
|
|
|
2017-02-07 19:29:59 +01:00
|
|
|
static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
|
|
|
|
unsigned size)
|
|
|
|
{
|
|
|
|
AspeedWDTState *s = ASPEED_WDT(opaque);
|
2019-09-25 16:32:35 +02:00
|
|
|
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
|
2021-09-20 08:50:59 +02:00
|
|
|
bool enable;
|
2017-02-07 19:29:59 +01:00
|
|
|
|
2021-10-12 08:20:08 +02:00
|
|
|
trace_aspeed_wdt_write(offset, size, data);
|
|
|
|
|
2017-02-07 19:29:59 +01:00
|
|
|
offset >>= 2;
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
case WDT_STATUS:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: write to read-only reg at offset 0x%"
|
|
|
|
HWADDR_PRIx "\n", __func__, offset);
|
|
|
|
break;
|
|
|
|
case WDT_RELOAD_VALUE:
|
|
|
|
s->regs[WDT_RELOAD_VALUE] = data;
|
|
|
|
break;
|
|
|
|
case WDT_RESTART:
|
|
|
|
if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
|
|
|
|
s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
|
2019-11-19 15:12:03 +01:00
|
|
|
awc->wdt_reload(s);
|
2017-02-07 19:29:59 +01:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case WDT_CTRL:
|
2021-09-20 08:50:59 +02:00
|
|
|
data = awc->sanitize_ctrl(data);
|
|
|
|
enable = data & WDT_CTRL_ENABLE;
|
2017-02-07 19:29:59 +01:00
|
|
|
if (enable && !aspeed_wdt_is_enabled(s)) {
|
|
|
|
s->regs[WDT_CTRL] = data;
|
2019-11-19 15:12:03 +01:00
|
|
|
awc->wdt_reload(s);
|
2017-02-07 19:29:59 +01:00
|
|
|
} else if (!enable && aspeed_wdt_is_enabled(s)) {
|
|
|
|
s->regs[WDT_CTRL] = data;
|
|
|
|
timer_del(s->timer);
|
2021-09-20 08:50:59 +02:00
|
|
|
} else {
|
|
|
|
s->regs[WDT_CTRL] = data;
|
2017-02-07 19:29:59 +01:00
|
|
|
}
|
|
|
|
break;
|
2017-09-04 16:21:54 +02:00
|
|
|
case WDT_RESET_WIDTH:
|
2019-09-25 16:32:35 +02:00
|
|
|
if (awc->reset_pulse) {
|
|
|
|
awc->reset_pulse(s, data & WDT_POLARITY_MASK);
|
2017-09-04 16:21:54 +02:00
|
|
|
}
|
2019-09-25 16:32:35 +02:00
|
|
|
s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask;
|
|
|
|
s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask;
|
2017-09-04 16:21:54 +02:00
|
|
|
break;
|
2019-09-25 16:32:35 +02:00
|
|
|
|
2019-09-25 16:32:36 +02:00
|
|
|
case WDT_RESET_MASK1:
|
|
|
|
/* TODO: implement */
|
|
|
|
s->regs[WDT_RESET_MASK1] = data;
|
|
|
|
break;
|
|
|
|
|
2017-02-07 19:29:59 +01:00
|
|
|
case WDT_TIMEOUT_STATUS:
|
|
|
|
case WDT_TIMEOUT_CLEAR:
|
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
|
|
|
|
__func__, offset);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
|
|
|
|
__func__, offset);
|
|
|
|
}
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
static WatchdogTimerModel model = {
|
|
|
|
.wdt_name = TYPE_ASPEED_WDT,
|
|
|
|
.wdt_description = "Aspeed watchdog device",
|
|
|
|
};
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_aspeed_wdt = {
|
|
|
|
.name = "vmstate_aspeed_wdt",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_TIMER_PTR(timer, AspeedWDTState),
|
|
|
|
VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps aspeed_wdt_ops = {
|
|
|
|
.read = aspeed_wdt_read,
|
|
|
|
.write = aspeed_wdt_write,
|
|
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
|
|
.valid.min_access_size = 4,
|
|
|
|
.valid.max_access_size = 4,
|
|
|
|
.valid.unaligned = false,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void aspeed_wdt_reset(DeviceState *dev)
|
|
|
|
{
|
|
|
|
AspeedWDTState *s = ASPEED_WDT(dev);
|
2021-09-20 08:50:59 +02:00
|
|
|
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
|
2017-02-07 19:29:59 +01:00
|
|
|
|
2022-05-02 17:03:03 +02:00
|
|
|
s->regs[WDT_STATUS] = awc->default_status;
|
|
|
|
s->regs[WDT_RELOAD_VALUE] = awc->default_reload_value;
|
2017-02-07 19:29:59 +01:00
|
|
|
s->regs[WDT_RESTART] = 0;
|
2021-09-20 08:50:59 +02:00
|
|
|
s->regs[WDT_CTRL] = awc->sanitize_ctrl(0);
|
2017-09-04 16:21:54 +02:00
|
|
|
s->regs[WDT_RESET_WIDTH] = 0xFF;
|
2017-02-07 19:29:59 +01:00
|
|
|
|
|
|
|
timer_del(s->timer);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_wdt_timer_expired(void *dev)
|
|
|
|
{
|
|
|
|
AspeedWDTState *s = ASPEED_WDT(dev);
|
2019-09-25 16:32:35 +02:00
|
|
|
uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg;
|
2017-02-07 19:29:59 +01:00
|
|
|
|
2019-07-01 18:26:18 +02:00
|
|
|
/* Do not reset on SDRAM controller reset */
|
2019-09-25 16:32:35 +02:00
|
|
|
if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) {
|
2019-07-01 18:26:18 +02:00
|
|
|
timer_del(s->timer);
|
|
|
|
s->regs[WDT_CTRL] = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:02 +01:00
|
|
|
qemu_log_mask(CPU_LOG_RESET, "Watchdog timer %" HWADDR_PRIx " expired.\n",
|
|
|
|
s->iomem.addr);
|
2017-02-07 19:29:59 +01:00
|
|
|
watchdog_perform_action();
|
|
|
|
timer_del(s->timer);
|
|
|
|
}
|
|
|
|
|
|
|
|
#define PCLK_HZ 24000000
|
|
|
|
|
|
|
|
static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
|
|
AspeedWDTState *s = ASPEED_WDT(dev);
|
2019-07-01 18:26:18 +02:00
|
|
|
|
2019-11-19 15:12:10 +01:00
|
|
|
assert(s->scu);
|
2017-02-07 19:29:59 +01:00
|
|
|
|
|
|
|
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
|
|
|
|
|
|
|
|
/* FIXME: This setting should be derived from the SCU hw strapping
|
|
|
|
* register SCU70
|
|
|
|
*/
|
|
|
|
s->pclk_freq = PCLK_HZ;
|
|
|
|
|
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
|
|
|
|
TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
}
|
|
|
|
|
2019-11-19 15:12:10 +01:00
|
|
|
static Property aspeed_wdt_properties[] = {
|
|
|
|
DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU,
|
|
|
|
AspeedSCUState *),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
2017-02-07 19:29:59 +01:00
|
|
|
static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
2019-09-25 16:32:35 +02:00
|
|
|
dc->desc = "ASPEED Watchdog Controller";
|
2017-02-07 19:29:59 +01:00
|
|
|
dc->realize = aspeed_wdt_realize;
|
|
|
|
dc->reset = aspeed_wdt_reset;
|
2021-10-27 14:34:53 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
|
2017-02-07 19:29:59 +01:00
|
|
|
dc->vmsd = &vmstate_aspeed_wdt;
|
2020-01-10 16:30:32 +01:00
|
|
|
device_class_set_props(dc, aspeed_wdt_properties);
|
2021-10-27 14:34:53 +02:00
|
|
|
dc->desc = "Aspeed watchdog device";
|
2017-02-07 19:29:59 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo aspeed_wdt_info = {
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.name = TYPE_ASPEED_WDT,
|
|
|
|
.instance_size = sizeof(AspeedWDTState),
|
|
|
|
.class_init = aspeed_wdt_class_init,
|
2019-09-25 16:32:35 +02:00
|
|
|
.class_size = sizeof(AspeedWDTClass),
|
|
|
|
.abstract = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
|
|
|
|
|
|
|
|
dc->desc = "ASPEED 2400 Watchdog Controller";
|
|
|
|
awc->offset = 0x20;
|
|
|
|
awc->ext_pulse_width_mask = 0xff;
|
|
|
|
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
|
2019-11-19 15:12:03 +01:00
|
|
|
awc->wdt_reload = aspeed_wdt_reload;
|
2021-09-20 08:50:59 +02:00
|
|
|
awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl;
|
2022-05-02 17:03:03 +02:00
|
|
|
awc->default_status = 0x03EF1480;
|
|
|
|
awc->default_reload_value = 0x03EF1480;
|
2019-09-25 16:32:35 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo aspeed_2400_wdt_info = {
|
|
|
|
.name = TYPE_ASPEED_2400_WDT,
|
|
|
|
.parent = TYPE_ASPEED_WDT,
|
|
|
|
.instance_size = sizeof(AspeedWDTState),
|
|
|
|
.class_init = aspeed_2400_wdt_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property)
|
|
|
|
{
|
|
|
|
if (property) {
|
|
|
|
if (property == WDT_ACTIVE_HIGH_MAGIC) {
|
|
|
|
s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH;
|
|
|
|
} else if (property == WDT_ACTIVE_LOW_MAGIC) {
|
|
|
|
s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;
|
|
|
|
} else if (property == WDT_PUSH_PULL_MAGIC) {
|
|
|
|
s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL;
|
|
|
|
} else if (property == WDT_OPEN_DRAIN_MAGIC) {
|
|
|
|
s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
|
|
|
|
|
|
|
|
dc->desc = "ASPEED 2500 Watchdog Controller";
|
|
|
|
awc->offset = 0x20;
|
|
|
|
awc->ext_pulse_width_mask = 0xfffff;
|
|
|
|
awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
|
|
|
|
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
|
2019-11-19 15:12:03 +01:00
|
|
|
awc->wdt_reload = aspeed_wdt_reload_1mhz;
|
2021-09-20 08:50:59 +02:00
|
|
|
awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl;
|
2022-05-02 17:03:03 +02:00
|
|
|
awc->default_status = 0x014FB180;
|
|
|
|
awc->default_reload_value = 0x014FB180;
|
2019-09-25 16:32:35 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo aspeed_2500_wdt_info = {
|
|
|
|
.name = TYPE_ASPEED_2500_WDT,
|
|
|
|
.parent = TYPE_ASPEED_WDT,
|
|
|
|
.instance_size = sizeof(AspeedWDTState),
|
|
|
|
.class_init = aspeed_2500_wdt_class_init,
|
2017-02-07 19:29:59 +01:00
|
|
|
};
|
|
|
|
|
2019-09-25 16:32:36 +02:00
|
|
|
static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
|
|
|
|
|
|
|
|
dc->desc = "ASPEED 2600 Watchdog Controller";
|
|
|
|
awc->offset = 0x40;
|
|
|
|
awc->ext_pulse_width_mask = 0xfffff; /* TODO */
|
|
|
|
awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
|
|
|
|
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
|
2019-11-19 15:12:03 +01:00
|
|
|
awc->wdt_reload = aspeed_wdt_reload_1mhz;
|
2021-09-20 08:50:59 +02:00
|
|
|
awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
|
2022-05-02 17:03:03 +02:00
|
|
|
awc->default_status = 0x014FB180;
|
|
|
|
awc->default_reload_value = 0x014FB180;
|
2019-09-25 16:32:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo aspeed_2600_wdt_info = {
|
|
|
|
.name = TYPE_ASPEED_2600_WDT,
|
|
|
|
.parent = TYPE_ASPEED_WDT,
|
|
|
|
.instance_size = sizeof(AspeedWDTState),
|
|
|
|
.class_init = aspeed_2600_wdt_class_init,
|
|
|
|
};
|
|
|
|
|
2022-05-02 17:03:03 +02:00
|
|
|
static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
|
|
|
|
|
|
|
|
dc->desc = "ASPEED 1030 Watchdog Controller";
|
|
|
|
awc->offset = 0x80;
|
|
|
|
awc->ext_pulse_width_mask = 0xfffff; /* TODO */
|
|
|
|
awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
|
|
|
|
awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
|
|
|
|
awc->wdt_reload = aspeed_wdt_reload_1mhz;
|
|
|
|
awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
|
|
|
|
awc->default_status = 0x014FB180;
|
|
|
|
awc->default_reload_value = 0x014FB180;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo aspeed_1030_wdt_info = {
|
|
|
|
.name = TYPE_ASPEED_1030_WDT,
|
|
|
|
.parent = TYPE_ASPEED_WDT,
|
|
|
|
.instance_size = sizeof(AspeedWDTState),
|
|
|
|
.class_init = aspeed_1030_wdt_class_init,
|
|
|
|
};
|
|
|
|
|
2017-02-07 19:29:59 +01:00
|
|
|
static void wdt_aspeed_register_types(void)
|
|
|
|
{
|
|
|
|
watchdog_add_model(&model);
|
|
|
|
type_register_static(&aspeed_wdt_info);
|
2019-09-25 16:32:35 +02:00
|
|
|
type_register_static(&aspeed_2400_wdt_info);
|
|
|
|
type_register_static(&aspeed_2500_wdt_info);
|
2019-09-25 16:32:36 +02:00
|
|
|
type_register_static(&aspeed_2600_wdt_info);
|
2022-05-02 17:03:03 +02:00
|
|
|
type_register_static(&aspeed_1030_wdt_info);
|
2017-02-07 19:29:59 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
type_init(wdt_aspeed_register_types)
|