2018-02-12 02:14:10 +01:00
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#
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# HPPA instruction decode definitions.
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#
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# Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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2020-10-23 14:33:53 +02:00
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# version 2.1 of the License, or (at your option) any later version.
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2018-02-12 02:14:10 +01:00
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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2018-02-12 03:22:38 +01:00
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####
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# Field definitions
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####
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%assemble_sr3 13:1 14:2
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2018-02-12 05:39:25 +01:00
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%assemble_sr3x 13:1 14:2 !function=expand_sr3x
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2018-02-12 03:22:38 +01:00
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2018-02-13 00:54:33 +01:00
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%assemble_11a 0:s1 4:10 !function=expand_shl3
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2018-02-12 18:36:07 +01:00
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%assemble_12 0:s1 2:1 3:10 !function=expand_shl2
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2018-02-13 00:54:33 +01:00
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%assemble_12a 0:s1 3:11 !function=expand_shl2
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2018-02-12 18:36:07 +01:00
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%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
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%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
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2018-02-12 08:33:50 +01:00
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2018-02-13 00:34:12 +01:00
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%assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11
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%lowsign_11 0:s1 1:10
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%lowsign_14 0:s1 1:13
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2018-02-12 03:45:01 +01:00
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%sm_imm 16:10 !function=expand_sm_imm
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2018-02-13 00:54:33 +01:00
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%rm64 1:1 16:5
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2018-02-13 04:37:36 +01:00
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%rt64 6:1 0:5
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2018-02-13 05:08:51 +01:00
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%ra64 7:1 21:5
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%rb64 12:1 16:5
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%rc64 8:1 13:3 9:2
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%rc32 13:3 9:2
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2018-02-13 00:54:33 +01:00
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2018-02-12 07:48:03 +01:00
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%im5_0 0:s1 1:4
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%im5_16 16:s1 17:4
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%ma_to_m 5:1 13:1 !function=ma_to_m
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2018-02-13 00:54:33 +01:00
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%ma2_to_m 2:2 !function=ma_to_m
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%pos_to_m 0:1 !function=pos_to_m
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%neg_to_m 0:1 !function=neg_to_m
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%a_to_m 2:1 !function=neg_to_m
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2018-02-12 07:48:03 +01:00
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2018-02-12 05:39:25 +01:00
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####
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# Argument set definitions
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####
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# All insns that need to form a virtual address should use this set.
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&ldst t b x disp sp m scale size
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2018-02-12 06:44:41 +01:00
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&rr_cf t r cf
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&rrr_cf t r1 r2 cf
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&rrr_cf_sh t r1 r2 cf sh
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2018-02-13 00:34:12 +01:00
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&rri_cf t r i cf
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2018-02-12 06:44:41 +01:00
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2018-02-12 08:33:50 +01:00
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&rrb_c_f disp n c f r1 r2
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&rib_c_f disp n c f r i
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2018-02-12 06:44:41 +01:00
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####
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# Format definitions
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####
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@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf
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@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
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@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
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@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0
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2018-02-13 00:34:12 +01:00
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@rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11
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2018-02-12 06:44:41 +01:00
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2018-02-12 08:33:50 +01:00
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@rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \
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&rrb_c_f disp=%assemble_12
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@rib_cf ...... r:5 ..... c:3 ........... n:1 . \
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&rib_c_f disp=%assemble_12 i=%im5_16
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2018-02-12 02:14:10 +01:00
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####
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# System
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####
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break 000000 ----- ----- --- 00000000 -----
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2018-02-12 03:22:38 +01:00
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mtsp 000000 ----- r:5 ... 11000001 00000 sp=%assemble_sr3
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mtctl 000000 t:5 r:5 --- 11000010 00000
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mtsarcm 000000 01011 r:5 --- 11000110 00000
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mtsm 000000 00000 r:5 000 11000011 00000
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mfia 000000 ----- 00000 --- 10100101 t:5
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mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3
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mfctl 000000 r:5 00000- e:1 -01000101 t:5
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2018-02-12 03:45:01 +01:00
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sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma
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ldsid 000000 b:5 ----- sp:2 0 10000101 t:5
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rsm 000000 .......... 000 01110011 t:5 i=%sm_imm
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ssm 000000 .......... 000 01101011 t:5 i=%sm_imm
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rfi 000000 ----- ----- --- 01100000 00000
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rfi_r 000000 ----- ----- --- 01100101 00000
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2018-02-12 05:39:25 +01:00
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2018-02-13 04:46:08 +01:00
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# These are artificial instructions used by QEMU firmware.
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# They are allocated from the unassigned instruction space.
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halt 1111 1111 1111 1101 1110 1010 1101 0000
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reset 1111 1111 1111 1101 1110 1010 1101 0001
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2022-01-05 23:09:04 +01:00
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getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010
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2018-02-13 04:46:08 +01:00
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2018-02-12 05:39:25 +01:00
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####
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# Memory Management
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####
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@addrx ...... b:5 x:5 .. ........ m:1 ..... \
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&ldst disp=0 scale=0 t=0 sp=0 size=0
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nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp
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nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index
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nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce
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nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a
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nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f
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nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice
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nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc
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probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5
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ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1
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ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
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sp=%assemble_sr3x data=0
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2019-04-23 08:36:20 +02:00
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# pcxl and pcxl2 Fast TLB Insert instructions
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ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
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2018-02-12 05:39:25 +01:00
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pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
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pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
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sp=%assemble_sr3x data=0
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lpa 000001 b:5 x:5 sp:2 01001101 m:1 t:5 \
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&ldst disp=0 scale=0 size=0
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lci 000001 ----- ----- -- 01001100 0 t:5
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2018-02-12 06:44:41 +01:00
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####
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# Arith/Log
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####
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target/hppa: Fix boot with old Linux installation CDs
The current qemu hppa emulation emulates a PA1.1 CPU, which can only execute
the 32-bit instruction set. For unknown 64-bit instructions, a instruction trap
is sent to the virtual CPU.
This behaviour is correct in the sense that we emulate what the PA1.1
specification says.
But when trying to boot older Linux installation images, e.g.
ftp://parisc.parisc-linux.org/debian-cd/debian-5.0/lenny-5.0.10-hppa-iso-cd/cdimage.debian.org/debian-5010-hppa-netinst.iso
one finds that qemu fails to boot those images.
The problem is, that in the Linux kernel (e.g. 2.6.26) of those old images
64-bit instructions were used by mistake in the fault handlers. The relevant
instructions (the ",*" indicates that it's a 64-bit instruction) I see are:
0: 09 3e 04 29 sub,* sp,r9,r9
0: 08 3d 06 3d add,* ret1,r1,ret1
0: 0a 09 02 61 or,* r9,r16,r1
0: 0a ba 00 3a andcm,* r26,r21,r26
0: 08 33 02 33 and,* r19,r1,r19
The interesting part is, that real physical 32-bit machines (like the 700/64
and B160L - which is the one we emulate) do boot those images and thus seem to
simply ignore the 64-bit flag on those instructions.
The patch below modifies the qemu instruction decoder to ignore the 64-bit flag
too - which is what real 32-bit hardware seems to do. With this modification
qemu now successfully boots those older images too.
I suggest to apply the patch below - even if it does not reflect what the SPEC
says. Instead it increases the compatibility to really existing hardware and
seem to not create problems if we add real PA2.0 support anytime later.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-08-30 15:35:07 +02:00
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andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf
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and 000010 ..... ..... .... 001000 - ..... @rrr_cf
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or 000010 ..... ..... .... 001001 - ..... @rrr_cf
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2018-02-12 06:44:41 +01:00
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xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf
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uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf
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ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
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cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf
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uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf
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uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf
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dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf
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dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf
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target/hppa: Fix boot with old Linux installation CDs
The current qemu hppa emulation emulates a PA1.1 CPU, which can only execute
the 32-bit instruction set. For unknown 64-bit instructions, a instruction trap
is sent to the virtual CPU.
This behaviour is correct in the sense that we emulate what the PA1.1
specification says.
But when trying to boot older Linux installation images, e.g.
ftp://parisc.parisc-linux.org/debian-cd/debian-5.0/lenny-5.0.10-hppa-iso-cd/cdimage.debian.org/debian-5010-hppa-netinst.iso
one finds that qemu fails to boot those images.
The problem is, that in the Linux kernel (e.g. 2.6.26) of those old images
64-bit instructions were used by mistake in the fault handlers. The relevant
instructions (the ",*" indicates that it's a 64-bit instruction) I see are:
0: 09 3e 04 29 sub,* sp,r9,r9
0: 08 3d 06 3d add,* ret1,r1,ret1
0: 0a 09 02 61 or,* r9,r16,r1
0: 0a ba 00 3a andcm,* r26,r21,r26
0: 08 33 02 33 and,* r19,r1,r19
The interesting part is, that real physical 32-bit machines (like the 700/64
and B160L - which is the one we emulate) do boot those images and thus seem to
simply ignore the 64-bit flag on those instructions.
The patch below modifies the qemu instruction decoder to ignore the 64-bit flag
too - which is what real 32-bit hardware seems to do. With this modification
qemu now successfully boots those older images too.
I suggest to apply the patch below - even if it does not reflect what the SPEC
says. Instead it increases the compatibility to really existing hardware and
seem to not create problems if we add real PA2.0 support anytime later.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-08-30 15:35:07 +02:00
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add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh
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2018-02-12 06:44:41 +01:00
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add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh
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add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh
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add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0
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add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0
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target/hppa: Fix boot with old Linux installation CDs
The current qemu hppa emulation emulates a PA1.1 CPU, which can only execute
the 32-bit instruction set. For unknown 64-bit instructions, a instruction trap
is sent to the virtual CPU.
This behaviour is correct in the sense that we emulate what the PA1.1
specification says.
But when trying to boot older Linux installation images, e.g.
ftp://parisc.parisc-linux.org/debian-cd/debian-5.0/lenny-5.0.10-hppa-iso-cd/cdimage.debian.org/debian-5010-hppa-netinst.iso
one finds that qemu fails to boot those images.
The problem is, that in the Linux kernel (e.g. 2.6.26) of those old images
64-bit instructions were used by mistake in the fault handlers. The relevant
instructions (the ",*" indicates that it's a 64-bit instruction) I see are:
0: 09 3e 04 29 sub,* sp,r9,r9
0: 08 3d 06 3d add,* ret1,r1,ret1
0: 0a 09 02 61 or,* r9,r16,r1
0: 0a ba 00 3a andcm,* r26,r21,r26
0: 08 33 02 33 and,* r19,r1,r19
The interesting part is, that real physical 32-bit machines (like the 700/64
and B160L - which is the one we emulate) do boot those images and thus seem to
simply ignore the 64-bit flag on those instructions.
The patch below modifies the qemu instruction decoder to ignore the 64-bit flag
too - which is what real 32-bit hardware seems to do. With this modification
qemu now successfully boots those older images too.
I suggest to apply the patch below - even if it does not reflect what the SPEC
says. Instead it increases the compatibility to really existing hardware and
seem to not create problems if we add real PA2.0 support anytime later.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-08-30 15:35:07 +02:00
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sub 000010 ..... ..... .... 010000 - ..... @rrr_cf
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2018-02-12 06:44:41 +01:00
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sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf
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sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf
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sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf
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sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf
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sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf
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2018-02-12 07:48:03 +01:00
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2018-02-13 00:34:12 +01:00
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ldil 001000 t:5 ..................... i=%assemble_21
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addil 001010 r:5 ..................... i=%assemble_21
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ldo 001101 b:5 t:5 -- .............. i=%lowsign_14
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addi 101101 ..... ..... .... 0 ........... @rri_cf
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addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf
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addi_tc 101100 ..... ..... .... 0 ........... @rri_cf
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addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf
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subi 100101 ..... ..... .... 0 ........... @rri_cf
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subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf
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cmpiclr 100100 ..... ..... .... 0 ........... @rri_cf
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2018-02-12 07:48:03 +01:00
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####
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# Index Mem
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####
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@ldstx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 &ldst disp=0
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@ldim5 ...... b:5 ..... sp:2 ......... t:5 \
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&ldst disp=%im5_16 x=0 scale=0 m=%ma_to_m
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@stim5 ...... b:5 t:5 sp:2 ......... ..... \
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&ldst disp=%im5_0 x=0 scale=0 m=%ma_to_m
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ld 000011 ..... ..... .. . 1 -- 00 size:2 ...... @ldim5
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ld 000011 ..... ..... .. . 0 -- 00 size:2 ...... @ldstx
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st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5
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ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 size=2
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|
ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx size=2
|
|
|
|
|
lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 size=2
|
|
|
|
|
lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
|
|
|
|
|
sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
|
|
|
|
|
stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
|
2018-02-12 08:23:54 +01:00
|
|
|
|
2018-02-13 04:37:36 +01:00
|
|
|
@fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \
|
|
|
|
|
&ldst t=%rt64 disp=0 size=2
|
|
|
|
|
@fldstwi ...... b:5 ..... sp:2 . ....... . ..... \
|
|
|
|
|
&ldst t=%rt64 disp=%im5_16 m=%ma_to_m x=0 scale=0 size=2
|
|
|
|
|
|
|
|
|
|
fldw 001001 ..... ..... .. . 0 -- 000 . . ..... @fldstwx
|
|
|
|
|
fldw 001001 ..... ..... .. . 1 -- 000 . . ..... @fldstwi
|
|
|
|
|
fstw 001001 ..... ..... .. . 0 -- 100 . . ..... @fldstwx
|
|
|
|
|
fstw 001001 ..... ..... .. . 1 -- 100 . . ..... @fldstwi
|
|
|
|
|
|
|
|
|
|
@fldstdx ...... b:5 x:5 sp:2 scale:1 ....... m:1 t:5 \
|
|
|
|
|
&ldst disp=0 size=3
|
|
|
|
|
@fldstdi ...... b:5 ..... sp:2 . ....... . t:5 \
|
|
|
|
|
&ldst disp=%im5_16 m=%ma_to_m x=0 scale=0 size=3
|
|
|
|
|
|
|
|
|
|
fldd 001011 ..... ..... .. . 0 -- 000 0 . ..... @fldstdx
|
|
|
|
|
fldd 001011 ..... ..... .. . 1 -- 000 0 . ..... @fldstdi
|
|
|
|
|
fstd 001011 ..... ..... .. . 0 -- 100 0 . ..... @fldstdx
|
|
|
|
|
fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
|
|
|
|
|
|
2018-02-13 00:54:33 +01:00
|
|
|
####
|
|
|
|
|
# Offset Mem
|
|
|
|
|
####
|
|
|
|
|
|
|
|
|
|
@ldstim14 ...... b:5 t:5 sp:2 .............. \
|
|
|
|
|
&ldst disp=%lowsign_14 x=0 scale=0 m=0
|
|
|
|
|
@ldstim14m ...... b:5 t:5 sp:2 .............. \
|
|
|
|
|
&ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m
|
|
|
|
|
@ldstim12m ...... b:5 t:5 sp:2 .............. \
|
|
|
|
|
&ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
|
|
|
|
|
|
|
|
|
|
# LDB, LDH, LDW, LDWM
|
|
|
|
|
ld 010000 ..... ..... .. .............. @ldstim14 size=0
|
|
|
|
|
ld 010001 ..... ..... .. .............. @ldstim14 size=1
|
|
|
|
|
ld 010010 ..... ..... .. .............. @ldstim14 size=2
|
|
|
|
|
ld 010011 ..... ..... .. .............. @ldstim14m size=2
|
|
|
|
|
ld 010111 ..... ..... .. ...........10. @ldstim12m size=2
|
|
|
|
|
|
|
|
|
|
# STB, STH, STW, STWM
|
|
|
|
|
st 011000 ..... ..... .. .............. @ldstim14 size=0
|
|
|
|
|
st 011001 ..... ..... .. .............. @ldstim14 size=1
|
|
|
|
|
st 011010 ..... ..... .. .............. @ldstim14 size=2
|
|
|
|
|
st 011011 ..... ..... .. .............. @ldstim14m size=2
|
|
|
|
|
st 011111 ..... ..... .. ...........10. @ldstim12m size=2
|
|
|
|
|
|
|
|
|
|
fldw 010110 b:5 ..... sp:2 .............. \
|
|
|
|
|
&ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
|
|
|
|
|
fldw 010111 b:5 ..... sp:2 ...........0.. \
|
|
|
|
|
&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
|
|
|
|
|
|
|
|
|
|
fstw 011110 b:5 ..... sp:2 .............. \
|
|
|
|
|
&ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
|
|
|
|
|
fstw 011111 b:5 ..... sp:2 ...........0.. \
|
|
|
|
|
&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
|
|
|
|
|
|
|
|
|
|
fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \
|
|
|
|
|
&ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
|
|
|
|
|
|
|
|
|
|
fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \
|
|
|
|
|
&ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
|
|
|
|
|
|
2018-02-12 08:23:54 +01:00
|
|
|
####
|
|
|
|
|
# Floating-point Multiply Add
|
|
|
|
|
####
|
|
|
|
|
|
|
|
|
|
&mpyadd rm1 rm2 ta ra tm
|
|
|
|
|
@mpyadd ...... rm1:5 rm2:5 ta:5 ra:5 . tm:5 &mpyadd
|
|
|
|
|
|
|
|
|
|
fmpyadd_f 000110 ..... ..... ..... ..... 0 ..... @mpyadd
|
|
|
|
|
fmpyadd_d 000110 ..... ..... ..... ..... 1 ..... @mpyadd
|
|
|
|
|
fmpysub_f 100110 ..... ..... ..... ..... 0 ..... @mpyadd
|
|
|
|
|
fmpysub_d 100110 ..... ..... ..... ..... 1 ..... @mpyadd
|
2018-02-12 08:33:50 +01:00
|
|
|
|
|
|
|
|
####
|
|
|
|
|
# Conditional Branches
|
|
|
|
|
####
|
|
|
|
|
|
|
|
|
|
bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12
|
|
|
|
|
bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12
|
|
|
|
|
|
|
|
|
|
movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
|
|
|
|
|
movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
|
|
|
|
|
|
|
|
|
|
cmpb 100000 ..... ..... ... ........... . . @rrb_cf f=0
|
|
|
|
|
cmpb 100010 ..... ..... ... ........... . . @rrb_cf f=1
|
|
|
|
|
cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=0
|
|
|
|
|
cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=1
|
|
|
|
|
|
|
|
|
|
addb 101000 ..... ..... ... ........... . . @rrb_cf f=0
|
|
|
|
|
addb 101010 ..... ..... ... ........... . . @rrb_cf f=1
|
|
|
|
|
addbi 101001 ..... ..... ... ........... . . @rib_cf f=0
|
|
|
|
|
addbi 101011 ..... ..... ... ........... . . @rib_cf f=1
|
2018-02-12 09:26:48 +01:00
|
|
|
|
|
|
|
|
####
|
|
|
|
|
# Shift, Extract, Deposit
|
|
|
|
|
####
|
|
|
|
|
|
|
|
|
|
shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5
|
|
|
|
|
shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5
|
|
|
|
|
|
|
|
|
|
extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5
|
|
|
|
|
extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5
|
|
|
|
|
|
|
|
|
|
depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5
|
|
|
|
|
depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5
|
|
|
|
|
depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=%im5_16
|
|
|
|
|
depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=%im5_16
|
2018-02-12 18:36:07 +01:00
|
|
|
|
|
|
|
|
####
|
|
|
|
|
# Branch External
|
|
|
|
|
####
|
|
|
|
|
|
|
|
|
|
&BE b l n disp sp
|
|
|
|
|
@be ...... b:5 ..... ... ........... n:1 . \
|
|
|
|
|
&BE disp=%assemble_17 sp=%assemble_sr3
|
|
|
|
|
|
|
|
|
|
be 111000 ..... ..... ... ........... . . @be l=0
|
|
|
|
|
be 111001 ..... ..... ... ........... . . @be l=31
|
|
|
|
|
|
|
|
|
|
####
|
|
|
|
|
# Branch
|
|
|
|
|
####
|
|
|
|
|
|
|
|
|
|
&BL l n disp
|
|
|
|
|
@bl ...... l:5 ..... ... ........... n:1 . &BL disp=%assemble_17
|
|
|
|
|
|
|
|
|
|
# B,L and B,L,PUSH
|
|
|
|
|
bl 111010 ..... ..... 000 ........... . . @bl
|
|
|
|
|
bl 111010 ..... ..... 100 ........... . . @bl
|
|
|
|
|
# B,L (long displacement)
|
|
|
|
|
bl 111010 ..... ..... 101 ........... n:1 . &BL l=2 \
|
|
|
|
|
disp=%assemble_22
|
|
|
|
|
b_gate 111010 ..... ..... 001 ........... . . @bl
|
|
|
|
|
blr 111010 l:5 x:5 010 00000000000 n:1 0
|
|
|
|
|
bv 111010 b:5 x:5 110 00000000000 n:1 0
|
|
|
|
|
bve 111010 b:5 00000 110 10000000000 n:1 - l=0
|
|
|
|
|
bve 111010 b:5 00000 111 10000000000 n:1 - l=2
|
2018-02-13 05:08:51 +01:00
|
|
|
|
|
|
|
|
####
|
|
|
|
|
# FP Fused Multiple-Add
|
|
|
|
|
####
|
|
|
|
|
|
|
|
|
|
fmpyfadd_f 101110 ..... ..... ... . 0 ... . . neg:1 ..... \
|
|
|
|
|
rm1=%ra64 rm2=%rb64 ra3=%rc64 t=%rt64
|
|
|
|
|
fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32
|
2018-02-13 08:01:47 +01:00
|
|
|
|
|
|
|
|
####
|
|
|
|
|
# FP operations
|
|
|
|
|
####
|
|
|
|
|
|
|
|
|
|
&fclass01 r t
|
|
|
|
|
&fclass2 r1 r2 c y
|
|
|
|
|
&fclass3 r1 r2 t
|
|
|
|
|
|
|
|
|
|
@f0c_0 ...... r:5 00000 ..... 00 000 0 t:5 &fclass01
|
|
|
|
|
@f0c_1 ...... r:5 000.. ..... 01 000 0 t:5 &fclass01
|
|
|
|
|
@f0c_2 ...... r1:5 r2:5 y:3 .. 10 000 . c:5 &fclass2
|
|
|
|
|
@f0c_3 ...... r1:5 r2:5 ..... 11 000 0 t:5 &fclass3
|
|
|
|
|
|
|
|
|
|
@f0e_f_0 ...... ..... 00000 ... 0 0 000 .. 0 ..... \
|
|
|
|
|
&fclass01 r=%ra64 t=%rt64
|
|
|
|
|
@f0e_d_0 ...... r:5 00000 ... 0 1 000 00 0 t:5 &fclass01
|
|
|
|
|
|
|
|
|
|
@f0e_ff_1 ...... ..... 000 ... 0000 010 .. 0 ..... \
|
|
|
|
|
&fclass01 r=%ra64 t=%rt64
|
|
|
|
|
@f0e_fd_1 ...... ..... 000 ... 0100 010 .0 0 t:5 &fclass01 r=%ra64
|
|
|
|
|
@f0e_df_1 ...... r:5 000 ... 0001 010 0. 0 ..... &fclass01 t=%rt64
|
|
|
|
|
@f0e_dd_1 ...... r:5 000 ... 0101 010 00 0 t:5 &fclass01
|
|
|
|
|
|
|
|
|
|
@f0e_f_2 ...... ..... ..... y:3 .0 100 .00 c:5 \
|
|
|
|
|
&fclass2 r1=%ra64 r2=%rb64
|
|
|
|
|
@f0e_d_2 ...... r1:5 r2:5 y:3 01 100 000 c:5 &fclass2
|
|
|
|
|
|
|
|
|
|
@f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \
|
|
|
|
|
&fclass3 r1=%ra64 r2=%rb64 t=%rt64
|
|
|
|
|
@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5
|
|
|
|
|
|
|
|
|
|
# Floating point class 0
|
|
|
|
|
|
2022-10-27 19:03:05 +02:00
|
|
|
fid_f 001100 00000 00000 000 00 000000 00000
|
2018-02-13 08:01:47 +01:00
|
|
|
|
|
|
|
|
fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0
|
|
|
|
|
fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0
|
|
|
|
|
fsqrt_f 001100 ..... ..... 100 00 ...... ..... @f0c_0
|
|
|
|
|
frnd_f 001100 ..... ..... 101 00 ...... ..... @f0c_0
|
|
|
|
|
fneg_f 001100 ..... ..... 110 00 ...... ..... @f0c_0
|
|
|
|
|
fnegabs_f 001100 ..... ..... 111 00 ...... ..... @f0c_0
|
|
|
|
|
|
|
|
|
|
fcpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_0
|
|
|
|
|
fabs_d 001100 ..... ..... 011 01 ...... ..... @f0c_0
|
|
|
|
|
fsqrt_d 001100 ..... ..... 100 01 ...... ..... @f0c_0
|
|
|
|
|
frnd_d 001100 ..... ..... 101 01 ...... ..... @f0c_0
|
|
|
|
|
fneg_d 001100 ..... ..... 110 01 ...... ..... @f0c_0
|
|
|
|
|
fnegabs_d 001100 ..... ..... 111 01 ...... ..... @f0c_0
|
|
|
|
|
|
|
|
|
|
fcpy_f 001110 ..... ..... 010 ........ ..... @f0e_f_0
|
|
|
|
|
fabs_f 001110 ..... ..... 011 ........ ..... @f0e_f_0
|
|
|
|
|
fsqrt_f 001110 ..... ..... 100 ........ ..... @f0e_f_0
|
|
|
|
|
frnd_f 001110 ..... ..... 101 ........ ..... @f0e_f_0
|
|
|
|
|
fneg_f 001110 ..... ..... 110 ........ ..... @f0e_f_0
|
|
|
|
|
fnegabs_f 001110 ..... ..... 111 ........ ..... @f0e_f_0
|
|
|
|
|
|
|
|
|
|
fcpy_d 001110 ..... ..... 010 ........ ..... @f0e_d_0
|
|
|
|
|
fabs_d 001110 ..... ..... 011 ........ ..... @f0e_d_0
|
|
|
|
|
fsqrt_d 001110 ..... ..... 100 ........ ..... @f0e_d_0
|
|
|
|
|
frnd_d 001110 ..... ..... 101 ........ ..... @f0e_d_0
|
|
|
|
|
fneg_d 001110 ..... ..... 110 ........ ..... @f0e_d_0
|
|
|
|
|
fnegabs_d 001110 ..... ..... 111 ........ ..... @f0e_d_0
|
|
|
|
|
|
|
|
|
|
# Floating point class 1
|
|
|
|
|
|
|
|
|
|
# float/float
|
|
|
|
|
fcnv_d_f 001100 ..... ... 000 00 01 ...... ..... @f0c_1
|
|
|
|
|
fcnv_f_d 001100 ..... ... 000 01 00 ...... ..... @f0c_1
|
|
|
|
|
|
|
|
|
|
fcnv_d_f 001110 ..... ... 000 .......... ..... @f0e_df_1
|
|
|
|
|
fcnv_f_d 001110 ..... ... 000 .......... ..... @f0e_fd_1
|
|
|
|
|
|
|
|
|
|
# int/float
|
|
|
|
|
fcnv_w_f 001100 ..... ... 001 00 00 ...... ..... @f0c_1
|
|
|
|
|
fcnv_q_f 001100 ..... ... 001 00 01 ...... ..... @f0c_1
|
|
|
|
|
fcnv_w_d 001100 ..... ... 001 01 00 ...... ..... @f0c_1
|
|
|
|
|
fcnv_q_d 001100 ..... ... 001 01 01 ...... ..... @f0c_1
|
|
|
|
|
|
|
|
|
|
fcnv_w_f 001110 ..... ... 001 .......... ..... @f0e_ff_1
|
|
|
|
|
fcnv_q_f 001110 ..... ... 001 .......... ..... @f0e_df_1
|
|
|
|
|
fcnv_w_d 001110 ..... ... 001 .......... ..... @f0e_fd_1
|
|
|
|
|
fcnv_q_d 001110 ..... ... 001 .......... ..... @f0e_dd_1
|
|
|
|
|
|
|
|
|
|
# float/int
|
|
|
|
|
fcnv_f_w 001100 ..... ... 010 00 00 ...... ..... @f0c_1
|
|
|
|
|
fcnv_d_w 001100 ..... ... 010 00 01 ...... ..... @f0c_1
|
|
|
|
|
fcnv_f_q 001100 ..... ... 010 01 00 ...... ..... @f0c_1
|
|
|
|
|
fcnv_d_q 001100 ..... ... 010 01 01 ...... ..... @f0c_1
|
|
|
|
|
|
|
|
|
|
fcnv_f_w 001110 ..... ... 010 .......... ..... @f0e_ff_1
|
|
|
|
|
fcnv_d_w 001110 ..... ... 010 .......... ..... @f0e_df_1
|
|
|
|
|
fcnv_f_q 001110 ..... ... 010 .......... ..... @f0e_fd_1
|
|
|
|
|
fcnv_d_q 001110 ..... ... 010 .......... ..... @f0e_dd_1
|
|
|
|
|
|
|
|
|
|
# float/int truncate
|
|
|
|
|
fcnv_t_f_w 001100 ..... ... 011 00 00 ...... ..... @f0c_1
|
|
|
|
|
fcnv_t_d_w 001100 ..... ... 011 00 01 ...... ..... @f0c_1
|
|
|
|
|
fcnv_t_f_q 001100 ..... ... 011 01 00 ...... ..... @f0c_1
|
|
|
|
|
fcnv_t_d_q 001100 ..... ... 011 01 01 ...... ..... @f0c_1
|
|
|
|
|
|
|
|
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fcnv_t_f_w 001110 ..... ... 011 .......... ..... @f0e_ff_1
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fcnv_t_d_w 001110 ..... ... 011 .......... ..... @f0e_df_1
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fcnv_t_f_q 001110 ..... ... 011 .......... ..... @f0e_fd_1
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fcnv_t_d_q 001110 ..... ... 011 .......... ..... @f0e_dd_1
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# uint/float
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fcnv_uw_f 001100 ..... ... 101 00 00 ...... ..... @f0c_1
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fcnv_uq_f 001100 ..... ... 101 00 01 ...... ..... @f0c_1
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fcnv_uw_d 001100 ..... ... 101 01 00 ...... ..... @f0c_1
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fcnv_uq_d 001100 ..... ... 101 01 01 ...... ..... @f0c_1
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fcnv_uw_f 001110 ..... ... 101 .......... ..... @f0e_ff_1
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fcnv_uq_f 001110 ..... ... 101 .......... ..... @f0e_df_1
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fcnv_uw_d 001110 ..... ... 101 .......... ..... @f0e_fd_1
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fcnv_uq_d 001110 ..... ... 101 .......... ..... @f0e_dd_1
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# float/int
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fcnv_f_uw 001100 ..... ... 110 00 00 ...... ..... @f0c_1
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fcnv_d_uw 001100 ..... ... 110 00 01 ...... ..... @f0c_1
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fcnv_f_uq 001100 ..... ... 110 01 00 ...... ..... @f0c_1
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fcnv_d_uq 001100 ..... ... 110 01 01 ...... ..... @f0c_1
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fcnv_f_uw 001110 ..... ... 110 .......... ..... @f0e_ff_1
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fcnv_d_uw 001110 ..... ... 110 .......... ..... @f0e_df_1
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fcnv_f_uq 001110 ..... ... 110 .......... ..... @f0e_fd_1
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fcnv_d_uq 001110 ..... ... 110 .......... ..... @f0e_dd_1
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# float/int truncate
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fcnv_t_f_uw 001100 ..... ... 111 00 00 ...... ..... @f0c_1
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fcnv_t_d_uw 001100 ..... ... 111 00 01 ...... ..... @f0c_1
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fcnv_t_f_uq 001100 ..... ... 111 01 00 ...... ..... @f0c_1
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fcnv_t_d_uq 001100 ..... ... 111 01 01 ...... ..... @f0c_1
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fcnv_t_f_uw 001110 ..... ... 111 .......... ..... @f0e_ff_1
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fcnv_t_d_uw 001110 ..... ... 111 .......... ..... @f0e_df_1
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fcnv_t_f_uq 001110 ..... ... 111 .......... ..... @f0e_fd_1
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fcnv_t_d_uq 001110 ..... ... 111 .......... ..... @f0e_dd_1
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# Floating point class 2
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ftest 001100 00000 00000 y:3 00 10000 1 c:5
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fcmp_f 001100 ..... ..... ... 00 ..... 0 ..... @f0c_2
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fcmp_d 001100 ..... ..... ... 01 ..... 0 ..... @f0c_2
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fcmp_f 001110 ..... ..... ... ..... ... ..... @f0e_f_2
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fcmp_d 001110 ..... ..... ... ..... ... ..... @f0e_d_2
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# Floating point class 3
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fadd_f 001100 ..... ..... 000 00 ...... ..... @f0c_3
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fsub_f 001100 ..... ..... 001 00 ...... ..... @f0c_3
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fmpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_3
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fdiv_f 001100 ..... ..... 011 00 ...... ..... @f0c_3
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fadd_d 001100 ..... ..... 000 01 ...... ..... @f0c_3
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fsub_d 001100 ..... ..... 001 01 ...... ..... @f0c_3
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fmpy_d 001100 ..... ..... 010 01 ...... ..... @f0c_3
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fdiv_d 001100 ..... ..... 011 01 ...... ..... @f0c_3
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fadd_f 001110 ..... ..... 000 ..... ... ..... @f0e_f_3
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fsub_f 001110 ..... ..... 001 ..... ... ..... @f0e_f_3
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fmpy_f 001110 ..... ..... 010 ..... ... ..... @f0e_f_3
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fdiv_f 001110 ..... ..... 011 ..... ... ..... @f0e_f_3
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fadd_d 001110 ..... ..... 000 ..... ... ..... @f0e_d_3
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fsub_d 001110 ..... ..... 001 ..... ... ..... @f0e_d_3
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fmpy_d 001110 ..... ..... 010 ..... ... ..... @f0e_d_3
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fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3
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xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64
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2019-03-11 20:15:57 +01:00
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# diag
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diag 000101 ----- ----- ---- ---- ---- ----
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