2004-06-06 17:16:19 +02:00
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/*
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* QEMU Cirrus CLGD 54xx VGA Emulator.
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2007-09-16 23:08:06 +02:00
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*
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2004-06-06 17:16:19 +02:00
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* Copyright (c) 2004 Fabrice Bellard
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2007-09-16 23:08:06 +02:00
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*
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2004-06-06 17:16:19 +02:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2017-03-15 11:47:52 +01:00
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static inline void glue(rop_8_, ROP_NAME)(CirrusVGAState *s,
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uint32_t dstaddr, uint8_t src)
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2010-10-13 20:38:07 +02:00
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{
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2017-03-15 11:47:52 +01:00
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uint8_t *dst = &s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask];
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2010-10-13 20:38:07 +02:00
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*dst = ROP_FN(*dst, src);
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}
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2017-03-15 11:47:52 +01:00
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static inline void glue(rop_tr_8_, ROP_NAME)(CirrusVGAState *s,
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uint32_t dstaddr, uint8_t src,
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uint8_t transp)
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2010-10-13 20:38:07 +02:00
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{
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2017-03-15 11:47:52 +01:00
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uint8_t *dst = &s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask];
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uint8_t pixel = ROP_FN(*dst, src);
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if (pixel != transp) {
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*dst = pixel;
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}
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}
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static inline void glue(rop_16_, ROP_NAME)(CirrusVGAState *s,
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uint32_t dstaddr, uint16_t src)
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{
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uint16_t *dst = (uint16_t *)
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(&s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask & ~1]);
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2010-10-13 20:38:07 +02:00
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*dst = ROP_FN(*dst, src);
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}
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2017-03-15 11:47:52 +01:00
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static inline void glue(rop_tr_16_, ROP_NAME)(CirrusVGAState *s,
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uint32_t dstaddr, uint16_t src,
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uint16_t transp)
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{
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uint16_t *dst = (uint16_t *)
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(&s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask & ~1]);
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uint16_t pixel = ROP_FN(*dst, src);
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if (pixel != transp) {
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*dst = pixel;
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}
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}
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static inline void glue(rop_32_, ROP_NAME)(CirrusVGAState *s,
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uint32_t dstaddr, uint32_t src)
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2010-10-13 20:38:07 +02:00
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{
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2017-03-15 11:47:52 +01:00
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uint32_t *dst = (uint32_t *)
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(&s->vga.vram_ptr[dstaddr & s->cirrus_addr_mask & ~3]);
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2010-10-13 20:38:07 +02:00
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*dst = ROP_FN(*dst, src);
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}
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2017-03-15 11:47:52 +01:00
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#define ROP_OP(st, d, s) glue(rop_8_, ROP_NAME)(st, d, s)
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#define ROP_OP_TR(st, d, s, t) glue(rop_tr_8_, ROP_NAME)(st, d, s, t)
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#define ROP_OP_16(st, d, s) glue(rop_16_, ROP_NAME)(st, d, s)
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#define ROP_OP_TR_16(st, d, s, t) glue(rop_tr_16_, ROP_NAME)(st, d, s, t)
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#define ROP_OP_32(st, d, s) glue(rop_32_, ROP_NAME)(st, d, s)
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2010-10-13 20:38:07 +02:00
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#undef ROP_FN
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2004-06-06 17:16:19 +02:00
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static void
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glue(cirrus_bitblt_rop_fwd_, ROP_NAME)(CirrusVGAState *s,
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2017-03-15 11:47:52 +01:00
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uint32_t dstaddr,
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2017-03-15 14:28:07 +01:00
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uint32_t srcaddr,
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2017-03-15 11:47:52 +01:00
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int dstpitch, int srcpitch,
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int bltwidth, int bltheight)
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2004-06-06 17:16:19 +02:00
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{
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int x,y;
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dstpitch -= bltwidth;
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srcpitch -= bltwidth;
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2008-05-05 23:26:31 +02:00
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2014-07-07 02:32:34 +02:00
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if (bltheight > 1 && (dstpitch < 0 || srcpitch < 0)) {
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2008-05-05 23:26:31 +02:00
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return;
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}
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2004-06-06 17:16:19 +02:00
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for (y = 0; y < bltheight; y++) {
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for (x = 0; x < bltwidth; x++) {
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2017-03-15 14:28:07 +01:00
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ROP_OP(s, dstaddr, cirrus_src(s, srcaddr));
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2017-03-15 11:47:52 +01:00
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dstaddr++;
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2017-03-15 14:28:07 +01:00
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srcaddr++;
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2004-06-06 17:16:19 +02:00
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}
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2017-03-15 11:47:52 +01:00
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dstaddr += dstpitch;
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2017-03-15 14:28:07 +01:00
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srcaddr += srcpitch;
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2004-06-06 17:16:19 +02:00
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}
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}
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static void
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glue(cirrus_bitblt_rop_bkwd_, ROP_NAME)(CirrusVGAState *s,
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2017-03-15 11:47:52 +01:00
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uint32_t dstaddr,
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2017-03-15 14:28:07 +01:00
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uint32_t srcaddr,
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2017-03-15 11:47:52 +01:00
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int dstpitch, int srcpitch,
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int bltwidth, int bltheight)
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2004-06-06 17:16:19 +02:00
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{
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int x,y;
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dstpitch += bltwidth;
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srcpitch += bltwidth;
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for (y = 0; y < bltheight; y++) {
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for (x = 0; x < bltwidth; x++) {
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2017-03-15 14:28:07 +01:00
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ROP_OP(s, dstaddr, cirrus_src(s, srcaddr));
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2017-03-15 11:47:52 +01:00
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dstaddr--;
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2017-03-15 14:28:07 +01:00
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srcaddr--;
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2004-06-06 17:16:19 +02:00
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}
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2017-03-15 11:47:52 +01:00
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dstaddr += dstpitch;
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2017-03-15 14:28:07 +01:00
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srcaddr += srcpitch;
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2004-06-06 17:16:19 +02:00
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}
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}
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2007-08-01 01:26:00 +02:00
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static void
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glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_8)(CirrusVGAState *s,
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2017-03-15 11:47:52 +01:00
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uint32_t dstaddr,
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2017-03-15 14:28:07 +01:00
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uint32_t srcaddr,
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2017-03-15 11:47:52 +01:00
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int dstpitch,
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int srcpitch,
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int bltwidth,
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int bltheight)
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2007-08-01 01:26:00 +02:00
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{
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int x,y;
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2017-03-15 11:47:52 +01:00
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uint8_t transp = s->vga.gr[0x34];
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2007-08-01 01:26:00 +02:00
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dstpitch -= bltwidth;
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srcpitch -= bltwidth;
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2017-03-14 07:39:19 +01:00
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if (bltheight > 1 && (dstpitch < 0 || srcpitch < 0)) {
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return;
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}
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2007-08-01 01:26:00 +02:00
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for (y = 0; y < bltheight; y++) {
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for (x = 0; x < bltwidth; x++) {
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2017-03-15 14:28:07 +01:00
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ROP_OP_TR(s, dstaddr, cirrus_src(s, srcaddr), transp);
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2017-03-15 11:47:52 +01:00
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dstaddr++;
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2017-03-15 14:28:07 +01:00
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srcaddr++;
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2007-08-01 01:26:00 +02:00
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}
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2017-03-15 11:47:52 +01:00
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dstaddr += dstpitch;
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2017-03-15 14:28:07 +01:00
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srcaddr += srcpitch;
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2007-08-01 01:26:00 +02:00
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}
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}
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static void
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glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_8)(CirrusVGAState *s,
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2017-03-15 11:47:52 +01:00
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uint32_t dstaddr,
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2017-03-15 14:28:07 +01:00
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uint32_t srcaddr,
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2017-03-15 11:47:52 +01:00
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int dstpitch,
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int srcpitch,
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int bltwidth,
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int bltheight)
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2007-08-01 01:26:00 +02:00
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{
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int x,y;
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2017-03-15 11:47:52 +01:00
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uint8_t transp = s->vga.gr[0x34];
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2007-08-01 01:26:00 +02:00
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dstpitch += bltwidth;
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srcpitch += bltwidth;
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for (y = 0; y < bltheight; y++) {
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for (x = 0; x < bltwidth; x++) {
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2017-03-15 14:28:07 +01:00
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ROP_OP_TR(s, dstaddr, cirrus_src(s, srcaddr), transp);
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2017-03-15 11:47:52 +01:00
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dstaddr--;
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2017-03-15 14:28:07 +01:00
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srcaddr--;
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2007-08-01 01:26:00 +02:00
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}
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2017-03-15 11:47:52 +01:00
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dstaddr += dstpitch;
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2017-03-15 14:28:07 +01:00
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srcaddr += srcpitch;
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2007-08-01 01:26:00 +02:00
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}
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}
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static void
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glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_16)(CirrusVGAState *s,
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2017-03-15 11:47:52 +01:00
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uint32_t dstaddr,
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2017-03-15 14:28:07 +01:00
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uint32_t srcaddr,
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2017-03-15 11:47:52 +01:00
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int dstpitch,
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int srcpitch,
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int bltwidth,
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int bltheight)
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2007-08-01 01:26:00 +02:00
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{
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int x,y;
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2017-03-15 11:47:52 +01:00
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uint16_t transp = s->vga.gr[0x34] | (uint16_t)s->vga.gr[0x35] << 8;
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2007-08-01 01:26:00 +02:00
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dstpitch -= bltwidth;
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srcpitch -= bltwidth;
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2017-03-14 07:39:19 +01:00
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if (bltheight > 1 && (dstpitch < 0 || srcpitch < 0)) {
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return;
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}
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2007-08-01 01:26:00 +02:00
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for (y = 0; y < bltheight; y++) {
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for (x = 0; x < bltwidth; x+=2) {
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2017-03-15 14:28:07 +01:00
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ROP_OP_TR_16(s, dstaddr, cirrus_src16(s, srcaddr), transp);
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2017-03-15 11:47:52 +01:00
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dstaddr += 2;
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2017-03-15 14:28:07 +01:00
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srcaddr += 2;
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2007-08-01 01:26:00 +02:00
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}
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2017-03-15 11:47:52 +01:00
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dstaddr += dstpitch;
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2017-03-15 14:28:07 +01:00
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srcaddr += srcpitch;
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2007-08-01 01:26:00 +02:00
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}
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}
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static void
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glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_16)(CirrusVGAState *s,
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2017-03-15 11:47:52 +01:00
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uint32_t dstaddr,
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2017-03-15 14:28:07 +01:00
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uint32_t srcaddr,
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2017-03-15 11:47:52 +01:00
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int dstpitch,
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int srcpitch,
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int bltwidth,
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int bltheight)
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2007-08-01 01:26:00 +02:00
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{
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int x,y;
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2017-03-15 11:47:52 +01:00
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uint16_t transp = s->vga.gr[0x34] | (uint16_t)s->vga.gr[0x35] << 8;
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2007-08-01 01:26:00 +02:00
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dstpitch += bltwidth;
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srcpitch += bltwidth;
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for (y = 0; y < bltheight; y++) {
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for (x = 0; x < bltwidth; x+=2) {
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2017-03-15 14:28:07 +01:00
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ROP_OP_TR_16(s, dstaddr, cirrus_src16(s, srcaddr), transp);
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2017-03-15 11:47:52 +01:00
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dstaddr -= 2;
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2017-03-15 14:28:07 +01:00
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srcaddr -= 2;
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2007-08-01 01:26:00 +02:00
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}
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2017-03-15 11:47:52 +01:00
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dstaddr += dstpitch;
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2017-03-15 14:28:07 +01:00
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srcaddr += srcpitch;
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2007-08-01 01:26:00 +02:00
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}
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}
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2004-06-06 17:16:19 +02:00
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#define DEPTH 8
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2013-03-18 17:36:02 +01:00
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#include "cirrus_vga_rop2.h"
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2004-06-06 17:16:19 +02:00
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#define DEPTH 16
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2013-03-18 17:36:02 +01:00
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#include "cirrus_vga_rop2.h"
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2004-06-06 17:16:19 +02:00
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#define DEPTH 24
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2013-03-18 17:36:02 +01:00
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#include "cirrus_vga_rop2.h"
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2004-06-06 17:16:19 +02:00
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#define DEPTH 32
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2013-03-18 17:36:02 +01:00
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#include "cirrus_vga_rop2.h"
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2004-06-06 17:16:19 +02:00
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#undef ROP_NAME
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#undef ROP_OP
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2010-10-13 20:38:07 +02:00
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#undef ROP_OP_16
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#undef ROP_OP_32
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