2016-10-22 11:46:35 +02:00
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/*
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* QEMU PowerPC PowerNV various definitions
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*
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* Copyright (c) 2014-2016 BenH, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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2020-10-16 16:53:46 +02:00
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* version 2.1 of the License, or (at your option) any later version.
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2016-10-22 11:46:35 +02:00
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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2019-03-15 15:51:21 +01:00
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#ifndef PPC_PNV_H
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#define PPC_PNV_H
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2016-10-22 11:46:35 +02:00
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#include "hw/boards.h"
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2016-10-22 11:46:36 +02:00
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#include "hw/sysbus.h"
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2017-05-10 08:46:01 +02:00
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#include "hw/ipmi/ipmi.h"
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2016-10-22 11:46:42 +02:00
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#include "hw/ppc/pnv_lpc.h"
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2019-10-21 15:12:11 +02:00
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#include "hw/ppc/pnv_pnor.h"
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2017-04-05 14:41:26 +02:00
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#include "hw/ppc/pnv_psi.h"
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2017-04-05 14:41:27 +02:00
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#include "hw/ppc/pnv_occ.h"
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2019-09-12 11:30:54 +02:00
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#include "hw/ppc/pnv_homer.h"
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2019-03-06 09:50:11 +01:00
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#include "hw/ppc/pnv_xive.h"
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2019-03-07 23:35:44 +01:00
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#include "hw/ppc/pnv_core.h"
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2020-01-27 15:45:06 +01:00
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#include "hw/pci-host/pnv_phb3.h"
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ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
These changes introduces models for the PCIe Host Bridge (PHB4) of the
POWER9 processor. It includes the PowerBus logic interface (PBCQ),
IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI
and LSI interrupt sources as found on a POWER9 system using the XIVE
interrupt controller.
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs. By default,
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Each PEC has a set "global" registers and some "per-stack" (per-PHB)
registers. Those are organized in two XSCOM ranges, the "Nest" range
and the "PCI" range, each range contains both some "PEC" registers and
some "per-stack" registers.
No default device layout is provided and PCI devices can be added on
any of the available PCIe Root Port (pcie.0 .. 2 of a Power9 chip)
with address 0x0 as the firwware (skiboot) only accepts a single
device per root port. To run a simple system with a network and a
storage adapters, use a command line options such as :
-device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
-netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0
-device megasas,id=scsi0,bus=pcie.1,addr=0x0
-drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
-device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2
If more are needed, include a bridge.
Multi chip is supported, each chip adding its set of PHB4 controllers
and its PCI busses. The model doesn't emulate the EEH error handling.
This model is not ready for hotplug yet.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[ clg: - numerous cleanups
- commit log
- fix for broken LSI support
- PHB pic printinfo
- large QOM rework ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200127144506.11132-2-clg@kaod.org>
[dwg: Use device_class_set_props()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-27 15:45:05 +01:00
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#include "hw/pci-host/pnv_phb4.h"
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2020-09-03 22:43:22 +02:00
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#include "qom/object.h"
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2016-10-22 11:46:36 +02:00
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2017-12-15 14:56:01 +01:00
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#define TYPE_PNV_CHIP "pnv-chip"
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2020-08-31 23:07:37 +02:00
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OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass,
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qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros
One of the goals of having less boilerplate on QOM declarations
is to avoid human error. Requiring an extra argument that is
never used is an opportunity for mistakes.
Remove the unused argument from OBJECT_DECLARE_TYPE and
OBJECT_DECLARE_SIMPLE_TYPE.
Coccinelle patch used to convert all users of the macros:
@@
declarer name OBJECT_DECLARE_TYPE;
identifier InstanceType, ClassType, lowercase, UPPERCASE;
@@
OBJECT_DECLARE_TYPE(InstanceType, ClassType,
- lowercase,
UPPERCASE);
@@
declarer name OBJECT_DECLARE_SIMPLE_TYPE;
identifier InstanceType, lowercase, UPPERCASE;
@@
OBJECT_DECLARE_SIMPLE_TYPE(InstanceType,
- lowercase,
UPPERCASE);
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Acked-by: Paul Durrant <paul@xen.org>
Acked-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20200916182519.415636-4-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-16 20:25:17 +02:00
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PNV_CHIP)
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2016-10-22 11:46:36 +02:00
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2020-09-03 22:43:22 +02:00
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struct PnvChip {
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2016-10-22 11:46:36 +02:00
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t chip_id;
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uint64_t ram_start;
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uint64_t ram_size;
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2016-10-22 11:46:37 +02:00
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uint32_t nr_cores;
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2020-01-06 15:56:39 +01:00
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uint32_t nr_threads;
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2016-10-22 11:46:37 +02:00
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uint64_t cores_mask;
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2019-11-25 07:58:03 +01:00
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PnvCore **cores;
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ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 11:46:40 +02:00
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2021-12-17 17:57:19 +01:00
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uint32_t num_pecs;
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ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
These changes introduces models for the PCIe Host Bridge (PHB4) of the
POWER9 processor. It includes the PowerBus logic interface (PBCQ),
IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI
and LSI interrupt sources as found on a POWER9 system using the XIVE
interrupt controller.
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs. By default,
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Each PEC has a set "global" registers and some "per-stack" (per-PHB)
registers. Those are organized in two XSCOM ranges, the "Nest" range
and the "PCI" range, each range contains both some "PEC" registers and
some "per-stack" registers.
No default device layout is provided and PCI devices can be added on
any of the available PCIe Root Port (pcie.0 .. 2 of a Power9 chip)
with address 0x0 as the firwware (skiboot) only accepts a single
device per root port. To run a simple system with a network and a
storage adapters, use a command line options such as :
-device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
-netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0
-device megasas,id=scsi0,bus=pcie.1,addr=0x0
-drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
-device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2
If more are needed, include a bridge.
Multi chip is supported, each chip adding its set of PHB4 controllers
and its PCI busses. The model doesn't emulate the EEH error handling.
This model is not ready for hotplug yet.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[ clg: - numerous cleanups
- commit log
- fix for broken LSI support
- PHB pic printinfo
- large QOM rework ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200127144506.11132-2-clg@kaod.org>
[dwg: Use device_class_set_props()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-27 15:45:05 +01:00
|
|
|
|
ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 11:46:40 +02:00
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MemoryRegion xscom_mmio;
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MemoryRegion xscom;
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AddressSpace xscom_as;
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2019-03-07 23:35:38 +01:00
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2021-01-26 18:10:59 +01:00
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MemoryRegion *fw_mr;
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2019-03-07 23:35:38 +01:00
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gchar *dt_isa_nodename;
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2020-09-03 22:43:22 +02:00
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};
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2018-06-18 19:05:39 +02:00
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#define TYPE_PNV8_CHIP "pnv8-chip"
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2020-09-03 22:43:22 +02:00
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typedef struct Pnv8Chip Pnv8Chip;
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2020-08-31 23:07:33 +02:00
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DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP,
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TYPE_PNV8_CHIP)
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2018-06-18 19:05:39 +02:00
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2020-09-03 22:43:22 +02:00
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struct Pnv8Chip {
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2018-06-18 19:05:39 +02:00
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/*< private >*/
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PnvChip parent_obj;
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/*< public >*/
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2017-04-03 09:46:05 +02:00
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MemoryRegion icp_mmio;
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2016-10-22 11:46:42 +02:00
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PnvLpcController lpc;
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2019-03-07 23:35:34 +01:00
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Pnv8Psi psi;
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2017-04-05 14:41:27 +02:00
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PnvOCC occ;
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2019-09-12 11:30:54 +02:00
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PnvHomer homer;
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2020-01-06 15:56:35 +01:00
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2020-01-27 15:45:06 +01:00
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#define PNV8_CHIP_PHB3_MAX 4
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PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX];
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2022-01-12 11:28:27 +01:00
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uint32_t num_phbs;
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2020-01-27 15:45:06 +01:00
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2020-01-06 15:56:35 +01:00
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XICSFabric *xics;
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2020-09-03 22:43:22 +02:00
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};
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2018-06-18 19:05:39 +02:00
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#define TYPE_PNV9_CHIP "pnv9-chip"
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2020-09-03 22:43:22 +02:00
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typedef struct Pnv9Chip Pnv9Chip;
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2020-08-31 23:07:33 +02:00
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DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP,
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TYPE_PNV9_CHIP)
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2018-06-18 19:05:39 +02:00
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2020-09-03 22:43:22 +02:00
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struct Pnv9Chip {
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2018-06-18 19:05:39 +02:00
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/*< private >*/
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PnvChip parent_obj;
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/*< public >*/
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2019-03-06 09:50:11 +01:00
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PnvXive xive;
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2019-03-07 23:35:35 +01:00
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Pnv9Psi psi;
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2019-03-07 23:35:39 +01:00
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PnvLpcController lpc;
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2019-03-07 23:35:42 +01:00
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PnvOCC occ;
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2019-09-12 11:30:54 +02:00
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PnvHomer homer;
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2019-03-07 23:35:44 +01:00
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uint32_t nr_quads;
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PnvQuad *quads;
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ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
These changes introduces models for the PCIe Host Bridge (PHB4) of the
POWER9 processor. It includes the PowerBus logic interface (PBCQ),
IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI
and LSI interrupt sources as found on a POWER9 system using the XIVE
interrupt controller.
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs. By default,
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Each PEC has a set "global" registers and some "per-stack" (per-PHB)
registers. Those are organized in two XSCOM ranges, the "Nest" range
and the "PCI" range, each range contains both some "PEC" registers and
some "per-stack" registers.
No default device layout is provided and PCI devices can be added on
any of the available PCIe Root Port (pcie.0 .. 2 of a Power9 chip)
with address 0x0 as the firwware (skiboot) only accepts a single
device per root port. To run a simple system with a network and a
storage adapters, use a command line options such as :
-device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0
-netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0
-device megasas,id=scsi0,bus=pcie.1,addr=0x0
-drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none
-device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2
If more are needed, include a bridge.
Multi chip is supported, each chip adding its set of PHB4 controllers
and its PCI busses. The model doesn't emulate the EEH error handling.
This model is not ready for hotplug yet.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[ clg: - numerous cleanups
- commit log
- fix for broken LSI support
- PHB pic printinfo
- large QOM rework ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200127144506.11132-2-clg@kaod.org>
[dwg: Use device_class_set_props()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2020-01-27 15:45:05 +01:00
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#define PNV9_CHIP_MAX_PEC 3
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PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC];
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2020-09-03 22:43:22 +02:00
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};
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2016-10-22 11:46:36 +02:00
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2019-11-25 07:58:06 +01:00
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/*
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* A SMT8 fused core is a pair of SMT4 cores.
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*/
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#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
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2019-11-25 07:58:13 +01:00
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#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
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2019-11-25 07:58:06 +01:00
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2019-12-05 19:44:51 +01:00
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#define TYPE_PNV10_CHIP "pnv10-chip"
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2020-09-03 22:43:22 +02:00
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typedef struct Pnv10Chip Pnv10Chip;
|
2020-08-31 23:07:33 +02:00
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DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP,
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TYPE_PNV10_CHIP)
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2019-12-05 19:44:51 +01:00
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2020-09-03 22:43:22 +02:00
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struct Pnv10Chip {
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2019-12-05 19:44:51 +01:00
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/*< private >*/
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PnvChip parent_obj;
|
2019-12-05 19:44:53 +01:00
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/*< public >*/
|
ppc/pnv: Add a XIVE2 controller to the POWER10 chip
The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE2 structures, and a set of new features
which are described below.
This is a model of the POWER10 XIVE2 interrupt controller for the
PowerNV machine. It focuses primarily on the needs of the skiboot
firmware but some initial hypervisor support is implemented for KVM
use (escalation).
Support for new features will be implemented in time and will require
new support from the OS.
* XIVE2 BARS
The interrupt controller BARs have a different layout outlined below.
Each sub-engine has now own its range and the indirect TIMA access was
replaced with a set of pages, one per CPU, under the IC BAR:
- IC BAR (Interrupt Controller)
. 4 pages, one per sub-engine
. 128 indirect TIMA pages
- TM BAR (Thread Interrupt Management Area)
. 4 pages
- ESB BAR (ESB pages for IPIs)
. up to 1TB
- END BAR (ESB pages for ENDs)
. up to 2TB
- NVC BAR (Notification Virtual Crowd)
. up to 128
- NVPG BAR (Notification Virtual Process and Group)
. up to 1TB
- Direct mapped Thread Context Area (reads & writes)
OPAL does not use the grouping and crowd capability.
* Virtual Structure Tables
XIVE2 adds new tables types and also changes the field layout of the END
and NVP Virtualization Structure Descriptors.
- EAS
- END new layout
- NVT was splitted in :
. NVP (Processor), 32B
. NVG (Group), 32B
. NVC (Crowd == P9 block group) 32B
- IC for remote configuration
- SYNC for cache injection
- ERQ for event input queue
The setup is slighly different on XIVE2 because the indexing has changed
for some of the tables, block ID or the chip topology ID can be used.
* XIVE2 features
SCOM and MMIO registers have a new layout and XIVE2 adds a new global
capability and configuration registers.
The lowlevel hardware offers a set of new features among which :
- a configurable number of priorities : 1 - 8
- StoreEOI with load-after-store ordering is activated by default
- Gen2 TIMA layout
- A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility
- increase to 24bit for VP number
Other features will have some impact on the Hypervisor and guest OS
when activated, but this is not required for initial support of the
controller.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02 06:51:38 +01:00
|
|
|
PnvXive2 xive;
|
2019-12-05 19:44:53 +01:00
|
|
|
Pnv9Psi psi;
|
2019-12-05 19:44:54 +01:00
|
|
|
PnvLpcController lpc;
|
2022-03-02 06:51:39 +01:00
|
|
|
PnvOCC occ;
|
2022-03-02 06:51:39 +01:00
|
|
|
PnvHomer homer;
|
2022-03-02 06:51:39 +01:00
|
|
|
|
|
|
|
|
uint32_t nr_quads;
|
|
|
|
|
PnvQuad *quads;
|
2022-03-02 06:51:39 +01:00
|
|
|
|
|
|
|
|
#define PNV10_CHIP_MAX_PEC 2
|
|
|
|
|
PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2019-12-05 19:44:51 +01:00
|
|
|
|
ppc/pnv: Add a XIVE2 controller to the POWER10 chip
The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE2 structures, and a set of new features
which are described below.
This is a model of the POWER10 XIVE2 interrupt controller for the
PowerNV machine. It focuses primarily on the needs of the skiboot
firmware but some initial hypervisor support is implemented for KVM
use (escalation).
Support for new features will be implemented in time and will require
new support from the OS.
* XIVE2 BARS
The interrupt controller BARs have a different layout outlined below.
Each sub-engine has now own its range and the indirect TIMA access was
replaced with a set of pages, one per CPU, under the IC BAR:
- IC BAR (Interrupt Controller)
. 4 pages, one per sub-engine
. 128 indirect TIMA pages
- TM BAR (Thread Interrupt Management Area)
. 4 pages
- ESB BAR (ESB pages for IPIs)
. up to 1TB
- END BAR (ESB pages for ENDs)
. up to 2TB
- NVC BAR (Notification Virtual Crowd)
. up to 128
- NVPG BAR (Notification Virtual Process and Group)
. up to 1TB
- Direct mapped Thread Context Area (reads & writes)
OPAL does not use the grouping and crowd capability.
* Virtual Structure Tables
XIVE2 adds new tables types and also changes the field layout of the END
and NVP Virtualization Structure Descriptors.
- EAS
- END new layout
- NVT was splitted in :
. NVP (Processor), 32B
. NVG (Group), 32B
. NVC (Crowd == P9 block group) 32B
- IC for remote configuration
- SYNC for cache injection
- ERQ for event input queue
The setup is slighly different on XIVE2 because the indexing has changed
for some of the tables, block ID or the chip topology ID can be used.
* XIVE2 features
SCOM and MMIO registers have a new layout and XIVE2 adds a new global
capability and configuration registers.
The lowlevel hardware offers a set of new features among which :
- a configurable number of priorities : 1 - 8
- StoreEOI with load-after-store ordering is activated by default
- Gen2 TIMA layout
- A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility
- increase to 24bit for VP number
Other features will have some impact on the Hypervisor and guest OS
when activated, but this is not required for initial support of the
controller.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02 06:51:38 +01:00
|
|
|
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
|
|
|
|
|
#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
|
|
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
struct PnvChipClass {
|
2016-10-22 11:46:36 +02:00
|
|
|
/*< private >*/
|
|
|
|
|
SysBusDeviceClass parent_class;
|
|
|
|
|
|
|
|
|
|
/*< public >*/
|
|
|
|
|
uint64_t chip_cfam_id;
|
2016-10-22 11:46:37 +02:00
|
|
|
uint64_t cores_mask;
|
2021-12-17 17:57:19 +01:00
|
|
|
uint32_t num_pecs;
|
2022-01-12 11:28:27 +01:00
|
|
|
uint32_t num_phbs;
|
2016-10-22 11:46:38 +02:00
|
|
|
|
2018-06-18 19:05:39 +02:00
|
|
|
DeviceRealize parent_realize;
|
|
|
|
|
|
2016-10-22 11:46:38 +02:00
|
|
|
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
|
2019-01-02 06:57:34 +01:00
|
|
|
void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp);
|
2019-10-22 18:38:10 +02:00
|
|
|
void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu);
|
2019-10-24 16:27:22 +02:00
|
|
|
void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu);
|
2019-12-13 13:00:07 +01:00
|
|
|
void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon);
|
2018-06-15 17:25:34 +02:00
|
|
|
ISABus *(*isa_create)(PnvChip *chip, Error **errp);
|
2019-03-06 09:50:12 +01:00
|
|
|
void (*dt_populate)(PnvChip *chip, void *fdt);
|
2019-03-06 09:50:13 +01:00
|
|
|
void (*pic_print_info)(PnvChip *chip, Monitor *mon);
|
2019-12-13 13:00:13 +01:00
|
|
|
uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id);
|
2019-12-13 13:00:35 +01:00
|
|
|
uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr);
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2016-10-22 11:46:36 +02:00
|
|
|
|
2017-10-09 21:51:07 +02:00
|
|
|
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
|
|
|
|
|
#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
|
|
|
|
|
|
|
|
|
|
#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
|
2020-08-31 23:07:33 +02:00
|
|
|
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
|
|
|
|
|
TYPE_PNV_CHIP_POWER8E)
|
2016-10-22 11:46:36 +02:00
|
|
|
|
2017-10-09 21:51:07 +02:00
|
|
|
#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
|
2020-08-31 23:07:33 +02:00
|
|
|
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
|
|
|
|
|
TYPE_PNV_CHIP_POWER8)
|
2016-10-22 11:46:36 +02:00
|
|
|
|
2017-10-09 21:51:07 +02:00
|
|
|
#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
|
2020-08-31 23:07:33 +02:00
|
|
|
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
|
|
|
|
|
TYPE_PNV_CHIP_POWER8NVL)
|
2016-10-22 11:46:36 +02:00
|
|
|
|
2017-10-09 21:51:07 +02:00
|
|
|
#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
|
2020-08-31 23:07:33 +02:00
|
|
|
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
|
|
|
|
|
TYPE_PNV_CHIP_POWER9)
|
2016-10-22 11:46:36 +02:00
|
|
|
|
2021-08-09 15:45:23 +02:00
|
|
|
#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
|
2020-08-31 23:07:33 +02:00
|
|
|
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
|
|
|
|
|
TYPE_PNV_CHIP_POWER10)
|
2019-12-05 19:44:51 +01:00
|
|
|
|
2019-11-25 07:58:07 +01:00
|
|
|
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
|
2022-01-12 11:28:27 +01:00
|
|
|
void pnv_phb_attach_root_port(PCIHostState *pci, const char *name);
|
2022-01-12 11:28:27 +01:00
|
|
|
void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index);
|
2019-11-25 07:58:07 +01:00
|
|
|
|
2017-12-15 14:56:01 +01:00
|
|
|
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
|
2020-09-03 22:43:22 +02:00
|
|
|
typedef struct PnvMachineClass PnvMachineClass;
|
|
|
|
|
typedef struct PnvMachineState PnvMachineState;
|
2020-08-31 23:07:33 +02:00
|
|
|
DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
|
|
|
|
|
PNV_MACHINE, TYPE_PNV_MACHINE)
|
2019-12-13 12:59:50 +01:00
|
|
|
|
2019-12-13 12:59:56 +01:00
|
|
|
|
2020-09-03 22:43:22 +02:00
|
|
|
struct PnvMachineClass {
|
2019-12-13 12:59:50 +01:00
|
|
|
/*< private >*/
|
|
|
|
|
MachineClass parent_class;
|
|
|
|
|
|
|
|
|
|
/*< public >*/
|
|
|
|
|
const char *compat;
|
|
|
|
|
int compat_size;
|
2019-12-13 12:59:56 +01:00
|
|
|
|
|
|
|
|
void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
|
2020-09-03 22:43:22 +02:00
|
|
|
};
|
2016-10-22 11:46:35 +02:00
|
|
|
|
2019-12-13 12:59:56 +01:00
|
|
|
struct PnvMachineState {
|
2016-10-22 11:46:35 +02:00
|
|
|
/*< private >*/
|
|
|
|
|
MachineState parent_obj;
|
|
|
|
|
|
|
|
|
|
uint32_t initrd_base;
|
|
|
|
|
long initrd_size;
|
2016-10-22 11:46:36 +02:00
|
|
|
|
|
|
|
|
uint32_t num_chips;
|
|
|
|
|
PnvChip **chips;
|
2016-10-22 11:46:43 +02:00
|
|
|
|
|
|
|
|
ISABus *isa_bus;
|
2017-04-05 14:41:26 +02:00
|
|
|
uint32_t cpld_irqstate;
|
2017-04-11 17:30:05 +02:00
|
|
|
|
|
|
|
|
IPMIBmc *bmc;
|
2017-04-11 17:30:06 +02:00
|
|
|
Notifier powerdown_notifier;
|
2019-10-21 15:12:11 +02:00
|
|
|
|
|
|
|
|
PnvPnor *pnor;
|
2020-01-27 15:41:54 +01:00
|
|
|
|
|
|
|
|
hwaddr fw_load_addr;
|
2019-12-13 12:59:56 +01:00
|
|
|
};
|
2016-10-22 11:46:35 +02:00
|
|
|
|
2022-01-12 11:28:27 +01:00
|
|
|
PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
|
|
|
|
|
|
2016-10-22 11:46:35 +02:00
|
|
|
#define PNV_FDT_ADDR 0x01000000
|
2016-10-22 11:46:39 +02:00
|
|
|
#define PNV_TIMEBASE_FREQ 512000000ULL
|
2016-10-22 11:46:35 +02:00
|
|
|
|
2017-04-11 17:30:05 +02:00
|
|
|
/*
|
|
|
|
|
* BMC helpers
|
|
|
|
|
*/
|
2017-12-15 14:56:01 +01:00
|
|
|
void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
|
2017-04-11 17:30:06 +02:00
|
|
|
void pnv_bmc_powerdown(IPMIBmc *bmc);
|
2020-01-06 15:56:40 +01:00
|
|
|
IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
|
2020-04-04 17:36:55 +02:00
|
|
|
IPMIBmc *pnv_bmc_find(Error **errp);
|
|
|
|
|
void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
|
2017-04-11 17:30:05 +02:00
|
|
|
|
ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 11:46:40 +02:00
|
|
|
/*
|
|
|
|
|
* POWER8 MMIO base addresses
|
|
|
|
|
*/
|
|
|
|
|
#define PNV_XSCOM_SIZE 0x800000000ull
|
|
|
|
|
#define PNV_XSCOM_BASE(chip) \
|
2019-06-12 19:43:45 +02:00
|
|
|
(0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
|
ppc/pnv: add XSCOM infrastructure
On a real POWER8 system, the Pervasive Interconnect Bus (PIB) serves
as a backbone to connect different units of the system. The host
firmware connects to the PIB through a bridge unit, the
Alter-Display-Unit (ADU), which gives him access to all the chiplets
on the PCB network (Pervasive Connect Bus), the PIB acting as the root
of this network.
XSCOM (serial communication) is the interface to the sideband bus
provided by the POWER8 pervasive unit to read and write to chiplets
resources. This is needed by the host firmware, OPAL and to a lesser
extent, Linux. This is among others how the PCI Host bridges get
configured at boot or how the LPC bus is accessed.
To represent the ADU of a real system, we introduce a specific
AddressSpace to dispatch XSCOM accesses to the targeted chiplets. The
translation of an XSCOM address into a PCB register address is
slightly different between the P9 and the P8. This is handled before
the dispatch using a 8byte alignment for all.
To customize the device tree, a QOM InterfaceClass, PnvXScomInterface,
is provided with a populate() handler. The chip populates the device
tree by simply looping on its children. Therefore, each model needing
custom nodes should not forget to declare itself as a child at
instantiation time.
Based on previous work done by :
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[dwg: Added cpu parameter to xscom_complete()]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-22 11:46:40 +02:00
|
|
|
|
2019-12-11 09:29:11 +01:00
|
|
|
#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
|
|
|
|
|
#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
|
2019-12-11 09:29:12 +01:00
|
|
|
#define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
|
2021-08-09 15:45:25 +02:00
|
|
|
PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
|
2019-09-12 11:30:52 +02:00
|
|
|
|
2019-12-11 09:29:11 +01:00
|
|
|
#define PNV_HOMER_SIZE 0x0000000000400000ull
|
2019-09-12 11:30:52 +02:00
|
|
|
#define PNV_HOMER_BASE(chip) \
|
2021-08-09 15:45:25 +02:00
|
|
|
(0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
|
2019-09-12 11:30:52 +02:00
|
|
|
|
|
|
|
|
|
2017-04-03 09:46:05 +02:00
|
|
|
/*
|
|
|
|
|
* XSCOM 0x20109CA defines the ICP BAR:
|
|
|
|
|
*
|
|
|
|
|
* 0:29 : bits 14 to 43 of address to define 1 MB region.
|
|
|
|
|
* 30 : 1 to enable ICP to receive loads/stores against its BAR region
|
|
|
|
|
* 31:63 : Constant 0
|
|
|
|
|
*
|
|
|
|
|
* Usually defined as :
|
|
|
|
|
*
|
|
|
|
|
* 0xffffe00200000000 -> 0x0003ffff80000000
|
|
|
|
|
* 0xffffe00600000000 -> 0x0003ffff80100000
|
|
|
|
|
* 0xffffe02200000000 -> 0x0003ffff80800000
|
|
|
|
|
* 0xffffe02600000000 -> 0x0003ffff80900000
|
|
|
|
|
*/
|
|
|
|
|
#define PNV_ICP_SIZE 0x0000000000100000ull
|
|
|
|
|
#define PNV_ICP_BASE(chip) \
|
2021-08-09 15:45:25 +02:00
|
|
|
(0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
|
2017-04-03 09:46:05 +02:00
|
|
|
|
2017-04-05 14:41:26 +02:00
|
|
|
|
|
|
|
|
#define PNV_PSIHB_SIZE 0x0000000000100000ull
|
|
|
|
|
#define PNV_PSIHB_BASE(chip) \
|
2021-08-09 15:45:25 +02:00
|
|
|
(0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
|
2017-04-05 14:41:26 +02:00
|
|
|
|
|
|
|
|
#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
|
|
|
|
|
#define PNV_PSIHB_FSP_BASE(chip) \
|
2021-08-09 15:45:25 +02:00
|
|
|
(0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
|
2017-04-05 14:41:26 +02:00
|
|
|
PNV_PSIHB_FSP_SIZE)
|
|
|
|
|
|
2019-03-06 09:50:11 +01:00
|
|
|
/*
|
|
|
|
|
* POWER9 MMIO base addresses
|
|
|
|
|
*/
|
|
|
|
|
#define PNV9_CHIP_BASE(chip, base) \
|
|
|
|
|
((base) + ((uint64_t) (chip)->chip_id << 42))
|
|
|
|
|
|
|
|
|
|
#define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
|
|
|
|
|
#define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
|
|
|
|
|
|
|
|
|
|
#define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
|
|
|
|
|
#define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
|
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2019-03-07 23:35:39 +01:00
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#define PNV9_LPCM_SIZE 0x0000000100000000ull
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#define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
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2019-03-07 23:35:35 +01:00
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#define PNV9_PSIHB_SIZE 0x0000000000100000ull
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#define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
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2019-03-06 09:50:11 +01:00
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#define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
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#define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
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#define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
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#define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
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2019-03-07 23:35:35 +01:00
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#define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
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#define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
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2019-03-06 09:50:11 +01:00
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2019-06-12 19:43:44 +02:00
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#define PNV9_XSCOM_SIZE 0x0000000400000000ull
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#define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
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2019-12-11 09:29:11 +01:00
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#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
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2019-12-11 09:29:12 +01:00
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#define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
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2021-08-09 15:45:25 +02:00
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PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
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2019-09-12 11:30:52 +02:00
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2019-12-11 09:29:11 +01:00
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#define PNV9_HOMER_SIZE 0x0000000000400000ull
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2019-09-12 11:30:52 +02:00
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#define PNV9_HOMER_BASE(chip) \
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2021-08-09 15:45:25 +02:00
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(0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
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2019-12-05 19:44:51 +01:00
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/*
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* POWER10 MMIO base addresses - 16TB stride per chip
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*/
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#define PNV10_CHIP_BASE(chip, base) \
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((base) + ((uint64_t) (chip)->chip_id << 44))
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#define PNV10_XSCOM_SIZE 0x0000000400000000ull
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#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
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2019-12-05 19:44:54 +01:00
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#define PNV10_LPCM_SIZE 0x0000000100000000ull
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#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
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ppc/pnv: Add a XIVE2 controller to the POWER10 chip
The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE2 structures, and a set of new features
which are described below.
This is a model of the POWER10 XIVE2 interrupt controller for the
PowerNV machine. It focuses primarily on the needs of the skiboot
firmware but some initial hypervisor support is implemented for KVM
use (escalation).
Support for new features will be implemented in time and will require
new support from the OS.
* XIVE2 BARS
The interrupt controller BARs have a different layout outlined below.
Each sub-engine has now own its range and the indirect TIMA access was
replaced with a set of pages, one per CPU, under the IC BAR:
- IC BAR (Interrupt Controller)
. 4 pages, one per sub-engine
. 128 indirect TIMA pages
- TM BAR (Thread Interrupt Management Area)
. 4 pages
- ESB BAR (ESB pages for IPIs)
. up to 1TB
- END BAR (ESB pages for ENDs)
. up to 2TB
- NVC BAR (Notification Virtual Crowd)
. up to 128
- NVPG BAR (Notification Virtual Process and Group)
. up to 1TB
- Direct mapped Thread Context Area (reads & writes)
OPAL does not use the grouping and crowd capability.
* Virtual Structure Tables
XIVE2 adds new tables types and also changes the field layout of the END
and NVP Virtualization Structure Descriptors.
- EAS
- END new layout
- NVT was splitted in :
. NVP (Processor), 32B
. NVG (Group), 32B
. NVC (Crowd == P9 block group) 32B
- IC for remote configuration
- SYNC for cache injection
- ERQ for event input queue
The setup is slighly different on XIVE2 because the indexing has changed
for some of the tables, block ID or the chip topology ID can be used.
* XIVE2 features
SCOM and MMIO registers have a new layout and XIVE2 adds a new global
capability and configuration registers.
The lowlevel hardware offers a set of new features among which :
- a configurable number of priorities : 1 - 8
- StoreEOI with load-after-store ordering is activated by default
- Gen2 TIMA layout
- A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility
- increase to 24bit for VP number
Other features will have some impact on the Hypervisor and guest OS
when activated, but this is not required for initial support of the
controller.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02 06:51:38 +01:00
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#define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull
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#define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
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2019-12-05 19:44:53 +01:00
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#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
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#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
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#define PNV10_PSIHB_SIZE 0x0000000000100000ull
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#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
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ppc/pnv: Add a XIVE2 controller to the POWER10 chip
The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE2 structures, and a set of new features
which are described below.
This is a model of the POWER10 XIVE2 interrupt controller for the
PowerNV machine. It focuses primarily on the needs of the skiboot
firmware but some initial hypervisor support is implemented for KVM
use (escalation).
Support for new features will be implemented in time and will require
new support from the OS.
* XIVE2 BARS
The interrupt controller BARs have a different layout outlined below.
Each sub-engine has now own its range and the indirect TIMA access was
replaced with a set of pages, one per CPU, under the IC BAR:
- IC BAR (Interrupt Controller)
. 4 pages, one per sub-engine
. 128 indirect TIMA pages
- TM BAR (Thread Interrupt Management Area)
. 4 pages
- ESB BAR (ESB pages for IPIs)
. up to 1TB
- END BAR (ESB pages for ENDs)
. up to 2TB
- NVC BAR (Notification Virtual Crowd)
. up to 128
- NVPG BAR (Notification Virtual Process and Group)
. up to 1TB
- Direct mapped Thread Context Area (reads & writes)
OPAL does not use the grouping and crowd capability.
* Virtual Structure Tables
XIVE2 adds new tables types and also changes the field layout of the END
and NVP Virtualization Structure Descriptors.
- EAS
- END new layout
- NVT was splitted in :
. NVP (Processor), 32B
. NVG (Group), 32B
. NVC (Crowd == P9 block group) 32B
- IC for remote configuration
- SYNC for cache injection
- ERQ for event input queue
The setup is slighly different on XIVE2 because the indexing has changed
for some of the tables, block ID or the chip topology ID can be used.
* XIVE2 features
SCOM and MMIO registers have a new layout and XIVE2 adds a new global
capability and configuration registers.
The lowlevel hardware offers a set of new features among which :
- a configurable number of priorities : 1 - 8
- StoreEOI with load-after-store ordering is activated by default
- Gen2 TIMA layout
- A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility
- increase to 24bit for VP number
Other features will have some impact on the Hypervisor and guest OS
when activated, but this is not required for initial support of the
controller.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-03-02 06:51:38 +01:00
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#define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull
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#define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
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#define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull
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#define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
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#define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull
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#define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
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#define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull
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#define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
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#define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
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#define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
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2022-03-02 06:51:39 +01:00
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#define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull
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#define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \
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PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
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#define PNV10_HOMER_SIZE 0x0000000000400000ull
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#define PNV10_HOMER_BASE(chip) \
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(0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
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2019-03-15 15:51:21 +01:00
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#endif /* PPC_PNV_H */
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