2020-10-06 09:05:29 +02:00
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/*
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* Target-specific parts of the CPU object
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "exec/target_page.h"
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#include "hw/qdev-core.h"
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#include "hw/qdev-properties.h"
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#include "qemu/error-report.h"
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#include "migration/vmstate.h"
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#ifdef CONFIG_USER_ONLY
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#include "qemu.h"
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#else
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2021-05-17 12:51:31 +02:00
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#include "hw/core/sysemu-cpu-ops.h"
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2020-10-06 09:05:29 +02:00
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#include "exec/address-spaces.h"
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#endif
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2023-03-03 03:58:05 +01:00
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#include "sysemu/cpus.h"
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2020-10-06 09:05:29 +02:00
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#include "sysemu/tcg.h"
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2022-12-19 18:09:43 +01:00
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#include "exec/replay-core.h"
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2022-03-14 15:01:08 +01:00
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#include "exec/cpu-common.h"
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2022-02-07 15:28:56 +01:00
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#include "exec/exec-all.h"
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2023-03-03 03:57:43 +01:00
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#include "exec/tb-flush.h"
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2020-12-16 13:27:58 +01:00
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#include "exec/translate-all.h"
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2020-10-06 09:05:29 +02:00
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#include "exec/log.h"
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2021-03-22 14:27:41 +01:00
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#include "hw/core/accel-cpu.h"
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2021-07-01 17:10:53 +02:00
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#include "trace/trace-root.h"
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2022-02-07 15:28:56 +01:00
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#include "qemu/accel.h"
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2023-03-15 18:43:14 +01:00
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#include "qemu/plugin.h"
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2020-10-06 09:05:29 +02:00
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uintptr_t qemu_host_page_size;
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intptr_t qemu_host_page_mask;
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#ifndef CONFIG_USER_ONLY
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static int cpu_common_post_load(void *opaque, int version_id)
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{
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CPUState *cpu = opaque;
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/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
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version_id is increased. */
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cpu->interrupt_request &= ~0x01;
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tlb_flush(cpu);
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/* loadvm has just updated the content of RAM, bypassing the
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* usual mechanisms that ensure we flush TBs for writes to
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* memory we've translated code from. So we must flush all TBs,
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* which will now be stale.
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*/
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tb_flush(cpu);
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return 0;
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}
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static int cpu_common_pre_load(void *opaque)
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{
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CPUState *cpu = opaque;
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cpu->exception_index = -1;
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return 0;
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}
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static bool cpu_common_exception_index_needed(void *opaque)
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{
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CPUState *cpu = opaque;
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return tcg_enabled() && cpu->exception_index != -1;
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}
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static const VMStateDescription vmstate_cpu_common_exception_index = {
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.name = "cpu_common/exception_index",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = cpu_common_exception_index_needed,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(exception_index, CPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool cpu_common_crash_occurred_needed(void *opaque)
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{
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CPUState *cpu = opaque;
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return cpu->crash_occurred;
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}
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static const VMStateDescription vmstate_cpu_common_crash_occurred = {
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.name = "cpu_common/crash_occurred",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = cpu_common_crash_occurred_needed,
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.fields = (VMStateField[]) {
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VMSTATE_BOOL(crash_occurred, CPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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const VMStateDescription vmstate_cpu_common = {
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.name = "cpu_common",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_load = cpu_common_pre_load,
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.post_load = cpu_common_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(halted, CPUState),
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VMSTATE_UINT32(interrupt_request, CPUState),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_cpu_common_exception_index,
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&vmstate_cpu_common_crash_occurred,
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NULL
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}
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};
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#endif
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2021-02-04 17:39:11 +01:00
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void cpu_exec_realizefn(CPUState *cpu, Error **errp)
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2020-10-06 09:05:29 +02:00
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{
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2022-09-23 10:47:59 +02:00
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/* cache the cpu class for the hotpath */
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cpu->cc = CPU_GET_CLASS(cpu);
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2020-10-06 09:05:29 +02:00
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2023-10-03 14:30:21 +02:00
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if (!accel_cpu_common_realize(cpu, errp)) {
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2021-03-22 14:27:44 +01:00
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return;
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}
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2022-10-31 03:26:36 +01:00
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/* Wait until cpu initialization complete before exposing cpu. */
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cpu_list_add(cpu);
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/* Plugin initialization must wait until cpu_index assigned. */
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if (tcg_enabled()) {
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qemu_plugin_vcpu_init_hook(cpu);
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}
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2021-02-04 17:39:11 +01:00
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#ifdef CONFIG_USER_ONLY
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2021-05-17 12:51:28 +02:00
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assert(qdev_get_vmsd(DEVICE(cpu)) == NULL ||
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qdev_get_vmsd(DEVICE(cpu))->unmigratable);
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2021-02-04 17:39:11 +01:00
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#else
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if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
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vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
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}
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2022-09-23 10:47:59 +02:00
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if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
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vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
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2021-02-04 17:39:11 +01:00
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}
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#endif /* CONFIG_USER_ONLY */
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}
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void cpu_exec_unrealizefn(CPUState *cpu)
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{
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2021-05-17 12:51:32 +02:00
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#ifndef CONFIG_USER_ONLY
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2021-02-04 17:39:11 +01:00
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CPUClass *cc = CPU_GET_CLASS(cpu);
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2020-10-06 09:05:29 +02:00
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2021-05-17 12:51:32 +02:00
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if (cc->sysemu_ops->legacy_vmsd != NULL) {
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vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu);
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2020-10-06 09:05:29 +02:00
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}
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if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
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vmstate_unregister(NULL, &vmstate_cpu_common, cpu);
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}
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#endif
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2023-01-24 19:01:18 +01:00
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/* Call the plugin hook before clearing cpu->cpu_index in cpu_list_remove */
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2021-02-04 17:39:11 +01:00
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if (tcg_enabled()) {
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2023-01-24 19:01:18 +01:00
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qemu_plugin_vcpu_exit_hook(cpu);
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2021-02-04 17:39:11 +01:00
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}
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cpu_list_remove(cpu);
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2023-01-24 19:01:18 +01:00
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/*
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* Now that the vCPU has been removed from the RCU list, we can call
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2023-10-03 14:30:22 +02:00
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* accel_cpu_common_unrealize, which may free fields using call_rcu.
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2023-01-24 19:01:18 +01:00
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*/
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2023-10-03 14:30:22 +02:00
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accel_cpu_common_unrealize(cpu);
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2020-10-06 09:05:29 +02:00
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}
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2021-12-27 16:01:24 +01:00
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/*
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* This can't go in hw/core/cpu.c because that file is compiled only
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* once for both user-mode and system builds.
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*/
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2021-08-22 09:25:28 +02:00
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static Property cpu_common_props[] = {
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2021-12-27 16:01:24 +01:00
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#ifdef CONFIG_USER_ONLY
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/*
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* Create a property for the user-only object, so users can
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* adjust prctl(PR_SET_UNALIGN) from the command-line.
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* Has no effect if the target does not support the feature.
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*/
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DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
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prctl_unalign_sigbus, false),
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#else
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2021-08-22 09:25:28 +02:00
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/*
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2023-10-04 11:06:18 +02:00
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* Create a memory property for system CPU object, so users can
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2021-12-27 16:01:24 +01:00
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* wire up its memory. The default if no link is set up is to use
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2021-08-22 09:25:28 +02:00
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* the system address space.
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*/
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DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
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MemoryRegion *),
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#endif
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DEFINE_PROP_END_OF_LIST(),
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};
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2022-01-27 16:46:25 +01:00
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static bool cpu_get_start_powered_off(Object *obj, Error **errp)
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{
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CPUState *cpu = CPU(obj);
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return cpu->start_powered_off;
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}
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static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp)
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{
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CPUState *cpu = CPU(obj);
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cpu->start_powered_off = value;
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}
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2021-08-22 09:25:28 +02:00
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void cpu_class_init_props(DeviceClass *dc)
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{
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2022-01-27 16:46:25 +01:00
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ObjectClass *oc = OBJECT_CLASS(dc);
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2021-08-22 09:25:28 +02:00
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device_class_set_props(dc, cpu_common_props);
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2022-01-27 16:46:25 +01:00
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/*
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* We can't use DEFINE_PROP_BOOL in the Property array for this
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* property, because we want this to be settable after realize.
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*/
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object_class_property_add_bool(oc, "start-powered-off",
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cpu_get_start_powered_off,
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cpu_set_start_powered_off);
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2021-08-22 09:25:28 +02:00
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}
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2020-10-06 09:05:29 +02:00
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void cpu_exec_initfn(CPUState *cpu)
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{
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cpu->as = NULL;
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cpu->num_ases = 0;
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#ifndef CONFIG_USER_ONLY
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cpu->thread_id = qemu_get_thread_id();
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cpu->memory = get_system_memory();
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object_ref(OBJECT(cpu->memory));
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#endif
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}
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const char *parse_cpu_option(const char *cpu_option)
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{
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ObjectClass *oc;
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CPUClass *cc;
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gchar **model_pieces;
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const char *cpu_type;
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model_pieces = g_strsplit(cpu_option, ",", 2);
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if (!model_pieces[0]) {
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error_report("-cpu option cannot be empty");
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exit(1);
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}
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oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
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if (oc == NULL) {
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error_report("unable to find CPU model '%s'", model_pieces[0]);
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g_strfreev(model_pieces);
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exit(EXIT_FAILURE);
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}
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cpu_type = object_class_get_name(oc);
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cc = CPU_CLASS(oc);
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cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
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g_strfreev(model_pieces);
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return cpu_type;
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}
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2023-04-19 14:48:31 +02:00
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void list_cpus(void)
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2022-03-14 15:01:08 +01:00
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{
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/* XXX: implement xxx_cpu_list for targets that still miss it */
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#if defined(cpu_list)
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cpu_list();
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#endif
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}
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2020-10-06 09:05:29 +02:00
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#if defined(CONFIG_USER_ONLY)
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2023-06-21 15:56:33 +02:00
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void tb_invalidate_phys_addr(hwaddr addr)
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2020-10-06 09:05:29 +02:00
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{
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mmap_lock();
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2022-10-05 18:26:26 +02:00
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tb_invalidate_phys_page(addr);
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2020-10-06 09:05:29 +02:00
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mmap_unlock();
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}
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#else
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void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
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{
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ram_addr_t ram_addr;
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MemoryRegion *mr;
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hwaddr l = 1;
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if (!tcg_enabled()) {
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return;
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}
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RCU_READ_LOCK_GUARD();
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mr = address_space_translate(as, addr, &addr, &l, false, attrs);
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if (!(memory_region_is_ram(mr)
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|| memory_region_is_romd(mr))) {
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return;
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}
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ram_addr = memory_region_get_ram_addr(mr) + addr;
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2022-10-05 18:26:26 +02:00
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tb_invalidate_phys_page(ram_addr);
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2020-10-06 09:05:29 +02:00
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}
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#endif
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/* enable or disable single step mode. EXCP_DEBUG is returned by the
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CPU loop after each instruction */
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void cpu_single_step(CPUState *cpu, int enabled)
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{
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if (cpu->singlestep_enabled != enabled) {
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cpu->singlestep_enabled = enabled;
|
2023-03-03 03:58:05 +01:00
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#if !defined(CONFIG_USER_ONLY)
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const AccelOpsClass *ops = cpus_get_accel();
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if (ops->update_guest_debug) {
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ops->update_guest_debug(cpu);
|
2020-10-06 09:05:29 +02:00
|
|
|
}
|
2023-03-03 03:58:05 +01:00
|
|
|
#endif
|
|
|
|
|
2021-07-01 17:10:53 +02:00
|
|
|
trace_breakpoint_singlestep(cpu->cpu_index, enabled);
|
2020-10-06 09:05:29 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_abort(CPUState *cpu, const char *fmt, ...)
|
|
|
|
{
|
|
|
|
va_list ap;
|
|
|
|
va_list ap2;
|
|
|
|
|
|
|
|
va_start(ap, fmt);
|
|
|
|
va_copy(ap2, ap);
|
|
|
|
fprintf(stderr, "qemu: fatal: ");
|
|
|
|
vfprintf(stderr, fmt, ap);
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
cpu_dump_state(cpu, stderr, CPU_DUMP_FPU | CPU_DUMP_CCOP);
|
|
|
|
if (qemu_log_separate()) {
|
2022-04-17 20:29:47 +02:00
|
|
|
FILE *logfile = qemu_log_trylock();
|
2022-04-17 20:29:49 +02:00
|
|
|
if (logfile) {
|
|
|
|
fprintf(logfile, "qemu: fatal: ");
|
|
|
|
vfprintf(logfile, fmt, ap2);
|
|
|
|
fprintf(logfile, "\n");
|
|
|
|
cpu_dump_state(cpu, logfile, CPU_DUMP_FPU | CPU_DUMP_CCOP);
|
|
|
|
qemu_log_unlock(logfile);
|
|
|
|
}
|
2020-10-06 09:05:29 +02:00
|
|
|
}
|
|
|
|
va_end(ap2);
|
|
|
|
va_end(ap);
|
|
|
|
replay_finish();
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
|
|
{
|
|
|
|
struct sigaction act;
|
|
|
|
sigfillset(&act.sa_mask);
|
|
|
|
act.sa_handler = SIG_DFL;
|
|
|
|
act.sa_flags = 0;
|
|
|
|
sigaction(SIGABRT, &act, NULL);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
abort();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* physical memory access (slow version, mainly for debug) */
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
2022-02-03 02:13:28 +01:00
|
|
|
int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
|
|
|
|
void *ptr, size_t len, bool is_write)
|
2020-10-06 09:05:29 +02:00
|
|
|
{
|
|
|
|
int flags;
|
2022-02-03 02:13:28 +01:00
|
|
|
vaddr l, page;
|
2020-10-06 09:05:29 +02:00
|
|
|
void * p;
|
|
|
|
uint8_t *buf = ptr;
|
|
|
|
|
|
|
|
while (len > 0) {
|
|
|
|
page = addr & TARGET_PAGE_MASK;
|
|
|
|
l = (page + TARGET_PAGE_SIZE) - addr;
|
|
|
|
if (l > len)
|
|
|
|
l = len;
|
|
|
|
flags = page_get_flags(page);
|
|
|
|
if (!(flags & PAGE_VALID))
|
|
|
|
return -1;
|
|
|
|
if (is_write) {
|
|
|
|
if (!(flags & PAGE_WRITE))
|
|
|
|
return -1;
|
|
|
|
/* XXX: this code should not depend on lock_user */
|
|
|
|
if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
|
|
|
|
return -1;
|
|
|
|
memcpy(p, buf, l);
|
|
|
|
unlock_user(p, addr, l);
|
|
|
|
} else {
|
|
|
|
if (!(flags & PAGE_READ))
|
|
|
|
return -1;
|
|
|
|
/* XXX: this code should not depend on lock_user */
|
|
|
|
if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
|
|
|
|
return -1;
|
|
|
|
memcpy(buf, p, l);
|
|
|
|
unlock_user(p, addr, 0);
|
|
|
|
}
|
|
|
|
len -= l;
|
|
|
|
buf += l;
|
|
|
|
addr += l;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
bool target_words_bigendian(void)
|
|
|
|
{
|
2023-09-07 13:35:00 +02:00
|
|
|
return TARGET_BIG_ENDIAN;
|
2020-10-06 09:05:29 +02:00
|
|
|
}
|
|
|
|
|
2023-04-24 18:04:33 +02:00
|
|
|
const char *target_name(void)
|
|
|
|
{
|
|
|
|
return TARGET_NAME;
|
|
|
|
}
|
|
|
|
|
2020-10-06 09:05:29 +02:00
|
|
|
void page_size_init(void)
|
|
|
|
{
|
|
|
|
/* NOTE: we can always suppose that qemu_host_page_size >=
|
|
|
|
TARGET_PAGE_SIZE */
|
|
|
|
if (qemu_host_page_size == 0) {
|
2022-03-23 16:57:22 +01:00
|
|
|
qemu_host_page_size = qemu_real_host_page_size();
|
2020-10-06 09:05:29 +02:00
|
|
|
}
|
|
|
|
if (qemu_host_page_size < TARGET_PAGE_SIZE) {
|
|
|
|
qemu_host_page_size = TARGET_PAGE_SIZE;
|
|
|
|
}
|
|
|
|
qemu_host_page_mask = -(intptr_t)qemu_host_page_size;
|
|
|
|
}
|