2007-04-30 03:48:07 +02:00
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/*
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* Intel XScale PXA255/270 OS Timers.
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*
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* Copyright (c) 2006 Openedhand Ltd.
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* Copyright (c) 2006 Thorsten Zitterell
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*
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* This code is licenced under the GPL.
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*/
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#include "vl.h"
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#define OSMR0 0x00
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#define OSMR1 0x04
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#define OSMR2 0x08
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#define OSMR3 0x0c
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#define OSMR4 0x80
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#define OSMR5 0x84
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#define OSMR6 0x88
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#define OSMR7 0x8c
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#define OSMR8 0x90
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#define OSMR9 0x94
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#define OSMR10 0x98
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#define OSMR11 0x9c
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#define OSCR 0x10 /* OS Timer Count */
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#define OSCR4 0x40
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#define OSCR5 0x44
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#define OSCR6 0x48
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#define OSCR7 0x4c
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#define OSCR8 0x50
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#define OSCR9 0x54
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#define OSCR10 0x58
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#define OSCR11 0x5c
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#define OSSR 0x14 /* Timer status register */
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#define OWER 0x18
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#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
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#define OMCR4 0xc0 /* OS Match Control registers */
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#define OMCR5 0xc4
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#define OMCR6 0xc8
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#define OMCR7 0xcc
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#define OMCR8 0xd0
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#define OMCR9 0xd4
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#define OMCR10 0xd8
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#define OMCR11 0xdc
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#define OSNR 0x20
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#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
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#define PXA27X_FREQ 3250000 /* 3.25 MHz */
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static int pxa2xx_timer4_freq[8] = {
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[0] = 0,
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[1] = 32768,
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[2] = 1000,
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[3] = 1,
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[4] = 1000000,
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/* [5] is the "Externally supplied clock". Assign if necessary. */
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[5 ... 7] = 0,
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};
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struct pxa2xx_timer0_s {
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uint32_t value;
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int level;
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qemu_irq irq;
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QEMUTimer *qtimer;
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int num;
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void *info;
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};
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struct pxa2xx_timer4_s {
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2007-05-09 00:51:00 +02:00
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struct pxa2xx_timer0_s tm;
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2007-04-30 03:48:07 +02:00
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int32_t oldclock;
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int32_t clock;
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uint64_t lastload;
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uint32_t freq;
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uint32_t control;
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};
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typedef struct {
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uint32_t base;
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int32_t clock;
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int32_t oldclock;
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uint64_t lastload;
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uint32_t freq;
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struct pxa2xx_timer0_s timer[4];
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struct pxa2xx_timer4_s *tm4;
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uint32_t events;
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uint32_t irq_enabled;
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uint32_t reset3;
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CPUState *cpustate;
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int64_t qemu_ticks;
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uint32_t snapshot;
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} pxa2xx_timer_info;
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static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
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{
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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int i;
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uint32_t now_vm;
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uint64_t new_qemu;
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now_vm = s->clock +
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muldiv64(now_qemu - s->lastload, s->freq, ticks_per_sec);
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for (i = 0; i < 4; i ++) {
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new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
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ticks_per_sec, s->freq);
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qemu_mod_timer(s->timer[i].qtimer, new_qemu);
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}
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}
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static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
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{
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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uint32_t now_vm;
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uint64_t new_qemu;
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static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
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int counter;
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if (s->tm4[n].control & (1 << 7))
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counter = n;
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else
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counter = counters[n];
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if (!s->tm4[counter].freq) {
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qemu_del_timer(s->timer[n].qtimer);
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return;
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}
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now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
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s->tm4[counter].lastload,
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s->tm4[counter].freq, ticks_per_sec);
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2007-05-09 00:51:00 +02:00
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new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
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2007-04-30 03:48:07 +02:00
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ticks_per_sec, s->tm4[counter].freq);
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qemu_mod_timer(s->timer[n].qtimer, new_qemu);
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}
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static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
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{
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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int tm = 0;
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offset -= s->base;
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switch (offset) {
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case OSMR3: tm ++;
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case OSMR2: tm ++;
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case OSMR1: tm ++;
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case OSMR0:
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return s->timer[tm].value;
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case OSMR11: tm ++;
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case OSMR10: tm ++;
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case OSMR9: tm ++;
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case OSMR8: tm ++;
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case OSMR7: tm ++;
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case OSMR6: tm ++;
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case OSMR5: tm ++;
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case OSMR4:
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if (!s->tm4)
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goto badreg;
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2007-05-09 00:51:00 +02:00
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return s->tm4[tm].tm.value;
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2007-04-30 03:48:07 +02:00
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case OSCR:
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return s->clock + muldiv64(qemu_get_clock(vm_clock) -
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s->lastload, s->freq, ticks_per_sec);
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case OSCR11: tm ++;
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case OSCR10: tm ++;
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case OSCR9: tm ++;
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case OSCR8: tm ++;
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case OSCR7: tm ++;
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case OSCR6: tm ++;
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case OSCR5: tm ++;
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case OSCR4:
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if (!s->tm4)
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goto badreg;
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if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
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if (s->tm4[tm - 1].freq)
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s->snapshot = s->tm4[tm - 1].clock + muldiv64(
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qemu_get_clock(vm_clock) -
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s->tm4[tm - 1].lastload,
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s->tm4[tm - 1].freq, ticks_per_sec);
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else
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s->snapshot = s->tm4[tm - 1].clock;
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}
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if (!s->tm4[tm].freq)
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return s->tm4[tm].clock;
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return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
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s->tm4[tm].lastload, s->tm4[tm].freq, ticks_per_sec);
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case OIER:
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return s->irq_enabled;
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case OSSR: /* Status register */
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return s->events;
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case OWER:
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return s->reset3;
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case OMCR11: tm ++;
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case OMCR10: tm ++;
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case OMCR9: tm ++;
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case OMCR8: tm ++;
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case OMCR7: tm ++;
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case OMCR6: tm ++;
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case OMCR5: tm ++;
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case OMCR4:
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if (!s->tm4)
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goto badreg;
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return s->tm4[tm].control;
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case OSNR:
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return s->snapshot;
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default:
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badreg:
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cpu_abort(cpu_single_env, "pxa2xx_timer_read: Bad offset "
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REG_FMT "\n", offset);
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}
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return 0;
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}
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static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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int i, tm = 0;
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pxa2xx_timer_info *s = (pxa2xx_timer_info *) opaque;
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offset -= s->base;
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switch (offset) {
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case OSMR3: tm ++;
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case OSMR2: tm ++;
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case OSMR1: tm ++;
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case OSMR0:
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s->timer[tm].value = value;
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pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
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break;
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case OSMR11: tm ++;
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case OSMR10: tm ++;
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case OSMR9: tm ++;
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case OSMR8: tm ++;
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case OSMR7: tm ++;
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case OSMR6: tm ++;
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case OSMR5: tm ++;
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case OSMR4:
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if (!s->tm4)
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goto badreg;
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2007-05-09 00:51:00 +02:00
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s->tm4[tm].tm.value = value;
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2007-04-30 03:48:07 +02:00
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pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
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break;
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case OSCR:
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s->oldclock = s->clock;
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s->lastload = qemu_get_clock(vm_clock);
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s->clock = value;
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pxa2xx_timer_update(s, s->lastload);
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break;
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case OSCR11: tm ++;
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case OSCR10: tm ++;
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case OSCR9: tm ++;
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case OSCR8: tm ++;
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case OSCR7: tm ++;
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case OSCR6: tm ++;
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case OSCR5: tm ++;
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case OSCR4:
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if (!s->tm4)
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goto badreg;
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s->tm4[tm].oldclock = s->tm4[tm].clock;
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s->tm4[tm].lastload = qemu_get_clock(vm_clock);
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s->tm4[tm].clock = value;
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pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
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break;
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case OIER:
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s->irq_enabled = value & 0xfff;
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break;
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case OSSR: /* Status register */
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s->events &= ~value;
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for (i = 0; i < 4; i ++, value >>= 1) {
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if (s->timer[i].level && (value & 1)) {
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s->timer[i].level = 0;
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qemu_irq_lower(s->timer[i].irq);
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}
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}
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if (s->tm4) {
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for (i = 0; i < 8; i ++, value >>= 1)
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2007-05-09 00:51:00 +02:00
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if (s->tm4[i].tm.level && (value & 1))
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s->tm4[i].tm.level = 0;
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2007-04-30 03:48:07 +02:00
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if (!(s->events & 0xff0))
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2007-05-09 00:51:00 +02:00
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qemu_irq_lower(s->tm4->tm.irq);
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2007-04-30 03:48:07 +02:00
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}
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break;
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case OWER: /* XXX: Reset on OSMR3 match? */
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s->reset3 = value;
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break;
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case OMCR7: tm ++;
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case OMCR6: tm ++;
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case OMCR5: tm ++;
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case OMCR4:
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if (!s->tm4)
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goto badreg;
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s->tm4[tm].control = value & 0x0ff;
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/* XXX Stop if running (shouldn't happen) */
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if ((value & (1 << 7)) || tm == 0)
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s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
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else {
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s->tm4[tm].freq = 0;
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pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
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}
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break;
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case OMCR11: tm ++;
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case OMCR10: tm ++;
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case OMCR9: tm ++;
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case OMCR8: tm += 4;
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if (!s->tm4)
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goto badreg;
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s->tm4[tm].control = value & 0x3ff;
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/* XXX Stop if running (shouldn't happen) */
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if ((value & (1 << 7)) || !(tm & 1))
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s->tm4[tm].freq =
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pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
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else {
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s->tm4[tm].freq = 0;
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pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
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}
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break;
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default:
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badreg:
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cpu_abort(cpu_single_env, "pxa2xx_timer_write: Bad offset "
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REG_FMT "\n", offset);
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}
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}
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static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
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pxa2xx_timer_read,
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pxa2xx_timer_read,
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pxa2xx_timer_read,
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};
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static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
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pxa2xx_timer_write,
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pxa2xx_timer_write,
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pxa2xx_timer_write,
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};
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static void pxa2xx_timer_tick(void *opaque)
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{
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struct pxa2xx_timer0_s *t = (struct pxa2xx_timer0_s *) opaque;
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pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->info;
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if (i->irq_enabled & (1 << t->num)) {
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t->level = 1;
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i->events |= 1 << t->num;
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qemu_irq_raise(t->irq);
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}
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if (t->num == 3)
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if (i->reset3 & 1) {
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i->reset3 = 0;
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cpu_reset(i->cpustate);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pxa2xx_timer_tick4(void *opaque)
|
|
|
|
{
|
|
|
|
struct pxa2xx_timer4_s *t = (struct pxa2xx_timer4_s *) opaque;
|
2007-05-09 00:51:00 +02:00
|
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|
pxa2xx_timer_info *i = (pxa2xx_timer_info *) t->tm.info;
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2007-04-30 03:48:07 +02:00
|
|
|
|
2007-05-09 00:51:00 +02:00
|
|
|
pxa2xx_timer_tick(&t->tm);
|
2007-04-30 03:48:07 +02:00
|
|
|
if (t->control & (1 << 3))
|
|
|
|
t->clock = 0;
|
|
|
|
if (t->control & (1 << 6))
|
2007-05-09 00:51:00 +02:00
|
|
|
pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
|
2007-04-30 03:48:07 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
|
|
|
|
qemu_irq *irqs, CPUState *cpustate)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int iomemtype;
|
|
|
|
pxa2xx_timer_info *s;
|
|
|
|
|
|
|
|
s = (pxa2xx_timer_info *) qemu_mallocz(sizeof(pxa2xx_timer_info));
|
|
|
|
s->base = base;
|
|
|
|
s->irq_enabled = 0;
|
|
|
|
s->oldclock = 0;
|
|
|
|
s->clock = 0;
|
|
|
|
s->lastload = qemu_get_clock(vm_clock);
|
|
|
|
s->reset3 = 0;
|
|
|
|
s->cpustate = cpustate;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i ++) {
|
|
|
|
s->timer[i].value = 0;
|
|
|
|
s->timer[i].irq = irqs[i];
|
|
|
|
s->timer[i].info = s;
|
|
|
|
s->timer[i].num = i;
|
|
|
|
s->timer[i].level = 0;
|
|
|
|
s->timer[i].qtimer = qemu_new_timer(vm_clock,
|
|
|
|
pxa2xx_timer_tick, &s->timer[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
iomemtype = cpu_register_io_memory(0, pxa2xx_timer_readfn,
|
|
|
|
pxa2xx_timer_writefn, s);
|
|
|
|
cpu_register_physical_memory(base, 0x00000fff, iomemtype);
|
|
|
|
return s;
|
|
|
|
}
|
|
|
|
|
|
|
|
void pxa25x_timer_init(target_phys_addr_t base,
|
|
|
|
qemu_irq *irqs, CPUState *cpustate)
|
|
|
|
{
|
|
|
|
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
|
|
|
|
s->freq = PXA25X_FREQ;
|
|
|
|
s->tm4 = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void pxa27x_timer_init(target_phys_addr_t base,
|
|
|
|
qemu_irq *irqs, qemu_irq irq4, CPUState *cpustate)
|
|
|
|
{
|
|
|
|
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs, cpustate);
|
|
|
|
int i;
|
|
|
|
s->freq = PXA27X_FREQ;
|
|
|
|
s->tm4 = (struct pxa2xx_timer4_s *) qemu_mallocz(8 *
|
|
|
|
sizeof(struct pxa2xx_timer4_s));
|
|
|
|
for (i = 0; i < 8; i ++) {
|
2007-05-09 00:51:00 +02:00
|
|
|
s->tm4[i].tm.value = 0;
|
|
|
|
s->tm4[i].tm.irq = irq4;
|
|
|
|
s->tm4[i].tm.info = s;
|
|
|
|
s->tm4[i].tm.num = i + 4;
|
|
|
|
s->tm4[i].tm.level = 0;
|
2007-04-30 03:48:07 +02:00
|
|
|
s->tm4[i].freq = 0;
|
|
|
|
s->tm4[i].control = 0x0;
|
2007-05-09 00:51:00 +02:00
|
|
|
s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
|
2007-04-30 03:48:07 +02:00
|
|
|
pxa2xx_timer_tick4, &s->tm4[i]);
|
|
|
|
}
|
|
|
|
}
|