2004-01-04 23:58:38 +01:00
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/*
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* PPC emulation helpers for qemu.
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*
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* Copyright (c) 2003 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <math.h>
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#include "exec.h"
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#define MEMSUFFIX _raw
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#include "op_helper_mem.h"
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2004-04-12 22:39:29 +02:00
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#if !defined(CONFIG_USER_ONLY)
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2004-01-04 23:58:38 +01:00
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#define MEMSUFFIX _user
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#include "op_helper_mem.h"
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#define MEMSUFFIX _kernel
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#include "op_helper_mem.h"
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#endif
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/*****************************************************************************/
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/* Exceptions processing helpers */
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2004-05-21 14:59:32 +02:00
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void cpu_loop_exit(void)
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2004-01-04 23:58:38 +01:00
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{
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2004-05-21 14:59:32 +02:00
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longjmp(env->jmp_env, 1);
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2004-01-04 23:58:38 +01:00
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}
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2004-05-21 14:59:32 +02:00
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void do_raise_exception_err (uint32_t exception, int error_code)
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2004-01-04 23:58:38 +01:00
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{
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2004-05-21 14:59:32 +02:00
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#if 0
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printf("Raise exception %3x code : %d\n", exception, error_code);
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#endif
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switch (exception) {
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case EXCP_EXTERNAL:
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case EXCP_DECR:
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printf("DECREMENTER & EXTERNAL exceptions should be hard interrupts !\n");
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if (msr_ee == 0)
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return;
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break;
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case EXCP_PROGRAM:
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if (error_code == EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
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return;
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break;
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default:
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break;
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2004-01-04 23:58:38 +01:00
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}
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2004-05-21 14:59:32 +02:00
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env->exception_index = exception;
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env->error_code = error_code;
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2004-01-04 23:58:38 +01:00
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cpu_loop_exit();
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}
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2004-05-21 14:59:32 +02:00
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void do_raise_exception (uint32_t exception)
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{
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do_raise_exception_err(exception, 0);
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2004-01-04 23:58:38 +01:00
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}
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/*****************************************************************************/
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/* Helpers for "fat" micro operations */
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/* Special registers load and store */
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void do_load_cr (void)
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{
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T0 = (env->crf[0] << 28) |
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(env->crf[1] << 24) |
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(env->crf[2] << 20) |
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(env->crf[3] << 16) |
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(env->crf[4] << 12) |
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(env->crf[5] << 8) |
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(env->crf[6] << 4) |
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(env->crf[7] << 0);
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}
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void do_store_cr (uint32_t mask)
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{
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int i, sh;
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for (i = 0, sh = 7; i < 8; i++, sh --) {
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if (mask & (1 << sh))
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env->crf[i] = (T0 >> (sh * 4)) & 0xF;
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}
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}
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void do_load_xer (void)
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{
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T0 = (xer_so << XER_SO) |
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(xer_ov << XER_OV) |
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(xer_ca << XER_CA) |
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(xer_bc << XER_BC);
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}
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void do_store_xer (void)
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{
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xer_so = (T0 >> XER_SO) & 0x01;
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xer_ov = (T0 >> XER_OV) & 0x01;
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xer_ca = (T0 >> XER_CA) & 0x01;
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xer_bc = (T0 >> XER_BC) & 0x1f;
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}
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void do_load_msr (void)
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{
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T0 = (msr_pow << MSR_POW) |
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(msr_ile << MSR_ILE) |
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(msr_ee << MSR_EE) |
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(msr_pr << MSR_PR) |
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(msr_fp << MSR_FP) |
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(msr_me << MSR_ME) |
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(msr_fe0 << MSR_FE0) |
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(msr_se << MSR_SE) |
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(msr_be << MSR_BE) |
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(msr_fe1 << MSR_FE1) |
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(msr_ip << MSR_IP) |
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(msr_ir << MSR_IR) |
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(msr_dr << MSR_DR) |
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(msr_ri << MSR_RI) |
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(msr_le << MSR_LE);
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}
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void do_store_msr (void)
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{
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2004-05-24 00:18:12 +02:00
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#if 1 // TRY
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2004-01-04 23:58:38 +01:00
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if (((T0 >> MSR_IR) & 0x01) != msr_ir ||
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2004-05-24 00:18:12 +02:00
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((T0 >> MSR_DR) & 0x01) != msr_dr ||
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((T0 >> MSR_PR) & 0x01) != msr_pr)
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{
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2004-01-04 23:58:38 +01:00
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do_tlbia();
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}
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2004-05-24 00:18:12 +02:00
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#endif
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2004-01-04 23:58:38 +01:00
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msr_pow = (T0 >> MSR_POW) & 0x03;
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msr_ile = (T0 >> MSR_ILE) & 0x01;
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msr_ee = (T0 >> MSR_EE) & 0x01;
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msr_pr = (T0 >> MSR_PR) & 0x01;
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msr_fp = (T0 >> MSR_FP) & 0x01;
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msr_me = (T0 >> MSR_ME) & 0x01;
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msr_fe0 = (T0 >> MSR_FE0) & 0x01;
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msr_se = (T0 >> MSR_SE) & 0x01;
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msr_be = (T0 >> MSR_BE) & 0x01;
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msr_fe1 = (T0 >> MSR_FE1) & 0x01;
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msr_ip = (T0 >> MSR_IP) & 0x01;
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msr_ir = (T0 >> MSR_IR) & 0x01;
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msr_dr = (T0 >> MSR_DR) & 0x01;
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msr_ri = (T0 >> MSR_RI) & 0x01;
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msr_le = (T0 >> MSR_LE) & 0x01;
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}
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/* shift right arithmetic helper */
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void do_sraw (void)
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{
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int32_t ret;
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xer_ca = 0;
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if (T1 & 0x20) {
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ret = (-1) * (T0 >> 31);
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2004-05-24 00:18:12 +02:00
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if (ret < 0 && (T0 & ~0x80000000) != 0)
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2004-01-04 23:58:38 +01:00
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xer_ca = 1;
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2004-05-24 00:18:12 +02:00
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#if 1 // TRY
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} else if (T1 == 0) {
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ret = T0;
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#endif
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2004-01-04 23:58:38 +01:00
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} else {
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ret = (int32_t)T0 >> (T1 & 0x1f);
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if (ret < 0 && ((int32_t)T0 & ((1 << T1) - 1)) != 0)
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xer_ca = 1;
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}
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2004-05-24 00:18:12 +02:00
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T0 = ret;
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2004-01-04 23:58:38 +01:00
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}
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/* Floating point operations helpers */
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void do_load_fpscr (void)
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{
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/* The 32 MSB of the target fpr are undefined.
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* They'll be zero...
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*/
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union {
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double d;
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struct {
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uint32_t u[2];
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} s;
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} u;
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int i;
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2005-02-16 00:06:19 +01:00
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#ifdef WORDS_BIGENDIAN
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#define WORD0 0
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#define WORD1 1
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#else
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#define WORD0 1
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#define WORD1 0
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#endif
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u.s.u[WORD0] = 0;
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u.s.u[WORD1] = 0;
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2004-01-04 23:58:38 +01:00
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for (i = 0; i < 8; i++)
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2005-02-16 00:06:19 +01:00
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u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
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2004-01-04 23:58:38 +01:00
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FT0 = u.d;
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}
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void do_store_fpscr (uint32_t mask)
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{
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/*
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* We use only the 32 LSB of the incoming fpr
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*/
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union {
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double d;
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struct {
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uint32_t u[2];
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} s;
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} u;
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2005-03-13 18:01:22 +01:00
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int i, rnd_type;
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2004-01-04 23:58:38 +01:00
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u.d = FT0;
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if (mask & 0x80)
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2005-02-16 00:06:19 +01:00
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env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
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2004-01-04 23:58:38 +01:00
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for (i = 1; i < 7; i++) {
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if (mask & (1 << (7 - i)))
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2005-02-16 00:06:19 +01:00
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env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
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2004-01-04 23:58:38 +01:00
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}
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/* TODO: update FEX & VX */
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/* Set rounding mode */
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switch (env->fpscr[0] & 0x3) {
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case 0:
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/* Best approximation (round to nearest) */
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2005-03-13 18:01:22 +01:00
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rnd_type = float_round_nearest_even;
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2004-01-04 23:58:38 +01:00
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break;
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case 1:
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/* Smaller magnitude (round toward zero) */
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2005-03-13 18:01:22 +01:00
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rnd_type = float_round_to_zero;
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2004-01-04 23:58:38 +01:00
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break;
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case 2:
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/* Round toward +infinite */
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2005-03-13 18:01:22 +01:00
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rnd_type = float_round_up;
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2004-01-04 23:58:38 +01:00
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break;
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2005-03-13 18:01:22 +01:00
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default:
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2004-01-04 23:58:38 +01:00
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case 3:
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/* Round toward -infinite */
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2005-03-13 18:01:22 +01:00
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rnd_type = float_round_down;
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2004-01-04 23:58:38 +01:00
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break;
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}
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2005-03-13 18:01:22 +01:00
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set_float_rounding_mode(rnd_type, &env->fp_status);
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2004-01-04 23:58:38 +01:00
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}
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void do_fctiw (void)
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{
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union {
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double d;
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uint64_t i;
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2005-03-13 18:01:22 +01:00
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} p;
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2004-01-04 23:58:38 +01:00
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2005-03-13 18:01:22 +01:00
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/* XXX: higher bits are not supposed to be significant.
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* to make tests easier, return the same as a real PPC 750 (aka G3)
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*/
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p.i = float64_to_int32(FT0, &env->fp_status);
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p.i |= 0xFFF80000ULL << 32;
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FT0 = p.d;
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2004-01-04 23:58:38 +01:00
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}
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void do_fctiwz (void)
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{
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union {
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double d;
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uint64_t i;
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2005-03-13 18:01:22 +01:00
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} p;
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/* XXX: higher bits are not supposed to be significant.
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* to make tests easier, return the same as a real PPC 750 (aka G3)
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*/
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p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
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p.i |= 0xFFF80000ULL << 32;
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FT0 = p.d;
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2004-01-04 23:58:38 +01:00
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}
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2004-05-24 00:18:12 +02:00
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void do_fnmadd (void)
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{
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2005-03-13 18:01:22 +01:00
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FT0 = (FT0 * FT1) + FT2;
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if (!isnan(FT0))
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FT0 = -FT0;
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2004-05-24 00:18:12 +02:00
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}
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void do_fnmsub (void)
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{
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2005-03-13 18:01:22 +01:00
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FT0 = (FT0 * FT1) - FT2;
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if (!isnan(FT0))
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FT0 = -FT0;
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2004-05-24 00:18:12 +02:00
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}
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2005-03-13 18:01:22 +01:00
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void do_fdiv (void)
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2004-04-26 21:48:05 +02:00
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{
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2005-03-13 18:01:22 +01:00
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if (FT0 == -0.0 && FT1 == -0.0)
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FT0 = 0.0 / 0.0;
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else
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FT0 /= FT1;
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2004-04-26 21:48:05 +02:00
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}
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2004-01-04 23:58:38 +01:00
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void do_fsqrt (void)
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{
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FT0 = sqrt(FT0);
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}
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void do_fres (void)
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{
|
2005-03-13 18:01:22 +01:00
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union {
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double d;
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uint64_t i;
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} p;
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if (isnormal(FT0)) {
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FT0 = (float)(1.0 / FT0);
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} else {
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p.d = FT0;
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if (p.i == 0x8000000000000000ULL) {
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p.i = 0xFFF0000000000000ULL;
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} else if (p.i == 0x0000000000000000ULL) {
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p.i = 0x7FF0000000000000ULL;
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} else if (isnan(FT0)) {
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p.i = 0x7FF8000000000000ULL;
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} else if (FT0 < 0.0) {
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p.i = 0x8000000000000000ULL;
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} else {
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p.i = 0x0000000000000000ULL;
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}
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|
|
|
FT0 = p.d;
|
|
|
|
}
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
2005-03-13 18:01:22 +01:00
|
|
|
void do_frsqrte (void)
|
2004-01-04 23:58:38 +01:00
|
|
|
{
|
2005-03-13 18:01:22 +01:00
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
|
|
|
} p;
|
|
|
|
|
|
|
|
if (isnormal(FT0) && FT0 > 0.0) {
|
|
|
|
FT0 = (float)(1.0 / sqrt(FT0));
|
|
|
|
} else {
|
|
|
|
p.d = FT0;
|
|
|
|
if (p.i == 0x8000000000000000ULL) {
|
|
|
|
p.i = 0xFFF0000000000000ULL;
|
|
|
|
} else if (p.i == 0x0000000000000000ULL) {
|
|
|
|
p.i = 0x7FF0000000000000ULL;
|
|
|
|
} else if (isnan(FT0)) {
|
|
|
|
if (!(p.i & 0x0008000000000000ULL))
|
|
|
|
p.i |= 0x000FFFFFFFFFFFFFULL;
|
|
|
|
} else if (FT0 < 0) {
|
|
|
|
p.i = 0x7FF8000000000000ULL;
|
|
|
|
} else {
|
|
|
|
p.i = 0x0000000000000000ULL;
|
|
|
|
}
|
|
|
|
FT0 = p.d;
|
|
|
|
}
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fsel (void)
|
|
|
|
{
|
|
|
|
if (FT0 >= 0)
|
|
|
|
FT0 = FT1;
|
2005-03-13 18:01:22 +01:00
|
|
|
else
|
|
|
|
FT0 = FT2;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fcmpu (void)
|
|
|
|
{
|
|
|
|
if (isnan(FT0) || isnan(FT1)) {
|
|
|
|
T0 = 0x01;
|
|
|
|
env->fpscr[4] |= 0x1;
|
|
|
|
env->fpscr[6] |= 0x1;
|
|
|
|
} else if (FT0 < FT1) {
|
|
|
|
T0 = 0x08;
|
|
|
|
} else if (FT0 > FT1) {
|
|
|
|
T0 = 0x04;
|
|
|
|
} else {
|
|
|
|
T0 = 0x02;
|
|
|
|
}
|
2004-05-24 00:18:12 +02:00
|
|
|
env->fpscr[3] = T0;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fcmpo (void)
|
|
|
|
{
|
|
|
|
env->fpscr[4] &= ~0x1;
|
|
|
|
if (isnan(FT0) || isnan(FT1)) {
|
|
|
|
T0 = 0x01;
|
|
|
|
env->fpscr[4] |= 0x1;
|
|
|
|
/* I don't know how to test "quiet" nan... */
|
|
|
|
if (0 /* || ! quiet_nan(...) */) {
|
|
|
|
env->fpscr[6] |= 0x1;
|
|
|
|
if (!(env->fpscr[1] & 0x8))
|
|
|
|
env->fpscr[4] |= 0x8;
|
|
|
|
} else {
|
|
|
|
env->fpscr[4] |= 0x8;
|
|
|
|
}
|
|
|
|
} else if (FT0 < FT1) {
|
|
|
|
T0 = 0x08;
|
|
|
|
} else if (FT0 > FT1) {
|
|
|
|
T0 = 0x04;
|
|
|
|
} else {
|
|
|
|
T0 = 0x02;
|
|
|
|
}
|
2004-05-24 00:18:12 +02:00
|
|
|
env->fpscr[3] = T0;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fabs (void)
|
|
|
|
{
|
2005-03-13 18:01:22 +01:00
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
|
|
|
} p;
|
|
|
|
|
|
|
|
p.d = FT0;
|
|
|
|
p.i &= ~0x8000000000000000ULL;
|
|
|
|
FT0 = p.d;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_fnabs (void)
|
|
|
|
{
|
2005-03-13 18:01:22 +01:00
|
|
|
union {
|
|
|
|
double d;
|
|
|
|
uint64_t i;
|
|
|
|
} p;
|
|
|
|
|
|
|
|
p.d = FT0;
|
|
|
|
p.i |= 0x8000000000000000ULL;
|
|
|
|
FT0 = p.d;
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Instruction cache invalidation helper */
|
2004-01-18 23:49:57 +01:00
|
|
|
#define ICACHE_LINE_SIZE 32
|
|
|
|
|
2004-05-24 00:18:12 +02:00
|
|
|
void do_check_reservation (void)
|
|
|
|
{
|
2005-02-08 22:24:36 +01:00
|
|
|
if ((env->reserve & ~0x03) == T0)
|
2004-05-24 00:18:12 +02:00
|
|
|
env->reserve = -1;
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
void do_icbi (void)
|
|
|
|
{
|
2004-01-18 23:49:57 +01:00
|
|
|
/* Invalidate one cache line */
|
|
|
|
T0 &= ~(ICACHE_LINE_SIZE - 1);
|
|
|
|
tb_invalidate_page_range(T0, T0 + ICACHE_LINE_SIZE);
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* TLB invalidation helpers */
|
|
|
|
void do_tlbia (void)
|
|
|
|
{
|
2004-02-04 00:39:42 +01:00
|
|
|
tlb_flush(env, 1);
|
2004-01-04 23:58:38 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_tlbie (void)
|
|
|
|
{
|
|
|
|
tlb_flush_page(env, T0);
|
|
|
|
}
|
|
|
|
|
2004-05-24 00:18:12 +02:00
|
|
|
void do_store_sr (uint32_t srnum)
|
|
|
|
{
|
|
|
|
#if defined (DEBUG_OP)
|
|
|
|
dump_store_sr(srnum);
|
|
|
|
#endif
|
|
|
|
#if 0 // TRY
|
|
|
|
{
|
|
|
|
uint32_t base, page;
|
|
|
|
|
|
|
|
base = srnum << 28;
|
|
|
|
for (page = base; page != base + 0x100000000; page += 0x1000)
|
|
|
|
tlb_flush_page(env, page);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
#endif
|
|
|
|
env->sr[srnum] = T0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* For BATs, we may not invalidate any TLBs if the change is only on
|
|
|
|
* protection bits for user mode.
|
|
|
|
*/
|
|
|
|
void do_store_ibat (int ul, int nr)
|
|
|
|
{
|
|
|
|
#if defined (DEBUG_OP)
|
|
|
|
dump_store_ibat(ul, nr);
|
|
|
|
#endif
|
|
|
|
#if 0 // TRY
|
|
|
|
{
|
|
|
|
uint32_t base, length, page;
|
|
|
|
|
|
|
|
base = env->IBAT[0][nr];
|
|
|
|
length = (((base >> 2) & 0x000007FF) + 1) << 17;
|
|
|
|
base &= 0xFFFC0000;
|
|
|
|
for (page = base; page != base + length; page += 0x1000)
|
|
|
|
tlb_flush_page(env, page);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
#endif
|
|
|
|
env->IBAT[ul][nr] = T0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void do_store_dbat (int ul, int nr)
|
|
|
|
{
|
|
|
|
#if defined (DEBUG_OP)
|
|
|
|
dump_store_dbat(ul, nr);
|
|
|
|
#endif
|
|
|
|
#if 0 // TRY
|
|
|
|
{
|
|
|
|
uint32_t base, length, page;
|
|
|
|
base = env->DBAT[0][nr];
|
|
|
|
length = (((base >> 2) & 0x000007FF) + 1) << 17;
|
|
|
|
base &= 0xFFFC0000;
|
|
|
|
for (page = base; page != base + length; page += 0x1000)
|
|
|
|
tlb_flush_page(env, page);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
tlb_flush(env, 1);
|
|
|
|
#endif
|
|
|
|
env->DBAT[ul][nr] = T0;
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
/*****************************************************************************/
|
|
|
|
/* Special helpers for debug */
|
2004-04-12 22:39:29 +02:00
|
|
|
void dump_state (void)
|
|
|
|
{
|
2004-10-09 20:08:01 +02:00
|
|
|
// cpu_dump_state(env, stdout, fprintf, 0);
|
2004-04-12 22:39:29 +02:00
|
|
|
}
|
|
|
|
|
2004-01-04 23:58:38 +01:00
|
|
|
void dump_rfi (void)
|
|
|
|
{
|
|
|
|
#if 0
|
2004-05-24 00:18:12 +02:00
|
|
|
printf("Return from interrupt => 0x%08x\n", env->nip);
|
2004-10-09 20:08:01 +02:00
|
|
|
// cpu_dump_state(env, stdout, fprintf, 0);
|
2004-01-04 23:58:38 +01:00
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
void dump_store_sr (int srnum)
|
|
|
|
{
|
|
|
|
#if 0
|
|
|
|
printf("%s: reg=%d 0x%08x\n", __func__, srnum, T0);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static void _dump_store_bat (char ID, int ul, int nr)
|
|
|
|
{
|
|
|
|
printf("Set %cBAT%d%c to 0x%08x (0x%08x)\n",
|
|
|
|
ID, nr, ul == 0 ? 'u' : 'l', T0, env->nip);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dump_store_ibat (int ul, int nr)
|
|
|
|
{
|
|
|
|
_dump_store_bat('I', ul, nr);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dump_store_dbat (int ul, int nr)
|
|
|
|
{
|
|
|
|
_dump_store_bat('D', ul, nr);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dump_store_tb (int ul)
|
|
|
|
{
|
|
|
|
printf("Set TB%c to 0x%08x\n", ul == 0 ? 'L' : 'U', T0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void dump_update_tb(uint32_t param)
|
|
|
|
{
|
|
|
|
#if 0
|
|
|
|
printf("Update TB: 0x%08x + %d => 0x%08x\n", T1, param, T0);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|