2016-06-29 13:47:03 +02:00
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#ifndef MMU_HASH64_H
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#define MMU_HASH64_H
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2013-03-12 01:31:06 +01:00
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#ifndef CONFIG_USER_ONLY
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#ifdef TARGET_PPC64
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2019-04-17 21:17:58 +02:00
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void dump_slb(PowerPCCPU *cpu);
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2016-01-27 01:07:29 +01:00
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int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
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target_ulong esid, target_ulong vsid);
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2021-06-21 14:51:13 +02:00
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bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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2021-06-28 15:36:10 +02:00
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hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
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2021-06-21 14:51:13 +02:00
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bool guest_visible);
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2016-01-15 06:12:09 +01:00
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void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
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target_ulong pte_index,
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target_ulong pte0, target_ulong pte1);
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2016-01-27 02:01:20 +01:00
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unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
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2016-07-01 09:10:10 +02:00
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uint64_t pte0, uint64_t pte1);
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2018-03-23 03:07:48 +01:00
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void ppc_hash64_init(PowerPCCPU *cpu);
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void ppc_hash64_finalize(PowerPCCPU *cpu);
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2013-03-12 01:31:06 +01:00
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#endif
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2013-03-12 01:31:18 +01:00
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/*
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* SLB definitions
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*/
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/* Bits in the SLB ESID word */
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#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
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#define SLB_ESID_V 0x0000000008000000ULL /* valid */
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/* Bits in the SLB VSID word */
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#define SLB_VSID_SHIFT 12
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#define SLB_VSID_SHIFT_1T 24
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#define SLB_VSID_SSIZE_SHIFT 62
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#define SLB_VSID_B 0xc000000000000000ULL
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#define SLB_VSID_B_256M 0x0000000000000000ULL
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#define SLB_VSID_B_1T 0x4000000000000000ULL
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#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
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2016-07-04 23:37:08 +02:00
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#define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
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2013-03-12 01:31:18 +01:00
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#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
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#define SLB_VSID_KS 0x0000000000000800ULL
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#define SLB_VSID_KP 0x0000000000000400ULL
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#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
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#define SLB_VSID_L 0x0000000000000100ULL
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2023-07-30 13:18:42 +02:00
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#define SLB_VSID_L_SHIFT PPC_BIT_NR(55)
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2013-03-12 01:31:18 +01:00
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#define SLB_VSID_C 0x0000000000000080ULL /* class */
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#define SLB_VSID_LP 0x0000000000000030ULL
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2023-07-30 13:18:42 +02:00
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#define SLB_VSID_LP_SHIFT PPC_BIT_NR(59)
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2013-03-12 01:31:18 +01:00
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#define SLB_VSID_ATTR 0x0000000000000FFFULL
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2015-01-26 15:21:58 +01:00
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#define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
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#define SLB_VSID_4K 0x0000000000000000ULL
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#define SLB_VSID_64K 0x0000000000000110ULL
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2016-01-15 07:54:42 +01:00
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#define SLB_VSID_16M 0x0000000000000100ULL
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#define SLB_VSID_16G 0x0000000000000120ULL
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2013-03-12 01:31:18 +01:00
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/*
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* Hash page table definitions
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*/
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2017-02-24 07:35:50 +01:00
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#define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL
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target/ppc: Eliminate htab_base and htab_mask variables
CPUPPCState includes fields htab_base and htab_mask which store the base
address (GPA) and size (as a mask) of the guest's hashed page table (HPT).
These are set when the SDR1 register is updated.
Keeping these in sync with the SDR1 is actually a little bit fiddly, and
probably not useful for performance, since keeping them expands the size of
CPUPPCState. It also makes some upcoming changes harder to implement.
This patch removes these fields, in favour of calculating them directly
from the SDR1 contents when necessary.
This does make a change to the behaviour of attempting to write a bad value
(invalid HPT size) to the SDR1 with an mtspr instruction. Previously, the
bad value would be stored in SDR1 and could be retrieved with a later
mfspr, but the HPT size as used by the softmmu would be, clamped to the
allowed values. Now, writing a bad value is treated as a no-op. An error
message is printed in both new and old versions.
I'm not sure which behaviour, if either, matches real hardware. I don't
think it matters that much, since it's pretty clear that if an OS writes
a bad value to SDR1, it's not going to boot.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
2017-02-24 06:36:44 +01:00
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#define SDR_64_HTABSIZE 0x000000000000001FULL
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2019-02-15 18:00:28 +01:00
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#define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
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2023-07-30 13:18:42 +02:00
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#define PATE0_PS PPC_BITMASK(56, 58)
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#define PATE0_GET_PS(dw0) (((dw0) & PATE0_PS) >> PPC_BIT_NR(58))
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2013-03-12 01:31:18 +01:00
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#define HPTES_PER_GROUP 8
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#define HASH_PTE_SIZE_64 16
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#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
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pseries: Implement HPT resizing
This patch implements hypercalls allowing a PAPR guest to resize its own
hash page table. This will eventually allow for more flexible memory
hotplug.
The implementation is partially asynchronous, handled in a special thread
running the hpt_prepare_thread() function. The state of a pending resize
is stored in SPAPR_MACHINE->pending_hpt.
The H_RESIZE_HPT_PREPARE hypercall will kick off creation of a new HPT, or,
if one is already in progress, monitor it for completion. If there is an
existing HPT resize in progress that doesn't match the size specified in
the call, it will cancel it, replacing it with a new one matching the
given size.
The H_RESIZE_HPT_COMMIT completes transition to a resized HPT, and can only
be called successfully once H_RESIZE_HPT_PREPARE has successfully
completed initialization of a new HPT. The guest must ensure that there
are no concurrent accesses to the existing HPT while this is called (this
effectively means stop_machine() for Linux guests).
For now H_RESIZE_HPT_COMMIT goes through the whole old HPT, rehashing each
HPTE into the new HPT. This can have quite high latency, but it seems to
be of the order of typical migration downtime latencies for HPTs of size
up to ~2GiB (which would be used in a 256GiB guest).
In future we probably want to move more of the rehashing to the "prepare"
phase, by having H_ENTER and other hcalls update both current and
pending HPTs. That's a project for another day, but should be possible
without any changes to the guest interface.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-05-12 07:46:49 +02:00
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#define HPTE64_V_SSIZE SLB_VSID_B
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#define HPTE64_V_SSIZE_256M SLB_VSID_B_256M
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#define HPTE64_V_SSIZE_1T SLB_VSID_B_1T
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2013-03-12 01:31:18 +01:00
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#define HPTE64_V_SSIZE_SHIFT 62
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#define HPTE64_V_AVPN_SHIFT 7
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#define HPTE64_V_AVPN 0x3fffffffffffff80ULL
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#define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
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2016-07-05 04:31:48 +02:00
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#define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
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pseries: Implement HPT resizing
This patch implements hypercalls allowing a PAPR guest to resize its own
hash page table. This will eventually allow for more flexible memory
hotplug.
The implementation is partially asynchronous, handled in a special thread
running the hpt_prepare_thread() function. The state of a pending resize
is stored in SPAPR_MACHINE->pending_hpt.
The H_RESIZE_HPT_PREPARE hypercall will kick off creation of a new HPT, or,
if one is already in progress, monitor it for completion. If there is an
existing HPT resize in progress that doesn't match the size specified in
the call, it will cancel it, replacing it with a new one matching the
given size.
The H_RESIZE_HPT_COMMIT completes transition to a resized HPT, and can only
be called successfully once H_RESIZE_HPT_PREPARE has successfully
completed initialization of a new HPT. The guest must ensure that there
are no concurrent accesses to the existing HPT while this is called (this
effectively means stop_machine() for Linux guests).
For now H_RESIZE_HPT_COMMIT goes through the whole old HPT, rehashing each
HPTE into the new HPT. This can have quite high latency, but it seems to
be of the order of typical migration downtime latencies for HPTs of size
up to ~2GiB (which would be used in a 256GiB guest).
In future we probably want to move more of the rehashing to the "prepare"
phase, by having H_ENTER and other hcalls update both current and
pending HPTs. That's a project for another day, but should be possible
without any changes to the guest interface.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-05-12 07:46:49 +02:00
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#define HPTE64_V_BOLTED 0x0000000000000010ULL
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2013-03-12 01:31:18 +01:00
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#define HPTE64_V_LARGE 0x0000000000000004ULL
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#define HPTE64_V_SECONDARY 0x0000000000000002ULL
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#define HPTE64_V_VALID 0x0000000000000001ULL
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#define HPTE64_R_PP0 0x8000000000000000ULL
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#define HPTE64_R_TS 0x4000000000000000ULL
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#define HPTE64_R_KEY_HI 0x3000000000000000ULL
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#define HPTE64_R_RPN_SHIFT 12
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#define HPTE64_R_RPN 0x0ffffffffffff000ULL
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#define HPTE64_R_FLAGS 0x00000000000003ffULL
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#define HPTE64_R_PP 0x0000000000000003ULL
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#define HPTE64_R_N 0x0000000000000004ULL
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#define HPTE64_R_G 0x0000000000000008ULL
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#define HPTE64_R_M 0x0000000000000010ULL
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#define HPTE64_R_I 0x0000000000000020ULL
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#define HPTE64_R_W 0x0000000000000040ULL
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#define HPTE64_R_WIMG 0x0000000000000078ULL
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#define HPTE64_R_C 0x0000000000000080ULL
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#define HPTE64_R_R 0x0000000000000100ULL
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#define HPTE64_R_KEY_LO 0x0000000000000e00ULL
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2017-01-13 07:28:23 +01:00
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#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 57) | \
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2013-03-12 01:31:47 +01:00
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(((x) & HPTE64_R_KEY_LO) >> 9))
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2013-03-12 01:31:18 +01:00
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#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
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#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
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2021-11-29 19:57:51 +01:00
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/* PTE offsets */
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#define HPTE64_DW1 (HASH_PTE_SIZE_64 / 2)
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#define HPTE64_DW1_R (HPTE64_DW1 + 6)
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#define HPTE64_DW1_C (HPTE64_DW1 + 7)
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2019-02-15 18:00:24 +01:00
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/* Format changes for ARCH v3 */
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#define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL
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#define HPTE64_R_3_0_SSIZE_SHIFT 58
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#define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)
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target/ppc: Cleanup HPTE accessors for 64-bit hash MMU
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
1) Within guest memory - when we're emulating a full guest CPU at the
hardware level (e.g. powernv, mac99, g3beige)
2) Within qemu, but outside guest memory - when we're emulating user and
supervisor instructions within TCG, but instead of emulating
the CPU's hypervisor mode, we just emulate a hypervisor's behaviour
(pseries in TCG or KVM-PR)
3) Within the host kernel - a pseries machine using KVM-HV
acceleration. Mostly accesses to the HPT are handled by KVM,
but there are a few cases where qemu needs to access it via a
special fd for the purpose.
In order to batch accesses to the fd in case (3), we use a somewhat awkward
ppc_hash64_start_access() / ppc_hash64_stop_access() pair, which for case
(3) reads / releases several HPTEs from the kernel as a batch (usually a
whole PTEG). For cases (1) & (2) it just returns an address value. The
actual HPTE load helpers then need to interpret the returned token
differently in the 3 cases.
This patch keeps the same basic structure, but simplfiies the details.
First start_access() / stop_access() are renamed to map_hptes() and
unmap_hptes() to make their operation more obvious. Second, map_hptes()
now always returns a qemu pointer, which can always be used in the same way
by the load_hpte() helpers. In case (1) it comes from address_space_map()
in case (2) directly from qemu's HPT buffer and in case (3) from a
temporary buffer read from the KVM fd.
While we're at it, make things a bit more consistent in terms of types and
variable names: avoid variables named 'index' (it shadows index(3) which
can lead to confusing results), use 'hwaddr ptex' for HPTE indices and
uint64_t for each of the HPTE words, use ptex throughout the call stack
instead of pte_offset in some places (we still need that at the bottom
layer, but nowhere else).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-27 06:03:41 +01:00
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struct ppc_hash_pte64 {
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uint64_t pte0, pte1;
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};
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const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
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hwaddr ptex, int n);
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void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
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hwaddr ptex, int n);
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2014-02-20 18:52:24 +01:00
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target/ppc: Cleanup HPTE accessors for 64-bit hash MMU
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
1) Within guest memory - when we're emulating a full guest CPU at the
hardware level (e.g. powernv, mac99, g3beige)
2) Within qemu, but outside guest memory - when we're emulating user and
supervisor instructions within TCG, but instead of emulating
the CPU's hypervisor mode, we just emulate a hypervisor's behaviour
(pseries in TCG or KVM-PR)
3) Within the host kernel - a pseries machine using KVM-HV
acceleration. Mostly accesses to the HPT are handled by KVM,
but there are a few cases where qemu needs to access it via a
special fd for the purpose.
In order to batch accesses to the fd in case (3), we use a somewhat awkward
ppc_hash64_start_access() / ppc_hash64_stop_access() pair, which for case
(3) reads / releases several HPTEs from the kernel as a batch (usually a
whole PTEG). For cases (1) & (2) it just returns an address value. The
actual HPTE load helpers then need to interpret the returned token
differently in the 3 cases.
This patch keeps the same basic structure, but simplfiies the details.
First start_access() / stop_access() are renamed to map_hptes() and
unmap_hptes() to make their operation more obvious. Second, map_hptes()
now always returns a qemu pointer, which can always be used in the same way
by the load_hpte() helpers. In case (1) it comes from address_space_map()
in case (2) directly from qemu's HPT buffer and in case (3) from a
temporary buffer read from the KVM fd.
While we're at it, make things a bit more consistent in terms of types and
variable names: avoid variables named 'index' (it shadows index(3) which
can lead to confusing results), use 'hwaddr ptex' for HPTE indices and
uint64_t for each of the HPTE words, use ptex throughout the call stack
instead of pte_offset in some places (we still need that at the bottom
layer, but nowhere else).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-27 06:03:41 +01:00
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static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu,
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const ppc_hash_pte64_t *hptes, int i)
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2013-03-12 01:31:19 +01:00
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{
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target/ppc: Cleanup HPTE accessors for 64-bit hash MMU
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
1) Within guest memory - when we're emulating a full guest CPU at the
hardware level (e.g. powernv, mac99, g3beige)
2) Within qemu, but outside guest memory - when we're emulating user and
supervisor instructions within TCG, but instead of emulating
the CPU's hypervisor mode, we just emulate a hypervisor's behaviour
(pseries in TCG or KVM-PR)
3) Within the host kernel - a pseries machine using KVM-HV
acceleration. Mostly accesses to the HPT are handled by KVM,
but there are a few cases where qemu needs to access it via a
special fd for the purpose.
In order to batch accesses to the fd in case (3), we use a somewhat awkward
ppc_hash64_start_access() / ppc_hash64_stop_access() pair, which for case
(3) reads / releases several HPTEs from the kernel as a batch (usually a
whole PTEG). For cases (1) & (2) it just returns an address value. The
actual HPTE load helpers then need to interpret the returned token
differently in the 3 cases.
This patch keeps the same basic structure, but simplfiies the details.
First start_access() / stop_access() are renamed to map_hptes() and
unmap_hptes() to make their operation more obvious. Second, map_hptes()
now always returns a qemu pointer, which can always be used in the same way
by the load_hpte() helpers. In case (1) it comes from address_space_map()
in case (2) directly from qemu's HPT buffer and in case (3) from a
temporary buffer read from the KVM fd.
While we're at it, make things a bit more consistent in terms of types and
variable names: avoid variables named 'index' (it shadows index(3) which
can lead to confusing results), use 'hwaddr ptex' for HPTE indices and
uint64_t for each of the HPTE words, use ptex throughout the call stack
instead of pte_offset in some places (we still need that at the bottom
layer, but nowhere else).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-27 06:03:41 +01:00
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return ldq_p(&(hptes[i].pte0));
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2013-03-12 01:31:19 +01:00
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}
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target/ppc: Cleanup HPTE accessors for 64-bit hash MMU
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
1) Within guest memory - when we're emulating a full guest CPU at the
hardware level (e.g. powernv, mac99, g3beige)
2) Within qemu, but outside guest memory - when we're emulating user and
supervisor instructions within TCG, but instead of emulating
the CPU's hypervisor mode, we just emulate a hypervisor's behaviour
(pseries in TCG or KVM-PR)
3) Within the host kernel - a pseries machine using KVM-HV
acceleration. Mostly accesses to the HPT are handled by KVM,
but there are a few cases where qemu needs to access it via a
special fd for the purpose.
In order to batch accesses to the fd in case (3), we use a somewhat awkward
ppc_hash64_start_access() / ppc_hash64_stop_access() pair, which for case
(3) reads / releases several HPTEs from the kernel as a batch (usually a
whole PTEG). For cases (1) & (2) it just returns an address value. The
actual HPTE load helpers then need to interpret the returned token
differently in the 3 cases.
This patch keeps the same basic structure, but simplfiies the details.
First start_access() / stop_access() are renamed to map_hptes() and
unmap_hptes() to make their operation more obvious. Second, map_hptes()
now always returns a qemu pointer, which can always be used in the same way
by the load_hpte() helpers. In case (1) it comes from address_space_map()
in case (2) directly from qemu's HPT buffer and in case (3) from a
temporary buffer read from the KVM fd.
While we're at it, make things a bit more consistent in terms of types and
variable names: avoid variables named 'index' (it shadows index(3) which
can lead to confusing results), use 'hwaddr ptex' for HPTE indices and
uint64_t for each of the HPTE words, use ptex throughout the call stack
instead of pte_offset in some places (we still need that at the bottom
layer, but nowhere else).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-27 06:03:41 +01:00
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static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
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const ppc_hash_pte64_t *hptes, int i)
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2013-03-12 01:31:19 +01:00
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{
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target/ppc: Cleanup HPTE accessors for 64-bit hash MMU
Accesses to the hashed page table (HPT) are complicated by the fact that
the HPT could be in one of three places:
1) Within guest memory - when we're emulating a full guest CPU at the
hardware level (e.g. powernv, mac99, g3beige)
2) Within qemu, but outside guest memory - when we're emulating user and
supervisor instructions within TCG, but instead of emulating
the CPU's hypervisor mode, we just emulate a hypervisor's behaviour
(pseries in TCG or KVM-PR)
3) Within the host kernel - a pseries machine using KVM-HV
acceleration. Mostly accesses to the HPT are handled by KVM,
but there are a few cases where qemu needs to access it via a
special fd for the purpose.
In order to batch accesses to the fd in case (3), we use a somewhat awkward
ppc_hash64_start_access() / ppc_hash64_stop_access() pair, which for case
(3) reads / releases several HPTEs from the kernel as a batch (usually a
whole PTEG). For cases (1) & (2) it just returns an address value. The
actual HPTE load helpers then need to interpret the returned token
differently in the 3 cases.
This patch keeps the same basic structure, but simplfiies the details.
First start_access() / stop_access() are renamed to map_hptes() and
unmap_hptes() to make their operation more obvious. Second, map_hptes()
now always returns a qemu pointer, which can always be used in the same way
by the load_hpte() helpers. In case (1) it comes from address_space_map()
in case (2) directly from qemu's HPT buffer and in case (3) from a
temporary buffer read from the KVM fd.
While we're at it, make things a bit more consistent in terms of types and
variable names: avoid variables named 'index' (it shadows index(3) which
can lead to confusing results), use 'hwaddr ptex' for HPTE indices and
uint64_t for each of the HPTE words, use ptex throughout the call stack
instead of pte_offset in some places (we still need that at the bottom
layer, but nowhere else).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-02-27 06:03:41 +01:00
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return ldq_p(&(hptes[i].pte1));
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2013-03-12 01:31:19 +01:00
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}
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2018-03-23 03:31:52 +01:00
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/*
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* MMU Options
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*/
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struct PPCHash64PageSize {
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uint32_t page_shift; /* Page shift (or 0) */
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uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
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};
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typedef struct PPCHash64PageSize PPCHash64PageSize;
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struct PPCHash64SegmentPageSizes {
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uint32_t page_shift; /* Base page shift of segment (or 0) */
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uint32_t slb_enc; /* SLB encoding for BookS */
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PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ];
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};
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struct PPCHash64Options {
|
2018-03-23 04:11:07 +01:00
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#define PPC_HASH64_1TSEG 0x00001
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#define PPC_HASH64_AMR 0x00002
|
2018-03-23 04:32:48 +01:00
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#define PPC_HASH64_CI_LARGEPAGE 0x00004
|
2018-03-23 04:11:07 +01:00
|
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unsigned flags;
|
2018-03-29 09:29:38 +02:00
|
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unsigned slb_size;
|
2018-03-23 03:31:52 +01:00
|
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PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
|
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};
|
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2018-03-23 03:59:20 +01:00
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extern const PPCHash64Options ppc_hash64_opts_basic;
|
2018-03-23 03:31:52 +01:00
|
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|
extern const PPCHash64Options ppc_hash64_opts_POWER7;
|
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|
2018-03-23 04:11:07 +01:00
|
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static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature)
|
|
|
|
|
{
|
|
|
|
|
return !!(cpu->hash64_opts->flags & feature);
|
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|
}
|
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2013-03-12 01:31:06 +01:00
|
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#endif /* CONFIG_USER_ONLY */
|
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|
2018-03-23 03:07:48 +01:00
|
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|
#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
|
|
|
|
|
static inline void ppc_hash64_init(PowerPCCPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
}
|
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|
|
|
static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
|
|
|
|
|
{
|
|
|
|
|
}
|
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|
|
#endif
|
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|
2016-06-29 13:47:03 +02:00
|
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|
#endif /* MMU_HASH64_H */
|