qemu-e2k/tests/tcg/riscv64/Makefile.target

# -*- Mode: makefile -*-
# RISC-V specific tweaks

VPATH += $(SRC_PATH)/tests/tcg/riscv64
TESTS += test-div
TESTS += noexec

# Disable compressed instructions for test-noc
TESTS += test-noc
test-noc: LDFLAGS = -nostdlib -static
run-test-noc: QEMU_OPTS += -cpu rv64,c=false

TESTS += test-aes
run-test-aes: QEMU_OPTS += -cpu rv64,zk=on

# Test for fcvtmod
TESTS += test-fcvtmod
test-fcvtmod: CFLAGS += -march=rv64imafdc
test-fcvtmod: LDFLAGS += -static
run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,Zfa=true
tests/tcg/riscv64: Add test for division Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210823195529.560295-3-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com> 2021-08-23 21:55:07 +02:00			`# -- Mode: makefile --`
			`# RISC-V specific tweaks`

			`VPATH += $(SRC_PATH)/tests/tcg/riscv64`
			`TESTS += test-div`
target/riscv: Make translator stop before the end of a page Right now the translator stops right after the end of a page, which breaks reporting of fault locations when the last instruction of a multi-insn translation block crosses a page boundary. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1155 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2022-08-19 03:00:30 +02:00			`TESTS += noexec`
target/riscv: Set pc_succ_insn for !rvc illegal insn Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org> [ Changes by AF: - Add missing run-plugin-test-noc-% line ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> 2022-12-03 18:57:44 +01:00
			`# Disable compressed instructions for test-noc`
			`TESTS += test-noc`
			`test-noc: LDFLAGS = -nostdlib -static`
			`run-test-noc: QEMU_OPTS += -cpu rv64,c=false`
tests/multiarch: Add test-aes Use a shared driver and backends for i386, aarch64, ppc64, riscv64. Acked-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2023-06-01 20:28:17 +02:00
			`TESTS += test-aes`
			`run-test-aes: QEMU_OPTS += -cpu rv64,zk=on`
riscv: Add support for the Zfa extension This patch introduces the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of float register bigger than XLEN * Quiet comparison instructions (fleq/fltq) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) Since QEMU does not support the RISC-V quad-precision floating-point ISA extension (Q), this patch does not include the instructions that depend on this extension. All other instructions are included in this patch. The Zfa specification can be found here: https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex The Zfa specifciation is frozen and is in public review since May 3, 2023: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg The patch also includes a TCG test for the fcvtmod.w.d instruction. The test cases test for correct results and flag behaviour. Note, that the Zfa specification requires fcvtmod's flag behaviour to be identical to a fcvt with the same operands (which is also tested). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230710071243.282464-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> 2023-07-10 09:12:43 +02:00
			`# Test for fcvtmod`
			`TESTS += test-fcvtmod`
			`test-fcvtmod: CFLAGS += -march=rv64imafdc`
			`test-fcvtmod: LDFLAGS += -static`
			`run-test-fcvtmod: QEMU_OPTS += -cpu rv64,d=true,Zfa=true`