qemu-e2k/target/riscv/cpu-param.h

/*
 * RISC-V cpu parameters for qemu.
 *
 * Copyright (c) 2017-2018 SiFive, Inc.
 * SPDX-License-Identifier: GPL-2.0+
 */

#ifndef RISCV_CPU_PARAM_H
#define RISCV_CPU_PARAM_H 1

#if defined(TARGET_RISCV64)
# define TARGET_LONG_BITS 64
# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
#elif defined(TARGET_RISCV32)
# define TARGET_LONG_BITS 32
# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
/*
 * The current MMU Modes are:
 *  - U mode 0b000
 *  - S mode 0b001
 *  - M mode 0b011
 *  - U mode HLV/HLVX/HSV 0b100
 *  - S mode HLV/HLVX/HSV 0b101
 *  - M mode HLV/HLVX/HSV 0b111
 */
#define NB_MMU_MODES 8

#endif
tcg: Split out target/arch/cpu-param.h For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2019-03-22 19:51:19 +01:00			`/*`
			`* RISC-V cpu parameters for qemu.`
			`*`
			`* Copyright (c) 2017-2018 SiFive, Inc.`
			`* SPDX-License-Identifier: GPL-2.0+`
			`*/`

			`#ifndef RISCV_CPU_PARAM_H`
			`#define RISCV_CPU_PARAM_H 1`

			`#if defined(TARGET_RISCV64)`
			`# define TARGET_LONG_BITS 64`
			`# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */`
			`# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */`
			`#elif defined(TARGET_RISCV32)`
			`# define TARGET_LONG_BITS 32`
			`# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */`
			`# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */`
			`#endif`
			`#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */`
target/riscv: Add a virtualised MMU Mode Add a new MMU mode that includes the current virt mode. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 4b301bc0ea36da962fc1605371b65019ac3073df.1604464950.git.alistair.francis@wdc.com 2020-11-04 05:43:23 +01:00			`/*`
			`* The current MMU Modes are:`
			`* - U mode 0b000`
			`* - S mode 0b001`
			`* - M mode 0b011`
			`* - U mode HLV/HLVX/HSV 0b100`
			`* - S mode HLV/HLVX/HSV 0b101`
			`* - M mode HLV/HLVX/HSV 0b111`
			`*/`
			`#define NB_MMU_MODES 8`
tcg: Split out target/arch/cpu-param.h For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> 2019-03-22 19:51:19 +01:00
			`#endif`